3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/cache.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/ptrace.h>
36 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
37 #define LOAD_BAT(n, reg, RA, RB) \
38 /* see the comment for clear_bats() -- Cort */ \
40 mtspr SPRN_IBAT##n##U,RA; \
41 mtspr SPRN_DBAT##n##U,RA; \
42 lwz RA,(n*16)+0(reg); \
43 lwz RB,(n*16)+4(reg); \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB; \
47 lwz RA,(n*16)+8(reg); \
48 lwz RB,(n*16)+12(reg); \
49 mtspr SPRN_DBAT##n##U,RA; \
50 mtspr SPRN_DBAT##n##L,RB; \
53 .section .text.head, "ax"
54 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
55 .stabs "head_32.S",N_SO,0,0,0f
60 * _start is defined this way because the XCOFF loader in the OpenFirmware
61 * on the powermac expects the entry point to be a procedure descriptor.
65 * These are here for legacy reasons, the kernel used to
66 * need to look like a coff function entry for the pmac
67 * but we're always started by some kind of bootloader now.
70 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
71 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
75 * Enter here with the kernel text, data and bss loaded starting at
76 * 0, running with virtual == physical mapping.
77 * r5 points to the prom entry point (the client interface handler
78 * address). Address translation is turned on, with the prom
79 * managing the hash table. Interrupts are disabled. The stack
80 * pointer (r1) points to just below the end of the half-meg region
81 * from 0x380000 - 0x400000, which is mapped in already.
83 * If we are booted from MacOS via BootX, we enter with the kernel
84 * image loaded somewhere, and the following values in registers:
85 * r3: 'BooX' (0x426f6f58)
86 * r4: virtual address of boot_infos_t
90 * This is jumped to on prep systems right after the kernel is relocated
91 * to its proper place in memory by the boot loader. The expected layout
93 * r3: ptr to residual data
94 * r4: initrd_start or if no initrd then 0
95 * r5: initrd_end - unused if r4 is 0
96 * r6: Start of command line string
97 * r7: End of command line string
99 * This just gets a minimal mmu environment setup so we can call
100 * start_here() to do the real work.
107 * We have to do any OF calls before we map ourselves to KERNELBASE,
108 * because OF may have I/O devices mapped into that area
109 * (particularly on CHRP).
114 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
115 /* find out where we are now */
117 0: mflr r8 /* r8 = runtime addr here */
118 addis r8,r8,(_stext - 0b)@ha
119 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
121 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
123 /* We never return. We also hit that trap if trying to boot
124 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
128 * Check for BootX signature when supporting PowerMac and branch to
129 * appropriate trampoline if it's present
131 #ifdef CONFIG_PPC_PMAC
138 #endif /* CONFIG_PPC_PMAC */
140 1: mr r31,r3 /* save parameters */
145 * early_init() does the early machine identification and does
146 * the necessary low-level setup and clears the BSS
147 * -- Cort <cort@fsmlabs.com>
151 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
152 * the physical address we are running at, returned by early_init()
160 #if defined(CONFIG_BOOTX_TEXT)
163 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
168 * Call setup_cpu for CPU 0 and initialize 6xx Idle
172 bl call_setup_cpu /* Call setup_cpu for this CPU */
176 #endif /* CONFIG_6xx */
180 * We need to run with _start at physical address 0.
181 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
182 * the exception vectors at 0 (and therefore this copy
183 * overwrites OF's exception vectors with our own).
184 * The MMU is off at this point.
188 addis r4,r3,KERNELBASE@h /* current address of _start */
189 lis r5,PHYSICAL_START@h
190 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
193 * we now have the 1st 16M of ram mapped with the bats.
194 * prep needs the mmu to be turned on here, but pmac already has it on.
195 * this shouldn't bother the pmac since it just gets turned on again
196 * as we jump to our code at KERNELBASE. -- Cort
197 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
198 * off, and in other cases, we now turn it off before changing BATs above.
202 ori r0,r0,MSR_DR|MSR_IR
205 ori r0,r0,start_here@l
208 RFI /* enables MMU */
211 * We need __secondary_hold as a place to hold the other cpus on
212 * an SMP machine, even when we are running a UP kernel.
214 . = 0xc0 /* for prep bootloader */
215 li r3,1 /* MTX only has 1 cpu */
216 .globl __secondary_hold
218 /* tell the master we're here */
219 stw r3,__secondary_hold_acknowledge@l(0)
222 /* wait until we're told to start */
225 /* our cpu # was at addr 0 - go */
226 mr r24,r3 /* cpu # */
230 #endif /* CONFIG_SMP */
232 .globl __secondary_hold_spinloop
233 __secondary_hold_spinloop:
235 .globl __secondary_hold_acknowledge
236 __secondary_hold_acknowledge:
240 * Exception entry code. This code runs with address translation
241 * turned off, i.e. using physical addresses.
242 * We assume sprg3 has the physical address of the current
243 * task's thread_struct.
245 #define EXCEPTION_PROLOG \
246 mtspr SPRN_SPRG0,r10; \
247 mtspr SPRN_SPRG1,r11; \
249 EXCEPTION_PROLOG_1; \
252 #define EXCEPTION_PROLOG_1 \
253 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
254 andi. r11,r11,MSR_PR; \
255 tophys(r11,r1); /* use tophys(r1) if kernel */ \
257 mfspr r11,SPRN_SPRG3; \
258 lwz r11,THREAD_INFO-THREAD(r11); \
259 addi r11,r11,THREAD_SIZE; \
261 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
264 #define EXCEPTION_PROLOG_2 \
266 stw r10,_CCR(r11); /* save registers */ \
267 stw r12,GPR12(r11); \
269 mfspr r10,SPRN_SPRG0; \
270 stw r10,GPR10(r11); \
271 mfspr r12,SPRN_SPRG1; \
272 stw r12,GPR11(r11); \
274 stw r10,_LINK(r11); \
275 mfspr r12,SPRN_SRR0; \
276 mfspr r9,SPRN_SRR1; \
279 tovirt(r1,r11); /* set new kernel sp */ \
280 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
281 MTMSRD(r10); /* (except for mach check in rtas) */ \
283 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
284 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
286 SAVE_4GPRS(3, r11); \
290 * Note: code which follows this uses cr0.eq (set if from kernel),
291 * r11, r12 (SRR0), and r9 (SRR1).
293 * Note2: once we have set r1 we are in a position to take exceptions
294 * again, and we could thus set MSR:RI at that point.
300 #define EXCEPTION(n, label, hdlr, xfer) \
304 addi r3,r1,STACK_FRAME_OVERHEAD; \
307 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
309 stw r10,_TRAP(r11); \
317 #define COPY_EE(d, s) rlwimi d,s,0,16,16
320 #define EXC_XFER_STD(n, hdlr) \
321 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
322 ret_from_except_full)
324 #define EXC_XFER_LITE(n, hdlr) \
325 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
328 #define EXC_XFER_EE(n, hdlr) \
329 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
330 ret_from_except_full)
332 #define EXC_XFER_EE_LITE(n, hdlr) \
333 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
337 /* core99 pmac starts the seconary here by changing the vector, and
338 putting it back to what it was (unknown_exception) when done. */
339 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
343 * On CHRP, this is complicated by the fact that we could get a
344 * machine check inside RTAS, and we have no guarantee that certain
345 * critical registers will have the values we expect. The set of
346 * registers that might have bad values includes all the GPRs
347 * and all the BATs. We indicate that we are in RTAS by putting
348 * a non-zero value, the address of the exception frame to use,
349 * in SPRG2. The machine check handler checks SPRG2 and uses its
350 * value if it is non-zero. If we ever needed to free up SPRG2,
351 * we could use a field in the thread_info or thread_struct instead.
352 * (Other exception handlers assume that r1 is a valid kernel stack
353 * pointer when we take an exception from supervisor mode.)
360 #ifdef CONFIG_PPC_CHRP
364 #endif /* CONFIG_PPC_CHRP */
366 7: EXCEPTION_PROLOG_2
367 addi r3,r1,STACK_FRAME_OVERHEAD
368 #ifdef CONFIG_PPC_CHRP
373 EXC_XFER_STD(0x200, machine_check_exception)
374 #ifdef CONFIG_PPC_CHRP
375 1: b machine_check_in_rtas
378 /* Data access exception. */
384 andis. r0,r10,0xa470 /* weird error? */
385 bne 1f /* if not, try to put a PTE */
386 mfspr r4,SPRN_DAR /* into the hash table */
387 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
389 1: lwz r5,_DSISR(r11) /* get DSISR value */
391 EXC_XFER_EE_LITE(0x300, handle_page_fault)
394 /* Instruction access exception. */
398 andis. r0,r9,0x4000 /* no pte found? */
399 beq 1f /* if so, try to put a PTE */
400 li r3,0 /* into the hash table */
401 mr r4,r12 /* SRR0 is fault address */
405 EXC_XFER_EE_LITE(0x400, handle_page_fault)
407 /* External interrupt */
408 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
410 /* Alignment exception */
418 addi r3,r1,STACK_FRAME_OVERHEAD
419 EXC_XFER_EE(0x600, alignment_exception)
421 /* Program check exception */
422 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
424 /* Floating-point unavailable */
429 * Certain Freescale cores don't have a FPU and treat fp instructions
430 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
433 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
436 bl load_up_fpu /* if from user, just load it up */
437 b fast_exception_return
438 1: addi r3,r1,STACK_FRAME_OVERHEAD
439 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
442 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
444 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
445 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
451 EXC_XFER_EE_LITE(0xc00, DoSyscall)
453 /* Single step - not used on 601 */
454 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
455 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
458 * The Altivec unavailable trap is at 0x0f20. Foo.
459 * We effectively remap it to 0x3000.
460 * We include an altivec unavailable exception vector even if
461 * not configured for Altivec, so that you can't panic a
462 * non-altivec kernel running on a machine with altivec just
463 * by executing an altivec instruction.
472 * Handle TLB miss for instruction on 603/603e.
473 * Note: we get an alternate set of r0 - r3 to use automatically.
479 * r1: linux style pte ( later becomes ppc hardware pte )
480 * r2: ptr to linux-style pte
484 /* Get PTE (linux-style) and check access */
486 lis r1,PAGE_OFFSET@h /* check if kernel address */
489 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
492 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
493 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
494 lis r2,swapper_pg_dir@ha /* if kernel address, use */
495 addi r2,r2,swapper_pg_dir@l /* kernel page table */
497 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
498 lwz r2,0(r2) /* get pmd entry */
499 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
500 beq- InstructionAddressInvalid /* return if no mapping */
501 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
502 lwz r3,0(r2) /* get linux-style pte */
503 andc. r1,r1,r3 /* check access & ~permission */
504 bne- InstructionAddressInvalid /* return if access not permitted */
505 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
507 * NOTE! We are assuming this is not an SMP system, otherwise
508 * we would need to update the pte atomically with lwarx/stwcx.
510 stw r3,0(r2) /* update PTE (accessed bit) */
511 /* Convert linux-style PTE to low word of PPC-style PTE */
512 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
513 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
514 and r1,r1,r2 /* writable if _RW and _DIRTY */
515 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
516 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
517 ori r1,r1,0xe14 /* clear out reserved bits and M */
518 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
522 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
525 InstructionAddressInvalid:
527 rlwinm r1,r3,9,6,6 /* Get load/store bit */
530 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
531 mtctr r0 /* Restore CTR */
532 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
535 mfspr r1,SPRN_IMISS /* Get failing address */
536 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
537 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
539 mtspr SPRN_DAR,r1 /* Set fault address */
540 mfmsr r0 /* Restore "normal" registers */
541 xoris r0,r0,MSR_TGPR>>16
542 mtcrf 0x80,r3 /* Restore CR0 */
547 * Handle TLB miss for DATA Load operation on 603/603e
553 * r1: linux style pte ( later becomes ppc hardware pte )
554 * r2: ptr to linux-style pte
558 /* Get PTE (linux-style) and check access */
560 lis r1,PAGE_OFFSET@h /* check if kernel address */
563 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
566 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
567 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
568 lis r2,swapper_pg_dir@ha /* if kernel address, use */
569 addi r2,r2,swapper_pg_dir@l /* kernel page table */
571 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
572 lwz r2,0(r2) /* get pmd entry */
573 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
574 beq- DataAddressInvalid /* return if no mapping */
575 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
576 lwz r3,0(r2) /* get linux-style pte */
577 andc. r1,r1,r3 /* check access & ~permission */
578 bne- DataAddressInvalid /* return if access not permitted */
579 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
581 * NOTE! We are assuming this is not an SMP system, otherwise
582 * we would need to update the pte atomically with lwarx/stwcx.
584 stw r3,0(r2) /* update PTE (accessed bit) */
585 /* Convert linux-style PTE to low word of PPC-style PTE */
586 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
587 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
588 and r1,r1,r2 /* writable if _RW and _DIRTY */
589 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
590 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
591 ori r1,r1,0xe14 /* clear out reserved bits and M */
592 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
596 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
601 rlwinm r1,r3,9,6,6 /* Get load/store bit */
604 mtctr r0 /* Restore CTR */
605 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
607 mfspr r1,SPRN_DMISS /* Get failing address */
608 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
609 beq 20f /* Jump if big endian */
611 20: mtspr SPRN_DAR,r1 /* Set fault address */
612 mfmsr r0 /* Restore "normal" registers */
613 xoris r0,r0,MSR_TGPR>>16
614 mtcrf 0x80,r3 /* Restore CR0 */
619 * Handle TLB miss for DATA Store on 603/603e
625 * r1: linux style pte ( later becomes ppc hardware pte )
626 * r2: ptr to linux-style pte
630 /* Get PTE (linux-style) and check access */
632 lis r1,PAGE_OFFSET@h /* check if kernel address */
635 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
638 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
639 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
640 lis r2,swapper_pg_dir@ha /* if kernel address, use */
641 addi r2,r2,swapper_pg_dir@l /* kernel page table */
643 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
644 lwz r2,0(r2) /* get pmd entry */
645 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
646 beq- DataAddressInvalid /* return if no mapping */
647 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
648 lwz r3,0(r2) /* get linux-style pte */
649 andc. r1,r1,r3 /* check access & ~permission */
650 bne- DataAddressInvalid /* return if access not permitted */
651 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
653 * NOTE! We are assuming this is not an SMP system, otherwise
654 * we would need to update the pte atomically with lwarx/stwcx.
656 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
657 /* Convert linux-style PTE to low word of PPC-style PTE */
658 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
659 li r1,0xe15 /* clear out reserved bits and M */
660 andc r1,r3,r1 /* PP = user? 2: 0 */
664 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
668 #ifndef CONFIG_ALTIVEC
669 #define altivec_assist_exception unknown_exception
672 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
673 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
674 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
675 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
676 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
677 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
678 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
679 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
680 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
681 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
682 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
683 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
684 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
685 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
686 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
687 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
688 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
689 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
690 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
691 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
692 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
693 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
694 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
695 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
696 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
697 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
698 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
699 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
700 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
702 .globl mol_trampoline
703 .set mol_trampoline, i0x2f00
709 #ifdef CONFIG_ALTIVEC
710 bne load_up_altivec /* if from user, just load it up */
711 #endif /* CONFIG_ALTIVEC */
712 addi r3,r1,STACK_FRAME_OVERHEAD
713 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
717 addi r3,r1,STACK_FRAME_OVERHEAD
718 EXC_XFER_STD(0xf00, performance_monitor_exception)
720 #ifdef CONFIG_ALTIVEC
721 /* Note that the AltiVec support is closely modeled after the FP
722 * support. Changes to one are likely to be applicable to the
726 * Disable AltiVec for the task which had AltiVec previously,
727 * and save its AltiVec registers in its thread_struct.
728 * Enables AltiVec for use in the kernel on return.
729 * On SMP we know the AltiVec units are free, since we give it up every
734 MTMSRD(r5) /* enable use of AltiVec now */
737 * For SMP, we don't do lazy AltiVec switching because it just gets too
738 * horrendously complex, especially when a task switches from one CPU
739 * to another. Instead we call giveup_altivec in switch_to.
743 addis r3,r6,last_task_used_altivec@ha
744 lwz r4,last_task_used_altivec@l(r3)
748 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
755 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
757 andc r4,r4,r10 /* disable altivec for previous task */
758 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
760 #endif /* CONFIG_SMP */
761 /* enable use of AltiVec after return */
763 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
766 stw r4,THREAD_USED_VR(r5)
773 stw r4,last_task_used_altivec@l(r3)
774 #endif /* CONFIG_SMP */
775 /* restore registers and return */
776 /* we haven't used ctr or xer or lr */
777 b fast_exception_return
780 * giveup_altivec(tsk)
781 * Disable AltiVec for the task given as the argument,
782 * and save the AltiVec registers in its thread_struct.
783 * Enables AltiVec for use in the kernel on return.
786 .globl giveup_altivec
791 MTMSRD(r5) /* enable use of AltiVec now */
794 beqlr- /* if no previous owner, done */
795 addi r3,r3,THREAD /* want THREAD of task */
798 SAVE_32VRS(0, r4, r3)
803 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
805 andc r4,r4,r3 /* disable AltiVec for previous task */
806 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
810 lis r4,last_task_used_altivec@ha
811 stw r5,last_task_used_altivec@l(r4)
812 #endif /* CONFIG_SMP */
814 #endif /* CONFIG_ALTIVEC */
817 * This code is jumped to from the startup code to copy
818 * the kernel image to physical address PHYSICAL_START.
821 addis r9,r26,klimit@ha /* fetch klimit */
823 addis r25,r25,-KERNELBASE@h
824 lis r3,PHYSICAL_START@h /* Destination base address */
825 li r6,0 /* Destination offset */
826 li r5,0x4000 /* # bytes of memory to copy */
827 bl copy_and_flush /* copy the first 0x4000 bytes */
828 addi r0,r3,4f@l /* jump to the address of 4f */
829 mtctr r0 /* in copy and do the rest. */
830 bctr /* jump to the copy */
832 bl copy_and_flush /* copy the rest */
836 * Copy routine used to copy the kernel to start at physical address 0
837 * and flush and invalidate the caches as needed.
838 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
839 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
841 _ENTRY(copy_and_flush)
844 4: li r0,L1_CACHE_BYTES/4
846 3: addi r6,r6,4 /* copy a cache line */
850 dcbst r6,r3 /* write it to memory */
852 icbi r6,r3 /* flush the icache line */
855 sync /* additional sync needed on g4 */
863 .globl __secondary_start_gemini
864 __secondary_start_gemini:
873 #endif /* CONFIG_GEMINI */
875 .globl __secondary_start_mpc86xx
876 __secondary_start_mpc86xx:
878 stw r3, __secondary_hold_acknowledge@l(0)
879 mr r24, r3 /* cpu # */
882 .globl __secondary_start_pmac_0
883 __secondary_start_pmac_0:
884 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
893 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
894 set to map the 0xf0000000 - 0xffffffff region */
896 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
901 .globl __secondary_start
903 /* Copy some CPU settings from CPU 0 */
904 bl __restore_cpu_setup
908 bl call_setup_cpu /* Call setup_cpu for this CPU */
912 #endif /* CONFIG_6xx */
914 /* get current_thread_info and current */
915 lis r1,secondary_ti@ha
917 lwz r1,secondary_ti@l(r1)
922 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
927 /* load up the MMU */
930 /* ptr to phys current thread */
932 addi r4,r4,THREAD /* phys address of our thread_struct */
936 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
938 /* enable MMU and jump to start_secondary */
941 lis r3,start_secondary@h
942 ori r3,r3,start_secondary@l
947 #endif /* CONFIG_SMP */
950 * Those generic dummy functions are kept for CPUs not
951 * included in CONFIG_6xx
953 #if !defined(CONFIG_6xx)
954 _ENTRY(__save_cpu_setup)
956 _ENTRY(__restore_cpu_setup)
958 #endif /* !defined(CONFIG_6xx) */
962 * Load stuff into the MMU. Intended to be called with
966 sync /* Force all PTE updates to finish */
968 tlbia /* Clear all TLB entries */
969 sync /* wait for tlbia/tlbie to finish */
970 TLBSYNC /* ... on all CPUs */
971 /* Load the SDR1 register (hash table base & size) */
976 li r0,16 /* load up segment register values */
977 mtctr r0 /* for context 0 */
978 lis r3,0x2000 /* Ku = 1, VSID = 0 */
981 addi r3,r3,0x111 /* increment VSID */
982 addis r4,r4,0x1000 /* address of next segment */
985 /* Load the BAT registers with the values set up by MMU_init.
986 MMU_init takes care of whether we're on a 601 or not. */
997 BEGIN_MMU_FTR_SECTION
1000 LOAD_BAT(6,r3,r4,r5)
1001 LOAD_BAT(7,r3,r4,r5)
1002 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1006 * This is where the main kernel code starts.
1009 /* ptr to current */
1011 ori r2,r2,init_task@l
1012 /* Set up for using our exception vectors */
1013 /* ptr to phys current thread */
1015 addi r4,r4,THREAD /* init task's THREAD */
1019 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1022 lis r1,init_thread_union@ha
1023 addi r1,r1,init_thread_union@l
1025 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1027 * Do early platform-specific initialization,
1028 * and set up the MMU.
1037 * Go back to running unmapped so we can load up new values
1038 * for SDR1 (hash table pointer) and the segment registers
1039 * and change to using our exception vectors.
1044 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1050 /* Load up the kernel context */
1053 #ifdef CONFIG_BDI_SWITCH
1054 /* Add helper information for the Abatron bdiGDB debugger.
1055 * We do this here because we know the mmu is disabled, and
1056 * will be enabled for real in just a few instructions.
1058 lis r5, abatron_pteptrs@h
1059 ori r5, r5, abatron_pteptrs@l
1060 stw r5, 0xf0(r0) /* This much match your Abatron config */
1061 lis r6, swapper_pg_dir@h
1062 ori r6, r6, swapper_pg_dir@l
1065 #endif /* CONFIG_BDI_SWITCH */
1067 /* Now turn on the MMU for real! */
1070 lis r3,start_kernel@h
1071 ori r3,r3,start_kernel@l
1078 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1080 * Set up the segment registers for a new context.
1082 _ENTRY(switch_mmu_context)
1083 lwz r3,MMCONTEXTID(r4)
1086 mulli r3,r3,897 /* multiply context by skew factor */
1087 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1088 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1089 li r0,NUM_USER_SEGMENTS
1092 #ifdef CONFIG_BDI_SWITCH
1093 /* Context switch the PTE pointer for the Abatron BDI2000.
1094 * The PGDIR is passed as second argument.
1097 lis r5, KERNELBASE@h
1105 addi r3,r3,0x111 /* next VSID */
1106 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1107 addis r4,r4,0x1000 /* address of next segment */
1113 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1117 * An undocumented "feature" of 604e requires that the v bit
1118 * be cleared before changing BAT values.
1120 * Also, newer IBM firmware does not clear bat3 and 4 so
1121 * this makes sure it's done.
1127 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1131 mtspr SPRN_DBAT0U,r10
1132 mtspr SPRN_DBAT0L,r10
1133 mtspr SPRN_DBAT1U,r10
1134 mtspr SPRN_DBAT1L,r10
1135 mtspr SPRN_DBAT2U,r10
1136 mtspr SPRN_DBAT2L,r10
1137 mtspr SPRN_DBAT3U,r10
1138 mtspr SPRN_DBAT3L,r10
1140 mtspr SPRN_IBAT0U,r10
1141 mtspr SPRN_IBAT0L,r10
1142 mtspr SPRN_IBAT1U,r10
1143 mtspr SPRN_IBAT1L,r10
1144 mtspr SPRN_IBAT2U,r10
1145 mtspr SPRN_IBAT2L,r10
1146 mtspr SPRN_IBAT3U,r10
1147 mtspr SPRN_IBAT3L,r10
1148 BEGIN_MMU_FTR_SECTION
1149 /* Here's a tweak: at this point, CPU setup have
1150 * not been called yet, so HIGH_BAT_EN may not be
1151 * set in HID0 for the 745x processors. However, it
1152 * seems that doesn't affect our ability to actually
1153 * write to these SPRs.
1155 mtspr SPRN_DBAT4U,r10
1156 mtspr SPRN_DBAT4L,r10
1157 mtspr SPRN_DBAT5U,r10
1158 mtspr SPRN_DBAT5L,r10
1159 mtspr SPRN_DBAT6U,r10
1160 mtspr SPRN_DBAT6L,r10
1161 mtspr SPRN_DBAT7U,r10
1162 mtspr SPRN_DBAT7L,r10
1163 mtspr SPRN_IBAT4U,r10
1164 mtspr SPRN_IBAT4L,r10
1165 mtspr SPRN_IBAT5U,r10
1166 mtspr SPRN_IBAT5L,r10
1167 mtspr SPRN_IBAT6U,r10
1168 mtspr SPRN_IBAT6L,r10
1169 mtspr SPRN_IBAT7U,r10
1170 mtspr SPRN_IBAT7L,r10
1171 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1176 1: addic. r10, r10, -0x1000
1183 addi r4, r3, __after_mmu_off - _start
1185 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1194 * Use the first pair of BAT registers to map the 1st 16MB
1195 * of RAM to PAGE_OFFSET. From this point on we can't safely
1199 lis r11,PAGE_OFFSET@h
1201 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1204 ori r11,r11,4 /* set up BAT registers for 601 */
1205 li r8,0x7f /* valid, block length = 8MB */
1206 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1207 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1208 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1209 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1210 mtspr SPRN_IBAT1U,r9
1211 mtspr SPRN_IBAT1L,r10
1217 ori r8,r8,0x12 /* R/W access, M=1 */
1219 ori r8,r8,2 /* R/W access */
1220 #endif /* CONFIG_SMP */
1221 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1223 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1224 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1225 mtspr SPRN_IBAT0L,r8
1226 mtspr SPRN_IBAT0U,r11
1231 #ifdef CONFIG_BOOTX_TEXT
1234 * setup the display bat prepared for us in prom.c
1239 addis r8,r3,disp_BAT@ha
1240 addi r8,r8,disp_BAT@l
1246 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1249 mtspr SPRN_DBAT3L,r8
1250 mtspr SPRN_DBAT3U,r11
1252 1: mtspr SPRN_IBAT3L,r8
1253 mtspr SPRN_IBAT3U,r11
1255 #endif /* CONFIG_BOOTX_TEXT */
1257 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1261 mtspr SPRN_DBAT1L, r8
1264 ori r11, r11, (BL_1M << 2) | 2
1265 mtspr SPRN_DBAT1U, r11
1271 /* Jump into the system reset for the rom.
1272 * We first disable the MMU, and then jump to the ROM reset address.
1274 * r3 is the board info structure, r4 is the location for starting.
1275 * I use this for building a small kernel that can load other kernels,
1276 * rather than trying to write or rely on a rom monitor that can tftp load.
1281 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1285 mfspr r11, SPRN_HID0
1287 ori r10,r10,HID0_ICE|HID0_DCE
1289 mtspr SPRN_HID0, r11
1291 li r5, MSR_ME|MSR_RI
1293 addis r6,r6,-KERNELBASE@h
1307 * We put a few things here that have to be page-aligned.
1308 * This stuff goes at the beginning of the data segment,
1309 * which is page-aligned.
1314 .globl empty_zero_page
1318 .globl swapper_pg_dir
1320 .space PGD_TABLE_SIZE
1322 .globl intercept_table
1324 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1325 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1326 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1327 .long 0, 0, 0, 0, 0, 0, 0, 0
1328 .long 0, 0, 0, 0, 0, 0, 0, 0
1329 .long 0, 0, 0, 0, 0, 0, 0, 0
1331 /* Room for two PTE pointers, usually the kernel and current user pointers
1332 * to their respective root page table.