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Merge branch 'ipi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip...
[deliverable/linux.git] / arch / powerpc / kernel / head_32.S
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
24 #include <asm/reg.h>
25 #include <asm/page.h>
26 #include <asm/mmu.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/cache.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/ptrace.h>
34 #include <asm/bug.h>
35
36 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
37 #define LOAD_BAT(n, reg, RA, RB) \
38 /* see the comment for clear_bats() -- Cort */ \
39 li RA,0; \
40 mtspr SPRN_IBAT##n##U,RA; \
41 mtspr SPRN_DBAT##n##U,RA; \
42 lwz RA,(n*16)+0(reg); \
43 lwz RB,(n*16)+4(reg); \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB; \
46 beq 1f; \
47 lwz RA,(n*16)+8(reg); \
48 lwz RB,(n*16)+12(reg); \
49 mtspr SPRN_DBAT##n##U,RA; \
50 mtspr SPRN_DBAT##n##L,RB; \
51 1:
52
53 .section .text.head, "ax"
54 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
55 .stabs "head_32.S",N_SO,0,0,0f
56 0:
57 _ENTRY(_stext);
58
59 /*
60 * _start is defined this way because the XCOFF loader in the OpenFirmware
61 * on the powermac expects the entry point to be a procedure descriptor.
62 */
63 _ENTRY(_start);
64 /*
65 * These are here for legacy reasons, the kernel used to
66 * need to look like a coff function entry for the pmac
67 * but we're always started by some kind of bootloader now.
68 * -- Cort
69 */
70 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
71 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
72 nop
73
74 /* PMAC
75 * Enter here with the kernel text, data and bss loaded starting at
76 * 0, running with virtual == physical mapping.
77 * r5 points to the prom entry point (the client interface handler
78 * address). Address translation is turned on, with the prom
79 * managing the hash table. Interrupts are disabled. The stack
80 * pointer (r1) points to just below the end of the half-meg region
81 * from 0x380000 - 0x400000, which is mapped in already.
82 *
83 * If we are booted from MacOS via BootX, we enter with the kernel
84 * image loaded somewhere, and the following values in registers:
85 * r3: 'BooX' (0x426f6f58)
86 * r4: virtual address of boot_infos_t
87 * r5: 0
88 *
89 * PREP
90 * This is jumped to on prep systems right after the kernel is relocated
91 * to its proper place in memory by the boot loader. The expected layout
92 * of the regs is:
93 * r3: ptr to residual data
94 * r4: initrd_start or if no initrd then 0
95 * r5: initrd_end - unused if r4 is 0
96 * r6: Start of command line string
97 * r7: End of command line string
98 *
99 * This just gets a minimal mmu environment setup so we can call
100 * start_here() to do the real work.
101 * -- Cort
102 */
103
104 .globl __start
105 __start:
106 /*
107 * We have to do any OF calls before we map ourselves to KERNELBASE,
108 * because OF may have I/O devices mapped into that area
109 * (particularly on CHRP).
110 */
111 cmpwi 0,r5,0
112 beq 1f
113
114 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
115 /* find out where we are now */
116 bcl 20,31,$+4
117 0: mflr r8 /* r8 = runtime addr here */
118 addis r8,r8,(_stext - 0b)@ha
119 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
120 bl prom_init
121 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
122
123 /* We never return. We also hit that trap if trying to boot
124 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
125 trap
126
127 /*
128 * Check for BootX signature when supporting PowerMac and branch to
129 * appropriate trampoline if it's present
130 */
131 #ifdef CONFIG_PPC_PMAC
132 1: lis r31,0x426f
133 ori r31,r31,0x6f58
134 cmpw 0,r3,r31
135 bne 1f
136 bl bootx_init
137 trap
138 #endif /* CONFIG_PPC_PMAC */
139
140 1: mr r31,r3 /* save parameters */
141 mr r30,r4
142 li r24,0 /* cpu # */
143
144 /*
145 * early_init() does the early machine identification and does
146 * the necessary low-level setup and clears the BSS
147 * -- Cort <cort@fsmlabs.com>
148 */
149 bl early_init
150
151 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
152 * the physical address we are running at, returned by early_init()
153 */
154 bl mmu_off
155 __after_mmu_off:
156 bl clear_bats
157 bl flush_tlbs
158
159 bl initial_bats
160 #if defined(CONFIG_BOOTX_TEXT)
161 bl setup_disp_bat
162 #endif
163 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
164 bl setup_cpm_bat
165 #endif
166
167 /*
168 * Call setup_cpu for CPU 0 and initialize 6xx Idle
169 */
170 bl reloc_offset
171 li r24,0 /* cpu# */
172 bl call_setup_cpu /* Call setup_cpu for this CPU */
173 #ifdef CONFIG_6xx
174 bl reloc_offset
175 bl init_idle_6xx
176 #endif /* CONFIG_6xx */
177
178
179 /*
180 * We need to run with _start at physical address 0.
181 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
182 * the exception vectors at 0 (and therefore this copy
183 * overwrites OF's exception vectors with our own).
184 * The MMU is off at this point.
185 */
186 bl reloc_offset
187 mr r26,r3
188 addis r4,r3,KERNELBASE@h /* current address of _start */
189 lis r5,PHYSICAL_START@h
190 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
191 bne relocate_kernel
192 /*
193 * we now have the 1st 16M of ram mapped with the bats.
194 * prep needs the mmu to be turned on here, but pmac already has it on.
195 * this shouldn't bother the pmac since it just gets turned on again
196 * as we jump to our code at KERNELBASE. -- Cort
197 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
198 * off, and in other cases, we now turn it off before changing BATs above.
199 */
200 turn_on_mmu:
201 mfmsr r0
202 ori r0,r0,MSR_DR|MSR_IR
203 mtspr SPRN_SRR1,r0
204 lis r0,start_here@h
205 ori r0,r0,start_here@l
206 mtspr SPRN_SRR0,r0
207 SYNC
208 RFI /* enables MMU */
209
210 /*
211 * We need __secondary_hold as a place to hold the other cpus on
212 * an SMP machine, even when we are running a UP kernel.
213 */
214 . = 0xc0 /* for prep bootloader */
215 li r3,1 /* MTX only has 1 cpu */
216 .globl __secondary_hold
217 __secondary_hold:
218 /* tell the master we're here */
219 stw r3,__secondary_hold_acknowledge@l(0)
220 #ifdef CONFIG_SMP
221 100: lwz r4,0(0)
222 /* wait until we're told to start */
223 cmpw 0,r4,r3
224 bne 100b
225 /* our cpu # was at addr 0 - go */
226 mr r24,r3 /* cpu # */
227 b __secondary_start
228 #else
229 b .
230 #endif /* CONFIG_SMP */
231
232 .globl __secondary_hold_spinloop
233 __secondary_hold_spinloop:
234 .long 0
235 .globl __secondary_hold_acknowledge
236 __secondary_hold_acknowledge:
237 .long -1
238
239 /*
240 * Exception entry code. This code runs with address translation
241 * turned off, i.e. using physical addresses.
242 * We assume sprg3 has the physical address of the current
243 * task's thread_struct.
244 */
245 #define EXCEPTION_PROLOG \
246 mtspr SPRN_SPRG0,r10; \
247 mtspr SPRN_SPRG1,r11; \
248 mfcr r10; \
249 EXCEPTION_PROLOG_1; \
250 EXCEPTION_PROLOG_2
251
252 #define EXCEPTION_PROLOG_1 \
253 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
254 andi. r11,r11,MSR_PR; \
255 tophys(r11,r1); /* use tophys(r1) if kernel */ \
256 beq 1f; \
257 mfspr r11,SPRN_SPRG3; \
258 lwz r11,THREAD_INFO-THREAD(r11); \
259 addi r11,r11,THREAD_SIZE; \
260 tophys(r11,r11); \
261 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
262
263
264 #define EXCEPTION_PROLOG_2 \
265 CLR_TOP32(r11); \
266 stw r10,_CCR(r11); /* save registers */ \
267 stw r12,GPR12(r11); \
268 stw r9,GPR9(r11); \
269 mfspr r10,SPRN_SPRG0; \
270 stw r10,GPR10(r11); \
271 mfspr r12,SPRN_SPRG1; \
272 stw r12,GPR11(r11); \
273 mflr r10; \
274 stw r10,_LINK(r11); \
275 mfspr r12,SPRN_SRR0; \
276 mfspr r9,SPRN_SRR1; \
277 stw r1,GPR1(r11); \
278 stw r1,0(r11); \
279 tovirt(r1,r11); /* set new kernel sp */ \
280 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
281 MTMSRD(r10); /* (except for mach check in rtas) */ \
282 stw r0,GPR0(r11); \
283 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
284 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
285 stw r10,8(r11); \
286 SAVE_4GPRS(3, r11); \
287 SAVE_2GPRS(7, r11)
288
289 /*
290 * Note: code which follows this uses cr0.eq (set if from kernel),
291 * r11, r12 (SRR0), and r9 (SRR1).
292 *
293 * Note2: once we have set r1 we are in a position to take exceptions
294 * again, and we could thus set MSR:RI at that point.
295 */
296
297 /*
298 * Exception vectors.
299 */
300 #define EXCEPTION(n, label, hdlr, xfer) \
301 . = n; \
302 label: \
303 EXCEPTION_PROLOG; \
304 addi r3,r1,STACK_FRAME_OVERHEAD; \
305 xfer(n, hdlr)
306
307 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
308 li r10,trap; \
309 stw r10,_TRAP(r11); \
310 li r10,MSR_KERNEL; \
311 copyee(r10, r9); \
312 bl tfer; \
313 i##n: \
314 .long hdlr; \
315 .long ret
316
317 #define COPY_EE(d, s) rlwimi d,s,0,16,16
318 #define NOCOPY(d, s)
319
320 #define EXC_XFER_STD(n, hdlr) \
321 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
322 ret_from_except_full)
323
324 #define EXC_XFER_LITE(n, hdlr) \
325 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
326 ret_from_except)
327
328 #define EXC_XFER_EE(n, hdlr) \
329 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
330 ret_from_except_full)
331
332 #define EXC_XFER_EE_LITE(n, hdlr) \
333 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
334 ret_from_except)
335
336 /* System reset */
337 /* core99 pmac starts the seconary here by changing the vector, and
338 putting it back to what it was (unknown_exception) when done. */
339 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
340
341 /* Machine check */
342 /*
343 * On CHRP, this is complicated by the fact that we could get a
344 * machine check inside RTAS, and we have no guarantee that certain
345 * critical registers will have the values we expect. The set of
346 * registers that might have bad values includes all the GPRs
347 * and all the BATs. We indicate that we are in RTAS by putting
348 * a non-zero value, the address of the exception frame to use,
349 * in SPRG2. The machine check handler checks SPRG2 and uses its
350 * value if it is non-zero. If we ever needed to free up SPRG2,
351 * we could use a field in the thread_info or thread_struct instead.
352 * (Other exception handlers assume that r1 is a valid kernel stack
353 * pointer when we take an exception from supervisor mode.)
354 * -- paulus.
355 */
356 . = 0x200
357 mtspr SPRN_SPRG0,r10
358 mtspr SPRN_SPRG1,r11
359 mfcr r10
360 #ifdef CONFIG_PPC_CHRP
361 mfspr r11,SPRN_SPRG2
362 cmpwi 0,r11,0
363 bne 7f
364 #endif /* CONFIG_PPC_CHRP */
365 EXCEPTION_PROLOG_1
366 7: EXCEPTION_PROLOG_2
367 addi r3,r1,STACK_FRAME_OVERHEAD
368 #ifdef CONFIG_PPC_CHRP
369 mfspr r4,SPRN_SPRG2
370 cmpwi cr1,r4,0
371 bne cr1,1f
372 #endif
373 EXC_XFER_STD(0x200, machine_check_exception)
374 #ifdef CONFIG_PPC_CHRP
375 1: b machine_check_in_rtas
376 #endif
377
378 /* Data access exception. */
379 . = 0x300
380 DataAccess:
381 EXCEPTION_PROLOG
382 mfspr r10,SPRN_DSISR
383 stw r10,_DSISR(r11)
384 andis. r0,r10,0xa470 /* weird error? */
385 bne 1f /* if not, try to put a PTE */
386 mfspr r4,SPRN_DAR /* into the hash table */
387 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
388 bl hash_page
389 1: lwz r5,_DSISR(r11) /* get DSISR value */
390 mfspr r4,SPRN_DAR
391 EXC_XFER_EE_LITE(0x300, handle_page_fault)
392
393
394 /* Instruction access exception. */
395 . = 0x400
396 InstructionAccess:
397 EXCEPTION_PROLOG
398 andis. r0,r9,0x4000 /* no pte found? */
399 beq 1f /* if so, try to put a PTE */
400 li r3,0 /* into the hash table */
401 mr r4,r12 /* SRR0 is fault address */
402 bl hash_page
403 1: mr r4,r12
404 mr r5,r9
405 EXC_XFER_EE_LITE(0x400, handle_page_fault)
406
407 /* External interrupt */
408 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
409
410 /* Alignment exception */
411 . = 0x600
412 Alignment:
413 EXCEPTION_PROLOG
414 mfspr r4,SPRN_DAR
415 stw r4,_DAR(r11)
416 mfspr r5,SPRN_DSISR
417 stw r5,_DSISR(r11)
418 addi r3,r1,STACK_FRAME_OVERHEAD
419 EXC_XFER_EE(0x600, alignment_exception)
420
421 /* Program check exception */
422 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
423
424 /* Floating-point unavailable */
425 . = 0x800
426 FPUnavailable:
427 BEGIN_FTR_SECTION
428 /*
429 * Certain Freescale cores don't have a FPU and treat fp instructions
430 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
431 */
432 b ProgramCheck
433 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
434 EXCEPTION_PROLOG
435 beq 1f
436 bl load_up_fpu /* if from user, just load it up */
437 b fast_exception_return
438 1: addi r3,r1,STACK_FRAME_OVERHEAD
439 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
440
441 /* Decrementer */
442 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
443
444 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
445 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
446
447 /* System call */
448 . = 0xc00
449 SystemCall:
450 EXCEPTION_PROLOG
451 EXC_XFER_EE_LITE(0xc00, DoSyscall)
452
453 /* Single step - not used on 601 */
454 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
455 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
456
457 /*
458 * The Altivec unavailable trap is at 0x0f20. Foo.
459 * We effectively remap it to 0x3000.
460 * We include an altivec unavailable exception vector even if
461 * not configured for Altivec, so that you can't panic a
462 * non-altivec kernel running on a machine with altivec just
463 * by executing an altivec instruction.
464 */
465 . = 0xf00
466 b PerformanceMonitor
467
468 . = 0xf20
469 b AltiVecUnavailable
470
471 /*
472 * Handle TLB miss for instruction on 603/603e.
473 * Note: we get an alternate set of r0 - r3 to use automatically.
474 */
475 . = 0x1000
476 InstructionTLBMiss:
477 /*
478 * r0: scratch
479 * r1: linux style pte ( later becomes ppc hardware pte )
480 * r2: ptr to linux-style pte
481 * r3: scratch
482 */
483 /* Get PTE (linux-style) and check access */
484 mfspr r3,SPRN_IMISS
485 lis r1,PAGE_OFFSET@h /* check if kernel address */
486 cmplw 0,r1,r3
487 mfspr r2,SPRN_SPRG3
488 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
489 lwz r2,PGDIR(r2)
490 bge- 112f
491 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
492 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
493 lis r2,swapper_pg_dir@ha /* if kernel address, use */
494 addi r2,r2,swapper_pg_dir@l /* kernel page table */
495 112: tophys(r2,r2)
496 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
497 lwz r2,0(r2) /* get pmd entry */
498 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
499 beq- InstructionAddressInvalid /* return if no mapping */
500 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
501 lwz r0,0(r2) /* get linux-style pte */
502 andc. r1,r1,r0 /* check access & ~permission */
503 bne- InstructionAddressInvalid /* return if access not permitted */
504 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
505 /*
506 * NOTE! We are assuming this is not an SMP system, otherwise
507 * we would need to update the pte atomically with lwarx/stwcx.
508 */
509 stw r0,0(r2) /* update PTE (accessed bit) */
510 /* Convert linux-style PTE to low word of PPC-style PTE */
511 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
512 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
513 and r1,r1,r2 /* writable if _RW and _DIRTY */
514 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
515 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
516 ori r1,r1,0xe04 /* clear out reserved bits */
517 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
518 BEGIN_FTR_SECTION
519 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
520 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
521 mtspr SPRN_RPA,r1
522 tlbli r3
523 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
524 mtcrf 0x80,r3
525 rfi
526 InstructionAddressInvalid:
527 mfspr r3,SPRN_SRR1
528 rlwinm r1,r3,9,6,6 /* Get load/store bit */
529
530 addis r1,r1,0x2000
531 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
532 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
533 or r2,r2,r1
534 mtspr SPRN_SRR1,r2
535 mfspr r1,SPRN_IMISS /* Get failing address */
536 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
537 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
538 xor r1,r1,r2
539 mtspr SPRN_DAR,r1 /* Set fault address */
540 mfmsr r0 /* Restore "normal" registers */
541 xoris r0,r0,MSR_TGPR>>16
542 mtcrf 0x80,r3 /* Restore CR0 */
543 mtmsr r0
544 b InstructionAccess
545
546 /*
547 * Handle TLB miss for DATA Load operation on 603/603e
548 */
549 . = 0x1100
550 DataLoadTLBMiss:
551 /*
552 * r0: scratch
553 * r1: linux style pte ( later becomes ppc hardware pte )
554 * r2: ptr to linux-style pte
555 * r3: scratch
556 */
557 /* Get PTE (linux-style) and check access */
558 mfspr r3,SPRN_DMISS
559 lis r1,PAGE_OFFSET@h /* check if kernel address */
560 cmplw 0,r1,r3
561 mfspr r2,SPRN_SPRG3
562 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
563 lwz r2,PGDIR(r2)
564 bge- 112f
565 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
566 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
567 lis r2,swapper_pg_dir@ha /* if kernel address, use */
568 addi r2,r2,swapper_pg_dir@l /* kernel page table */
569 112: tophys(r2,r2)
570 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
571 lwz r2,0(r2) /* get pmd entry */
572 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
573 beq- DataAddressInvalid /* return if no mapping */
574 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
575 lwz r0,0(r2) /* get linux-style pte */
576 andc. r1,r1,r0 /* check access & ~permission */
577 bne- DataAddressInvalid /* return if access not permitted */
578 ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
579 /*
580 * NOTE! We are assuming this is not an SMP system, otherwise
581 * we would need to update the pte atomically with lwarx/stwcx.
582 */
583 stw r0,0(r2) /* update PTE (accessed bit) */
584 /* Convert linux-style PTE to low word of PPC-style PTE */
585 rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */
586 rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
587 and r1,r1,r2 /* writable if _RW and _DIRTY */
588 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
589 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
590 ori r1,r1,0xe04 /* clear out reserved bits */
591 andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
592 BEGIN_FTR_SECTION
593 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
594 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
595 mtspr SPRN_RPA,r1
596 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
597 mtcrf 0x80,r2
598 BEGIN_MMU_FTR_SECTION
599 li r0,1
600 mfspr r1,SPRN_SPRG4
601 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
602 slw r0,r0,r2
603 xor r1,r0,r1
604 srw r0,r1,r2
605 mtspr SPRN_SPRG4,r1
606 mfspr r2,SPRN_SRR1
607 rlwimi r2,r0,31-14,14,14
608 mtspr SPRN_SRR1,r2
609 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
610 tlbld r3
611 rfi
612 DataAddressInvalid:
613 mfspr r3,SPRN_SRR1
614 rlwinm r1,r3,9,6,6 /* Get load/store bit */
615 addis r1,r1,0x2000
616 mtspr SPRN_DSISR,r1
617 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
618 mtspr SPRN_SRR1,r2
619 mfspr r1,SPRN_DMISS /* Get failing address */
620 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
621 beq 20f /* Jump if big endian */
622 xori r1,r1,3
623 20: mtspr SPRN_DAR,r1 /* Set fault address */
624 mfmsr r0 /* Restore "normal" registers */
625 xoris r0,r0,MSR_TGPR>>16
626 mtcrf 0x80,r3 /* Restore CR0 */
627 mtmsr r0
628 b DataAccess
629
630 /*
631 * Handle TLB miss for DATA Store on 603/603e
632 */
633 . = 0x1200
634 DataStoreTLBMiss:
635 /*
636 * r0: scratch
637 * r1: linux style pte ( later becomes ppc hardware pte )
638 * r2: ptr to linux-style pte
639 * r3: scratch
640 */
641 /* Get PTE (linux-style) and check access */
642 mfspr r3,SPRN_DMISS
643 lis r1,PAGE_OFFSET@h /* check if kernel address */
644 cmplw 0,r1,r3
645 mfspr r2,SPRN_SPRG3
646 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
647 lwz r2,PGDIR(r2)
648 bge- 112f
649 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
650 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
651 lis r2,swapper_pg_dir@ha /* if kernel address, use */
652 addi r2,r2,swapper_pg_dir@l /* kernel page table */
653 112: tophys(r2,r2)
654 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
655 lwz r2,0(r2) /* get pmd entry */
656 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
657 beq- DataAddressInvalid /* return if no mapping */
658 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
659 lwz r0,0(r2) /* get linux-style pte */
660 andc. r1,r1,r0 /* check access & ~permission */
661 bne- DataAddressInvalid /* return if access not permitted */
662 ori r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY
663 /*
664 * NOTE! We are assuming this is not an SMP system, otherwise
665 * we would need to update the pte atomically with lwarx/stwcx.
666 */
667 stw r0,0(r2) /* update PTE (accessed/dirty bits) */
668 /* Convert linux-style PTE to low word of PPC-style PTE */
669 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
670 li r1,0xe05 /* clear out reserved bits & PP lsb */
671 andc r1,r0,r1 /* PP = user? 2: 0 */
672 BEGIN_FTR_SECTION
673 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
674 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
675 mtspr SPRN_RPA,r1
676 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
677 mtcrf 0x80,r2
678 BEGIN_MMU_FTR_SECTION
679 li r0,1
680 mfspr r1,SPRN_SPRG4
681 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
682 slw r0,r0,r2
683 xor r1,r0,r1
684 srw r0,r1,r2
685 mtspr SPRN_SPRG4,r1
686 mfspr r2,SPRN_SRR1
687 rlwimi r2,r0,31-14,14,14
688 mtspr SPRN_SRR1,r2
689 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
690 tlbld r3
691 rfi
692
693 #ifndef CONFIG_ALTIVEC
694 #define altivec_assist_exception unknown_exception
695 #endif
696
697 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
698 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
699 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
700 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
701 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
702 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
703 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
704 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
705 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
706 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
707 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
708 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
709 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
710 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
711 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
712 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
713 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
714 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
715 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
716 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
717 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
718 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
719 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
720 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
721 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
722 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
723 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
724 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
725 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
726
727 .globl mol_trampoline
728 .set mol_trampoline, i0x2f00
729
730 . = 0x3000
731
732 AltiVecUnavailable:
733 EXCEPTION_PROLOG
734 #ifdef CONFIG_ALTIVEC
735 bne load_up_altivec /* if from user, just load it up */
736 #endif /* CONFIG_ALTIVEC */
737 addi r3,r1,STACK_FRAME_OVERHEAD
738 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
739
740 PerformanceMonitor:
741 EXCEPTION_PROLOG
742 addi r3,r1,STACK_FRAME_OVERHEAD
743 EXC_XFER_STD(0xf00, performance_monitor_exception)
744
745 #ifdef CONFIG_ALTIVEC
746 /* Note that the AltiVec support is closely modeled after the FP
747 * support. Changes to one are likely to be applicable to the
748 * other! */
749 load_up_altivec:
750 /*
751 * Disable AltiVec for the task which had AltiVec previously,
752 * and save its AltiVec registers in its thread_struct.
753 * Enables AltiVec for use in the kernel on return.
754 * On SMP we know the AltiVec units are free, since we give it up every
755 * switch. -- Kumar
756 */
757 mfmsr r5
758 oris r5,r5,MSR_VEC@h
759 MTMSRD(r5) /* enable use of AltiVec now */
760 isync
761 /*
762 * For SMP, we don't do lazy AltiVec switching because it just gets too
763 * horrendously complex, especially when a task switches from one CPU
764 * to another. Instead we call giveup_altivec in switch_to.
765 */
766 #ifndef CONFIG_SMP
767 tophys(r6,0)
768 addis r3,r6,last_task_used_altivec@ha
769 lwz r4,last_task_used_altivec@l(r3)
770 cmpwi 0,r4,0
771 beq 1f
772 add r4,r4,r6
773 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
774 SAVE_32VRS(0,r10,r4)
775 mfvscr vr0
776 li r10,THREAD_VSCR
777 stvx vr0,r10,r4
778 lwz r5,PT_REGS(r4)
779 add r5,r5,r6
780 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
781 lis r10,MSR_VEC@h
782 andc r4,r4,r10 /* disable altivec for previous task */
783 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
784 1:
785 #endif /* CONFIG_SMP */
786 /* enable use of AltiVec after return */
787 oris r9,r9,MSR_VEC@h
788 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
789 li r4,1
790 li r10,THREAD_VSCR
791 stw r4,THREAD_USED_VR(r5)
792 lvx vr0,r10,r5
793 mtvscr vr0
794 REST_32VRS(0,r10,r5)
795 #ifndef CONFIG_SMP
796 subi r4,r5,THREAD
797 sub r4,r4,r6
798 stw r4,last_task_used_altivec@l(r3)
799 #endif /* CONFIG_SMP */
800 /* restore registers and return */
801 /* we haven't used ctr or xer or lr */
802 b fast_exception_return
803
804 /*
805 * giveup_altivec(tsk)
806 * Disable AltiVec for the task given as the argument,
807 * and save the AltiVec registers in its thread_struct.
808 * Enables AltiVec for use in the kernel on return.
809 */
810
811 .globl giveup_altivec
812 giveup_altivec:
813 mfmsr r5
814 oris r5,r5,MSR_VEC@h
815 SYNC
816 MTMSRD(r5) /* enable use of AltiVec now */
817 isync
818 cmpwi 0,r3,0
819 beqlr- /* if no previous owner, done */
820 addi r3,r3,THREAD /* want THREAD of task */
821 lwz r5,PT_REGS(r3)
822 cmpwi 0,r5,0
823 SAVE_32VRS(0, r4, r3)
824 mfvscr vr0
825 li r4,THREAD_VSCR
826 stvx vr0,r4,r3
827 beq 1f
828 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
829 lis r3,MSR_VEC@h
830 andc r4,r4,r3 /* disable AltiVec for previous task */
831 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
832 1:
833 #ifndef CONFIG_SMP
834 li r5,0
835 lis r4,last_task_used_altivec@ha
836 stw r5,last_task_used_altivec@l(r4)
837 #endif /* CONFIG_SMP */
838 blr
839 #endif /* CONFIG_ALTIVEC */
840
841 /*
842 * This code is jumped to from the startup code to copy
843 * the kernel image to physical address PHYSICAL_START.
844 */
845 relocate_kernel:
846 addis r9,r26,klimit@ha /* fetch klimit */
847 lwz r25,klimit@l(r9)
848 addis r25,r25,-KERNELBASE@h
849 lis r3,PHYSICAL_START@h /* Destination base address */
850 li r6,0 /* Destination offset */
851 li r5,0x4000 /* # bytes of memory to copy */
852 bl copy_and_flush /* copy the first 0x4000 bytes */
853 addi r0,r3,4f@l /* jump to the address of 4f */
854 mtctr r0 /* in copy and do the rest. */
855 bctr /* jump to the copy */
856 4: mr r5,r25
857 bl copy_and_flush /* copy the rest */
858 b turn_on_mmu
859
860 /*
861 * Copy routine used to copy the kernel to start at physical address 0
862 * and flush and invalidate the caches as needed.
863 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
864 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
865 */
866 _ENTRY(copy_and_flush)
867 addi r5,r5,-4
868 addi r6,r6,-4
869 4: li r0,L1_CACHE_BYTES/4
870 mtctr r0
871 3: addi r6,r6,4 /* copy a cache line */
872 lwzx r0,r6,r4
873 stwx r0,r6,r3
874 bdnz 3b
875 dcbst r6,r3 /* write it to memory */
876 sync
877 icbi r6,r3 /* flush the icache line */
878 cmplw 0,r6,r5
879 blt 4b
880 sync /* additional sync needed on g4 */
881 isync
882 addi r5,r5,4
883 addi r6,r6,4
884 blr
885
886 #ifdef CONFIG_SMP
887 #ifdef CONFIG_GEMINI
888 .globl __secondary_start_gemini
889 __secondary_start_gemini:
890 mfspr r4,SPRN_HID0
891 ori r4,r4,HID0_ICFI
892 li r3,0
893 ori r3,r3,HID0_ICE
894 andc r4,r4,r3
895 mtspr SPRN_HID0,r4
896 sync
897 b __secondary_start
898 #endif /* CONFIG_GEMINI */
899
900 .globl __secondary_start_mpc86xx
901 __secondary_start_mpc86xx:
902 mfspr r3, SPRN_PIR
903 stw r3, __secondary_hold_acknowledge@l(0)
904 mr r24, r3 /* cpu # */
905 b __secondary_start
906
907 .globl __secondary_start_pmac_0
908 __secondary_start_pmac_0:
909 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
910 li r24,0
911 b 1f
912 li r24,1
913 b 1f
914 li r24,2
915 b 1f
916 li r24,3
917 1:
918 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
919 set to map the 0xf0000000 - 0xffffffff region */
920 mfmsr r0
921 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
922 SYNC
923 mtmsr r0
924 isync
925
926 .globl __secondary_start
927 __secondary_start:
928 /* Copy some CPU settings from CPU 0 */
929 bl __restore_cpu_setup
930
931 lis r3,-KERNELBASE@h
932 mr r4,r24
933 bl call_setup_cpu /* Call setup_cpu for this CPU */
934 #ifdef CONFIG_6xx
935 lis r3,-KERNELBASE@h
936 bl init_idle_6xx
937 #endif /* CONFIG_6xx */
938
939 /* get current_thread_info and current */
940 lis r1,secondary_ti@ha
941 tophys(r1,r1)
942 lwz r1,secondary_ti@l(r1)
943 tophys(r2,r1)
944 lwz r2,TI_TASK(r2)
945
946 /* stack */
947 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
948 li r0,0
949 tophys(r3,r1)
950 stw r0,0(r3)
951
952 /* load up the MMU */
953 bl load_up_mmu
954
955 /* ptr to phys current thread */
956 tophys(r4,r2)
957 addi r4,r4,THREAD /* phys address of our thread_struct */
958 CLR_TOP32(r4)
959 mtspr SPRN_SPRG3,r4
960 li r3,0
961 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
962
963 /* enable MMU and jump to start_secondary */
964 li r4,MSR_KERNEL
965 FIX_SRR1(r4,r5)
966 lis r3,start_secondary@h
967 ori r3,r3,start_secondary@l
968 mtspr SPRN_SRR0,r3
969 mtspr SPRN_SRR1,r4
970 SYNC
971 RFI
972 #endif /* CONFIG_SMP */
973
974 /*
975 * Those generic dummy functions are kept for CPUs not
976 * included in CONFIG_6xx
977 */
978 #if !defined(CONFIG_6xx)
979 _ENTRY(__save_cpu_setup)
980 blr
981 _ENTRY(__restore_cpu_setup)
982 blr
983 #endif /* !defined(CONFIG_6xx) */
984
985
986 /*
987 * Load stuff into the MMU. Intended to be called with
988 * IR=0 and DR=0.
989 */
990 load_up_mmu:
991 sync /* Force all PTE updates to finish */
992 isync
993 tlbia /* Clear all TLB entries */
994 sync /* wait for tlbia/tlbie to finish */
995 TLBSYNC /* ... on all CPUs */
996 /* Load the SDR1 register (hash table base & size) */
997 lis r6,_SDR1@ha
998 tophys(r6,r6)
999 lwz r6,_SDR1@l(r6)
1000 mtspr SPRN_SDR1,r6
1001 li r0,16 /* load up segment register values */
1002 mtctr r0 /* for context 0 */
1003 lis r3,0x2000 /* Ku = 1, VSID = 0 */
1004 li r4,0
1005 3: mtsrin r3,r4
1006 addi r3,r3,0x111 /* increment VSID */
1007 addis r4,r4,0x1000 /* address of next segment */
1008 bdnz 3b
1009
1010 /* Load the BAT registers with the values set up by MMU_init.
1011 MMU_init takes care of whether we're on a 601 or not. */
1012 mfpvr r3
1013 srwi r3,r3,16
1014 cmpwi r3,1
1015 lis r3,BATS@ha
1016 addi r3,r3,BATS@l
1017 tophys(r3,r3)
1018 LOAD_BAT(0,r3,r4,r5)
1019 LOAD_BAT(1,r3,r4,r5)
1020 LOAD_BAT(2,r3,r4,r5)
1021 LOAD_BAT(3,r3,r4,r5)
1022 BEGIN_MMU_FTR_SECTION
1023 LOAD_BAT(4,r3,r4,r5)
1024 LOAD_BAT(5,r3,r4,r5)
1025 LOAD_BAT(6,r3,r4,r5)
1026 LOAD_BAT(7,r3,r4,r5)
1027 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1028 blr
1029
1030 /*
1031 * This is where the main kernel code starts.
1032 */
1033 start_here:
1034 /* ptr to current */
1035 lis r2,init_task@h
1036 ori r2,r2,init_task@l
1037 /* Set up for using our exception vectors */
1038 /* ptr to phys current thread */
1039 tophys(r4,r2)
1040 addi r4,r4,THREAD /* init task's THREAD */
1041 CLR_TOP32(r4)
1042 mtspr SPRN_SPRG3,r4
1043 li r3,0
1044 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1045
1046 /* stack */
1047 lis r1,init_thread_union@ha
1048 addi r1,r1,init_thread_union@l
1049 li r0,0
1050 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1051 /*
1052 * Do early platform-specific initialization,
1053 * and set up the MMU.
1054 */
1055 mr r3,r31
1056 mr r4,r30
1057 bl machine_init
1058 bl __save_cpu_setup
1059 bl MMU_init
1060
1061 /*
1062 * Go back to running unmapped so we can load up new values
1063 * for SDR1 (hash table pointer) and the segment registers
1064 * and change to using our exception vectors.
1065 */
1066 lis r4,2f@h
1067 ori r4,r4,2f@l
1068 tophys(r4,r4)
1069 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1070 FIX_SRR1(r3,r5)
1071 mtspr SPRN_SRR0,r4
1072 mtspr SPRN_SRR1,r3
1073 SYNC
1074 RFI
1075 /* Load up the kernel context */
1076 2: bl load_up_mmu
1077
1078 #ifdef CONFIG_BDI_SWITCH
1079 /* Add helper information for the Abatron bdiGDB debugger.
1080 * We do this here because we know the mmu is disabled, and
1081 * will be enabled for real in just a few instructions.
1082 */
1083 lis r5, abatron_pteptrs@h
1084 ori r5, r5, abatron_pteptrs@l
1085 stw r5, 0xf0(r0) /* This much match your Abatron config */
1086 lis r6, swapper_pg_dir@h
1087 ori r6, r6, swapper_pg_dir@l
1088 tophys(r5, r5)
1089 stw r6, 0(r5)
1090 #endif /* CONFIG_BDI_SWITCH */
1091
1092 /* Now turn on the MMU for real! */
1093 li r4,MSR_KERNEL
1094 FIX_SRR1(r4,r5)
1095 lis r3,start_kernel@h
1096 ori r3,r3,start_kernel@l
1097 mtspr SPRN_SRR0,r3
1098 mtspr SPRN_SRR1,r4
1099 SYNC
1100 RFI
1101
1102 /*
1103 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1104 *
1105 * Set up the segment registers for a new context.
1106 */
1107 _ENTRY(switch_mmu_context)
1108 lwz r3,MMCONTEXTID(r4)
1109 cmpwi cr0,r3,0
1110 blt- 4f
1111 mulli r3,r3,897 /* multiply context by skew factor */
1112 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1113 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1114 li r0,NUM_USER_SEGMENTS
1115 mtctr r0
1116
1117 #ifdef CONFIG_BDI_SWITCH
1118 /* Context switch the PTE pointer for the Abatron BDI2000.
1119 * The PGDIR is passed as second argument.
1120 */
1121 lwz r4,MM_PGD(r4)
1122 lis r5, KERNELBASE@h
1123 lwz r5, 0xf0(r5)
1124 stw r4, 0x4(r5)
1125 #endif
1126 li r4,0
1127 isync
1128 3:
1129 mtsrin r3,r4
1130 addi r3,r3,0x111 /* next VSID */
1131 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1132 addis r4,r4,0x1000 /* address of next segment */
1133 bdnz 3b
1134 sync
1135 isync
1136 blr
1137 4: trap
1138 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1139 blr
1140
1141 /*
1142 * An undocumented "feature" of 604e requires that the v bit
1143 * be cleared before changing BAT values.
1144 *
1145 * Also, newer IBM firmware does not clear bat3 and 4 so
1146 * this makes sure it's done.
1147 * -- Cort
1148 */
1149 clear_bats:
1150 li r10,0
1151 mfspr r9,SPRN_PVR
1152 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1153 cmpwi r9, 1
1154 beq 1f
1155
1156 mtspr SPRN_DBAT0U,r10
1157 mtspr SPRN_DBAT0L,r10
1158 mtspr SPRN_DBAT1U,r10
1159 mtspr SPRN_DBAT1L,r10
1160 mtspr SPRN_DBAT2U,r10
1161 mtspr SPRN_DBAT2L,r10
1162 mtspr SPRN_DBAT3U,r10
1163 mtspr SPRN_DBAT3L,r10
1164 1:
1165 mtspr SPRN_IBAT0U,r10
1166 mtspr SPRN_IBAT0L,r10
1167 mtspr SPRN_IBAT1U,r10
1168 mtspr SPRN_IBAT1L,r10
1169 mtspr SPRN_IBAT2U,r10
1170 mtspr SPRN_IBAT2L,r10
1171 mtspr SPRN_IBAT3U,r10
1172 mtspr SPRN_IBAT3L,r10
1173 BEGIN_MMU_FTR_SECTION
1174 /* Here's a tweak: at this point, CPU setup have
1175 * not been called yet, so HIGH_BAT_EN may not be
1176 * set in HID0 for the 745x processors. However, it
1177 * seems that doesn't affect our ability to actually
1178 * write to these SPRs.
1179 */
1180 mtspr SPRN_DBAT4U,r10
1181 mtspr SPRN_DBAT4L,r10
1182 mtspr SPRN_DBAT5U,r10
1183 mtspr SPRN_DBAT5L,r10
1184 mtspr SPRN_DBAT6U,r10
1185 mtspr SPRN_DBAT6L,r10
1186 mtspr SPRN_DBAT7U,r10
1187 mtspr SPRN_DBAT7L,r10
1188 mtspr SPRN_IBAT4U,r10
1189 mtspr SPRN_IBAT4L,r10
1190 mtspr SPRN_IBAT5U,r10
1191 mtspr SPRN_IBAT5L,r10
1192 mtspr SPRN_IBAT6U,r10
1193 mtspr SPRN_IBAT6L,r10
1194 mtspr SPRN_IBAT7U,r10
1195 mtspr SPRN_IBAT7L,r10
1196 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1197 blr
1198
1199 flush_tlbs:
1200 lis r10, 0x40
1201 1: addic. r10, r10, -0x1000
1202 tlbie r10
1203 bgt 1b
1204 sync
1205 blr
1206
1207 mmu_off:
1208 addi r4, r3, __after_mmu_off - _start
1209 mfmsr r3
1210 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1211 beqlr
1212 andc r3,r3,r0
1213 mtspr SPRN_SRR0,r4
1214 mtspr SPRN_SRR1,r3
1215 sync
1216 RFI
1217
1218 /*
1219 * Use the first pair of BAT registers to map the 1st 16MB
1220 * of RAM to PAGE_OFFSET. From this point on we can't safely
1221 * call OF any more.
1222 */
1223 initial_bats:
1224 lis r11,PAGE_OFFSET@h
1225 mfspr r9,SPRN_PVR
1226 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1227 cmpwi 0,r9,1
1228 bne 4f
1229 ori r11,r11,4 /* set up BAT registers for 601 */
1230 li r8,0x7f /* valid, block length = 8MB */
1231 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1232 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1233 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1234 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1235 mtspr SPRN_IBAT1U,r9
1236 mtspr SPRN_IBAT1L,r10
1237 isync
1238 blr
1239
1240 4: tophys(r8,r11)
1241 #ifdef CONFIG_SMP
1242 ori r8,r8,0x12 /* R/W access, M=1 */
1243 #else
1244 ori r8,r8,2 /* R/W access */
1245 #endif /* CONFIG_SMP */
1246 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1247
1248 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1249 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1250 mtspr SPRN_IBAT0L,r8
1251 mtspr SPRN_IBAT0U,r11
1252 isync
1253 blr
1254
1255
1256 #ifdef CONFIG_BOOTX_TEXT
1257 setup_disp_bat:
1258 /*
1259 * setup the display bat prepared for us in prom.c
1260 */
1261 mflr r8
1262 bl reloc_offset
1263 mtlr r8
1264 addis r8,r3,disp_BAT@ha
1265 addi r8,r8,disp_BAT@l
1266 cmpwi cr0,r8,0
1267 beqlr
1268 lwz r11,0(r8)
1269 lwz r8,4(r8)
1270 mfspr r9,SPRN_PVR
1271 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1272 cmpwi 0,r9,1
1273 beq 1f
1274 mtspr SPRN_DBAT3L,r8
1275 mtspr SPRN_DBAT3U,r11
1276 blr
1277 1: mtspr SPRN_IBAT3L,r8
1278 mtspr SPRN_IBAT3U,r11
1279 blr
1280 #endif /* CONFIG_BOOTX_TEXT */
1281
1282 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1283 setup_cpm_bat:
1284 lis r8, 0xf000
1285 ori r8, r8, 0x002a
1286 mtspr SPRN_DBAT1L, r8
1287
1288 lis r11, 0xf000
1289 ori r11, r11, (BL_1M << 2) | 2
1290 mtspr SPRN_DBAT1U, r11
1291
1292 blr
1293 #endif
1294
1295 #ifdef CONFIG_8260
1296 /* Jump into the system reset for the rom.
1297 * We first disable the MMU, and then jump to the ROM reset address.
1298 *
1299 * r3 is the board info structure, r4 is the location for starting.
1300 * I use this for building a small kernel that can load other kernels,
1301 * rather than trying to write or rely on a rom monitor that can tftp load.
1302 */
1303 .globl m8260_gorom
1304 m8260_gorom:
1305 mfmsr r0
1306 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1307 sync
1308 mtmsr r0
1309 sync
1310 mfspr r11, SPRN_HID0
1311 lis r10, 0
1312 ori r10,r10,HID0_ICE|HID0_DCE
1313 andc r11, r11, r10
1314 mtspr SPRN_HID0, r11
1315 isync
1316 li r5, MSR_ME|MSR_RI
1317 lis r6,2f@h
1318 addis r6,r6,-KERNELBASE@h
1319 ori r6,r6,2f@l
1320 mtspr SPRN_SRR0,r6
1321 mtspr SPRN_SRR1,r5
1322 isync
1323 sync
1324 rfi
1325 2:
1326 mtlr r4
1327 blr
1328 #endif
1329
1330
1331 /*
1332 * We put a few things here that have to be page-aligned.
1333 * This stuff goes at the beginning of the data segment,
1334 * which is page-aligned.
1335 */
1336 .data
1337 .globl sdata
1338 sdata:
1339 .globl empty_zero_page
1340 empty_zero_page:
1341 .space 4096
1342
1343 .globl swapper_pg_dir
1344 swapper_pg_dir:
1345 .space PGD_TABLE_SIZE
1346
1347 .globl intercept_table
1348 intercept_table:
1349 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1350 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1351 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1352 .long 0, 0, 0, 0, 0, 0, 0, 0
1353 .long 0, 0, 0, 0, 0, 0, 0, 0
1354 .long 0, 0, 0, 0, 0, 0, 0, 0
1355
1356 /* Room for two PTE pointers, usually the kernel and current user pointers
1357 * to their respective root page table.
1358 */
1359 abatron_pteptrs:
1360 .space 8
Linux kernel - Deliverables
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