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Merge commit 'jk/jk-merge'
[deliverable/linux.git] / arch / powerpc / kernel / head_32.S
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
24 #include <asm/reg.h>
25 #include <asm/page.h>
26 #include <asm/mmu.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/cache.h>
30 #include <asm/thread_info.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/ptrace.h>
34
35 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
36 #define LOAD_BAT(n, reg, RA, RB) \
37 /* see the comment for clear_bats() -- Cort */ \
38 li RA,0; \
39 mtspr SPRN_IBAT##n##U,RA; \
40 mtspr SPRN_DBAT##n##U,RA; \
41 lwz RA,(n*16)+0(reg); \
42 lwz RB,(n*16)+4(reg); \
43 mtspr SPRN_IBAT##n##U,RA; \
44 mtspr SPRN_IBAT##n##L,RB; \
45 beq 1f; \
46 lwz RA,(n*16)+8(reg); \
47 lwz RB,(n*16)+12(reg); \
48 mtspr SPRN_DBAT##n##U,RA; \
49 mtspr SPRN_DBAT##n##L,RB; \
50 1:
51
52 .section .text.head, "ax"
53 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
54 .stabs "head_32.S",N_SO,0,0,0f
55 0:
56 _ENTRY(_stext);
57
58 /*
59 * _start is defined this way because the XCOFF loader in the OpenFirmware
60 * on the powermac expects the entry point to be a procedure descriptor.
61 */
62 _ENTRY(_start);
63 /*
64 * These are here for legacy reasons, the kernel used to
65 * need to look like a coff function entry for the pmac
66 * but we're always started by some kind of bootloader now.
67 * -- Cort
68 */
69 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
70 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
71 nop
72
73 /* PMAC
74 * Enter here with the kernel text, data and bss loaded starting at
75 * 0, running with virtual == physical mapping.
76 * r5 points to the prom entry point (the client interface handler
77 * address). Address translation is turned on, with the prom
78 * managing the hash table. Interrupts are disabled. The stack
79 * pointer (r1) points to just below the end of the half-meg region
80 * from 0x380000 - 0x400000, which is mapped in already.
81 *
82 * If we are booted from MacOS via BootX, we enter with the kernel
83 * image loaded somewhere, and the following values in registers:
84 * r3: 'BooX' (0x426f6f58)
85 * r4: virtual address of boot_infos_t
86 * r5: 0
87 *
88 * PREP
89 * This is jumped to on prep systems right after the kernel is relocated
90 * to its proper place in memory by the boot loader. The expected layout
91 * of the regs is:
92 * r3: ptr to residual data
93 * r4: initrd_start or if no initrd then 0
94 * r5: initrd_end - unused if r4 is 0
95 * r6: Start of command line string
96 * r7: End of command line string
97 *
98 * This just gets a minimal mmu environment setup so we can call
99 * start_here() to do the real work.
100 * -- Cort
101 */
102
103 .globl __start
104 __start:
105 /*
106 * We have to do any OF calls before we map ourselves to KERNELBASE,
107 * because OF may have I/O devices mapped into that area
108 * (particularly on CHRP).
109 */
110 #ifdef CONFIG_PPC_MULTIPLATFORM
111 cmpwi 0,r5,0
112 beq 1f
113 bl prom_init
114 trap
115 #endif
116
117 /*
118 * Check for BootX signature when supporting PowerMac and branch to
119 * appropriate trampoline if it's present
120 */
121 #ifdef CONFIG_PPC_PMAC
122 1: lis r31,0x426f
123 ori r31,r31,0x6f58
124 cmpw 0,r3,r31
125 bne 1f
126 bl bootx_init
127 trap
128 #endif /* CONFIG_PPC_PMAC */
129
130 1: mr r31,r3 /* save parameters */
131 mr r30,r4
132 li r24,0 /* cpu # */
133
134 /*
135 * early_init() does the early machine identification and does
136 * the necessary low-level setup and clears the BSS
137 * -- Cort <cort@fsmlabs.com>
138 */
139 bl early_init
140
141 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
142 * the physical address we are running at, returned by early_init()
143 */
144 bl mmu_off
145 __after_mmu_off:
146 bl clear_bats
147 bl flush_tlbs
148
149 bl initial_bats
150 #if defined(CONFIG_BOOTX_TEXT)
151 bl setup_disp_bat
152 #endif
153 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
154 bl setup_cpm_bat
155 #endif
156
157 /*
158 * Call setup_cpu for CPU 0 and initialize 6xx Idle
159 */
160 bl reloc_offset
161 li r24,0 /* cpu# */
162 bl call_setup_cpu /* Call setup_cpu for this CPU */
163 #ifdef CONFIG_6xx
164 bl reloc_offset
165 bl init_idle_6xx
166 #endif /* CONFIG_6xx */
167
168
169 /*
170 * We need to run with _start at physical address 0.
171 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
172 * the exception vectors at 0 (and therefore this copy
173 * overwrites OF's exception vectors with our own).
174 * The MMU is off at this point.
175 */
176 bl reloc_offset
177 mr r26,r3
178 addis r4,r3,KERNELBASE@h /* current address of _start */
179 cmpwi 0,r4,0 /* are we already running at 0? */
180 bne relocate_kernel
181 /*
182 * we now have the 1st 16M of ram mapped with the bats.
183 * prep needs the mmu to be turned on here, but pmac already has it on.
184 * this shouldn't bother the pmac since it just gets turned on again
185 * as we jump to our code at KERNELBASE. -- Cort
186 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
187 * off, and in other cases, we now turn it off before changing BATs above.
188 */
189 turn_on_mmu:
190 mfmsr r0
191 ori r0,r0,MSR_DR|MSR_IR
192 mtspr SPRN_SRR1,r0
193 lis r0,start_here@h
194 ori r0,r0,start_here@l
195 mtspr SPRN_SRR0,r0
196 SYNC
197 RFI /* enables MMU */
198
199 /*
200 * We need __secondary_hold as a place to hold the other cpus on
201 * an SMP machine, even when we are running a UP kernel.
202 */
203 . = 0xc0 /* for prep bootloader */
204 li r3,1 /* MTX only has 1 cpu */
205 .globl __secondary_hold
206 __secondary_hold:
207 /* tell the master we're here */
208 stw r3,__secondary_hold_acknowledge@l(0)
209 #ifdef CONFIG_SMP
210 100: lwz r4,0(0)
211 /* wait until we're told to start */
212 cmpw 0,r4,r3
213 bne 100b
214 /* our cpu # was at addr 0 - go */
215 mr r24,r3 /* cpu # */
216 b __secondary_start
217 #else
218 b .
219 #endif /* CONFIG_SMP */
220
221 .globl __secondary_hold_spinloop
222 __secondary_hold_spinloop:
223 .long 0
224 .globl __secondary_hold_acknowledge
225 __secondary_hold_acknowledge:
226 .long -1
227
228 /*
229 * Exception entry code. This code runs with address translation
230 * turned off, i.e. using physical addresses.
231 * We assume sprg3 has the physical address of the current
232 * task's thread_struct.
233 */
234 #define EXCEPTION_PROLOG \
235 mtspr SPRN_SPRG0,r10; \
236 mtspr SPRN_SPRG1,r11; \
237 mfcr r10; \
238 EXCEPTION_PROLOG_1; \
239 EXCEPTION_PROLOG_2
240
241 #define EXCEPTION_PROLOG_1 \
242 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
243 andi. r11,r11,MSR_PR; \
244 tophys(r11,r1); /* use tophys(r1) if kernel */ \
245 beq 1f; \
246 mfspr r11,SPRN_SPRG3; \
247 lwz r11,THREAD_INFO-THREAD(r11); \
248 addi r11,r11,THREAD_SIZE; \
249 tophys(r11,r11); \
250 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
251
252
253 #define EXCEPTION_PROLOG_2 \
254 CLR_TOP32(r11); \
255 stw r10,_CCR(r11); /* save registers */ \
256 stw r12,GPR12(r11); \
257 stw r9,GPR9(r11); \
258 mfspr r10,SPRN_SPRG0; \
259 stw r10,GPR10(r11); \
260 mfspr r12,SPRN_SPRG1; \
261 stw r12,GPR11(r11); \
262 mflr r10; \
263 stw r10,_LINK(r11); \
264 mfspr r12,SPRN_SRR0; \
265 mfspr r9,SPRN_SRR1; \
266 stw r1,GPR1(r11); \
267 stw r1,0(r11); \
268 tovirt(r1,r11); /* set new kernel sp */ \
269 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
270 MTMSRD(r10); /* (except for mach check in rtas) */ \
271 stw r0,GPR0(r11); \
272 lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
273 addi r10,r10,STACK_FRAME_REGS_MARKER@l; \
274 stw r10,8(r11); \
275 SAVE_4GPRS(3, r11); \
276 SAVE_2GPRS(7, r11)
277
278 /*
279 * Note: code which follows this uses cr0.eq (set if from kernel),
280 * r11, r12 (SRR0), and r9 (SRR1).
281 *
282 * Note2: once we have set r1 we are in a position to take exceptions
283 * again, and we could thus set MSR:RI at that point.
284 */
285
286 /*
287 * Exception vectors.
288 */
289 #define EXCEPTION(n, label, hdlr, xfer) \
290 . = n; \
291 label: \
292 EXCEPTION_PROLOG; \
293 addi r3,r1,STACK_FRAME_OVERHEAD; \
294 xfer(n, hdlr)
295
296 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
297 li r10,trap; \
298 stw r10,_TRAP(r11); \
299 li r10,MSR_KERNEL; \
300 copyee(r10, r9); \
301 bl tfer; \
302 i##n: \
303 .long hdlr; \
304 .long ret
305
306 #define COPY_EE(d, s) rlwimi d,s,0,16,16
307 #define NOCOPY(d, s)
308
309 #define EXC_XFER_STD(n, hdlr) \
310 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
311 ret_from_except_full)
312
313 #define EXC_XFER_LITE(n, hdlr) \
314 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
315 ret_from_except)
316
317 #define EXC_XFER_EE(n, hdlr) \
318 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
319 ret_from_except_full)
320
321 #define EXC_XFER_EE_LITE(n, hdlr) \
322 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
323 ret_from_except)
324
325 /* System reset */
326 /* core99 pmac starts the seconary here by changing the vector, and
327 putting it back to what it was (unknown_exception) when done. */
328 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
329
330 /* Machine check */
331 /*
332 * On CHRP, this is complicated by the fact that we could get a
333 * machine check inside RTAS, and we have no guarantee that certain
334 * critical registers will have the values we expect. The set of
335 * registers that might have bad values includes all the GPRs
336 * and all the BATs. We indicate that we are in RTAS by putting
337 * a non-zero value, the address of the exception frame to use,
338 * in SPRG2. The machine check handler checks SPRG2 and uses its
339 * value if it is non-zero. If we ever needed to free up SPRG2,
340 * we could use a field in the thread_info or thread_struct instead.
341 * (Other exception handlers assume that r1 is a valid kernel stack
342 * pointer when we take an exception from supervisor mode.)
343 * -- paulus.
344 */
345 . = 0x200
346 mtspr SPRN_SPRG0,r10
347 mtspr SPRN_SPRG1,r11
348 mfcr r10
349 #ifdef CONFIG_PPC_CHRP
350 mfspr r11,SPRN_SPRG2
351 cmpwi 0,r11,0
352 bne 7f
353 #endif /* CONFIG_PPC_CHRP */
354 EXCEPTION_PROLOG_1
355 7: EXCEPTION_PROLOG_2
356 addi r3,r1,STACK_FRAME_OVERHEAD
357 #ifdef CONFIG_PPC_CHRP
358 mfspr r4,SPRN_SPRG2
359 cmpwi cr1,r4,0
360 bne cr1,1f
361 #endif
362 EXC_XFER_STD(0x200, machine_check_exception)
363 #ifdef CONFIG_PPC_CHRP
364 1: b machine_check_in_rtas
365 #endif
366
367 /* Data access exception. */
368 . = 0x300
369 DataAccess:
370 EXCEPTION_PROLOG
371 mfspr r10,SPRN_DSISR
372 stw r10,_DSISR(r11)
373 andis. r0,r10,0xa470 /* weird error? */
374 bne 1f /* if not, try to put a PTE */
375 mfspr r4,SPRN_DAR /* into the hash table */
376 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
377 bl hash_page
378 1: lwz r5,_DSISR(r11) /* get DSISR value */
379 mfspr r4,SPRN_DAR
380 EXC_XFER_EE_LITE(0x300, handle_page_fault)
381
382
383 /* Instruction access exception. */
384 . = 0x400
385 InstructionAccess:
386 EXCEPTION_PROLOG
387 andis. r0,r9,0x4000 /* no pte found? */
388 beq 1f /* if so, try to put a PTE */
389 li r3,0 /* into the hash table */
390 mr r4,r12 /* SRR0 is fault address */
391 bl hash_page
392 1: mr r4,r12
393 mr r5,r9
394 EXC_XFER_EE_LITE(0x400, handle_page_fault)
395
396 /* External interrupt */
397 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
398
399 /* Alignment exception */
400 . = 0x600
401 Alignment:
402 EXCEPTION_PROLOG
403 mfspr r4,SPRN_DAR
404 stw r4,_DAR(r11)
405 mfspr r5,SPRN_DSISR
406 stw r5,_DSISR(r11)
407 addi r3,r1,STACK_FRAME_OVERHEAD
408 EXC_XFER_EE(0x600, alignment_exception)
409
410 /* Program check exception */
411 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
412
413 /* Floating-point unavailable */
414 . = 0x800
415 FPUnavailable:
416 BEGIN_FTR_SECTION
417 /*
418 * Certain Freescale cores don't have a FPU and treat fp instructions
419 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
420 */
421 b ProgramCheck
422 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
423 EXCEPTION_PROLOG
424 beq 1f
425 bl load_up_fpu /* if from user, just load it up */
426 b fast_exception_return
427 1: addi r3,r1,STACK_FRAME_OVERHEAD
428 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
429
430 /* Decrementer */
431 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
432
433 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
434 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
435
436 /* System call */
437 . = 0xc00
438 SystemCall:
439 EXCEPTION_PROLOG
440 EXC_XFER_EE_LITE(0xc00, DoSyscall)
441
442 /* Single step - not used on 601 */
443 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
444 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
445
446 /*
447 * The Altivec unavailable trap is at 0x0f20. Foo.
448 * We effectively remap it to 0x3000.
449 * We include an altivec unavailable exception vector even if
450 * not configured for Altivec, so that you can't panic a
451 * non-altivec kernel running on a machine with altivec just
452 * by executing an altivec instruction.
453 */
454 . = 0xf00
455 b PerformanceMonitor
456
457 . = 0xf20
458 b AltiVecUnavailable
459
460 /*
461 * Handle TLB miss for instruction on 603/603e.
462 * Note: we get an alternate set of r0 - r3 to use automatically.
463 */
464 . = 0x1000
465 InstructionTLBMiss:
466 /*
467 * r0: stored ctr
468 * r1: linux style pte ( later becomes ppc hardware pte )
469 * r2: ptr to linux-style pte
470 * r3: scratch
471 */
472 mfctr r0
473 /* Get PTE (linux-style) and check access */
474 mfspr r3,SPRN_IMISS
475 lis r1,PAGE_OFFSET@h /* check if kernel address */
476 cmplw 0,r1,r3
477 mfspr r2,SPRN_SPRG3
478 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
479 lwz r2,PGDIR(r2)
480 bge- 112f
481 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
482 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
483 lis r2,swapper_pg_dir@ha /* if kernel address, use */
484 addi r2,r2,swapper_pg_dir@l /* kernel page table */
485 112: tophys(r2,r2)
486 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
487 lwz r2,0(r2) /* get pmd entry */
488 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
489 beq- InstructionAddressInvalid /* return if no mapping */
490 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
491 lwz r3,0(r2) /* get linux-style pte */
492 andc. r1,r1,r3 /* check access & ~permission */
493 bne- InstructionAddressInvalid /* return if access not permitted */
494 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
495 /*
496 * NOTE! We are assuming this is not an SMP system, otherwise
497 * we would need to update the pte atomically with lwarx/stwcx.
498 */
499 stw r3,0(r2) /* update PTE (accessed bit) */
500 /* Convert linux-style PTE to low word of PPC-style PTE */
501 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
502 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
503 and r1,r1,r2 /* writable if _RW and _DIRTY */
504 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
505 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
506 ori r1,r1,0xe14 /* clear out reserved bits and M */
507 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
508 mtspr SPRN_RPA,r1
509 mfspr r3,SPRN_IMISS
510 tlbli r3
511 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
512 mtcrf 0x80,r3
513 rfi
514 InstructionAddressInvalid:
515 mfspr r3,SPRN_SRR1
516 rlwinm r1,r3,9,6,6 /* Get load/store bit */
517
518 addis r1,r1,0x2000
519 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
520 mtctr r0 /* Restore CTR */
521 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
522 or r2,r2,r1
523 mtspr SPRN_SRR1,r2
524 mfspr r1,SPRN_IMISS /* Get failing address */
525 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
526 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
527 xor r1,r1,r2
528 mtspr SPRN_DAR,r1 /* Set fault address */
529 mfmsr r0 /* Restore "normal" registers */
530 xoris r0,r0,MSR_TGPR>>16
531 mtcrf 0x80,r3 /* Restore CR0 */
532 mtmsr r0
533 b InstructionAccess
534
535 /*
536 * Handle TLB miss for DATA Load operation on 603/603e
537 */
538 . = 0x1100
539 DataLoadTLBMiss:
540 /*
541 * r0: stored ctr
542 * r1: linux style pte ( later becomes ppc hardware pte )
543 * r2: ptr to linux-style pte
544 * r3: scratch
545 */
546 mfctr r0
547 /* Get PTE (linux-style) and check access */
548 mfspr r3,SPRN_DMISS
549 lis r1,PAGE_OFFSET@h /* check if kernel address */
550 cmplw 0,r1,r3
551 mfspr r2,SPRN_SPRG3
552 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
553 lwz r2,PGDIR(r2)
554 bge- 112f
555 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
556 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
557 lis r2,swapper_pg_dir@ha /* if kernel address, use */
558 addi r2,r2,swapper_pg_dir@l /* kernel page table */
559 112: tophys(r2,r2)
560 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
561 lwz r2,0(r2) /* get pmd entry */
562 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
563 beq- DataAddressInvalid /* return if no mapping */
564 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
565 lwz r3,0(r2) /* get linux-style pte */
566 andc. r1,r1,r3 /* check access & ~permission */
567 bne- DataAddressInvalid /* return if access not permitted */
568 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
569 /*
570 * NOTE! We are assuming this is not an SMP system, otherwise
571 * we would need to update the pte atomically with lwarx/stwcx.
572 */
573 stw r3,0(r2) /* update PTE (accessed bit) */
574 /* Convert linux-style PTE to low word of PPC-style PTE */
575 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
576 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
577 and r1,r1,r2 /* writable if _RW and _DIRTY */
578 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
579 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
580 ori r1,r1,0xe14 /* clear out reserved bits and M */
581 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
582 mtspr SPRN_RPA,r1
583 mfspr r3,SPRN_DMISS
584 tlbld r3
585 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
586 mtcrf 0x80,r3
587 rfi
588 DataAddressInvalid:
589 mfspr r3,SPRN_SRR1
590 rlwinm r1,r3,9,6,6 /* Get load/store bit */
591 addis r1,r1,0x2000
592 mtspr SPRN_DSISR,r1
593 mtctr r0 /* Restore CTR */
594 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
595 mtspr SPRN_SRR1,r2
596 mfspr r1,SPRN_DMISS /* Get failing address */
597 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
598 beq 20f /* Jump if big endian */
599 xori r1,r1,3
600 20: mtspr SPRN_DAR,r1 /* Set fault address */
601 mfmsr r0 /* Restore "normal" registers */
602 xoris r0,r0,MSR_TGPR>>16
603 mtcrf 0x80,r3 /* Restore CR0 */
604 mtmsr r0
605 b DataAccess
606
607 /*
608 * Handle TLB miss for DATA Store on 603/603e
609 */
610 . = 0x1200
611 DataStoreTLBMiss:
612 /*
613 * r0: stored ctr
614 * r1: linux style pte ( later becomes ppc hardware pte )
615 * r2: ptr to linux-style pte
616 * r3: scratch
617 */
618 mfctr r0
619 /* Get PTE (linux-style) and check access */
620 mfspr r3,SPRN_DMISS
621 lis r1,PAGE_OFFSET@h /* check if kernel address */
622 cmplw 0,r1,r3
623 mfspr r2,SPRN_SPRG3
624 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
625 lwz r2,PGDIR(r2)
626 bge- 112f
627 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
628 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
629 lis r2,swapper_pg_dir@ha /* if kernel address, use */
630 addi r2,r2,swapper_pg_dir@l /* kernel page table */
631 112: tophys(r2,r2)
632 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
633 lwz r2,0(r2) /* get pmd entry */
634 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
635 beq- DataAddressInvalid /* return if no mapping */
636 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
637 lwz r3,0(r2) /* get linux-style pte */
638 andc. r1,r1,r3 /* check access & ~permission */
639 bne- DataAddressInvalid /* return if access not permitted */
640 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
641 /*
642 * NOTE! We are assuming this is not an SMP system, otherwise
643 * we would need to update the pte atomically with lwarx/stwcx.
644 */
645 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
646 /* Convert linux-style PTE to low word of PPC-style PTE */
647 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
648 li r1,0xe15 /* clear out reserved bits and M */
649 andc r1,r3,r1 /* PP = user? 2: 0 */
650 mtspr SPRN_RPA,r1
651 mfspr r3,SPRN_DMISS
652 tlbld r3
653 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
654 mtcrf 0x80,r3
655 rfi
656
657 #ifndef CONFIG_ALTIVEC
658 #define altivec_assist_exception unknown_exception
659 #endif
660
661 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
662 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
663 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
664 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
665 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
666 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
667 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
668 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
669 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
670 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
671 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
672 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
673 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
674 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
675 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
676 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
677 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
678 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
679 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
680 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
681 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
682 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
683 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
684 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
685 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
686 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
687 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
688 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
689 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
690
691 .globl mol_trampoline
692 .set mol_trampoline, i0x2f00
693
694 . = 0x3000
695
696 AltiVecUnavailable:
697 EXCEPTION_PROLOG
698 #ifdef CONFIG_ALTIVEC
699 bne load_up_altivec /* if from user, just load it up */
700 #endif /* CONFIG_ALTIVEC */
701 addi r3,r1,STACK_FRAME_OVERHEAD
702 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
703
704 PerformanceMonitor:
705 EXCEPTION_PROLOG
706 addi r3,r1,STACK_FRAME_OVERHEAD
707 EXC_XFER_STD(0xf00, performance_monitor_exception)
708
709 #ifdef CONFIG_ALTIVEC
710 /* Note that the AltiVec support is closely modeled after the FP
711 * support. Changes to one are likely to be applicable to the
712 * other! */
713 load_up_altivec:
714 /*
715 * Disable AltiVec for the task which had AltiVec previously,
716 * and save its AltiVec registers in its thread_struct.
717 * Enables AltiVec for use in the kernel on return.
718 * On SMP we know the AltiVec units are free, since we give it up every
719 * switch. -- Kumar
720 */
721 mfmsr r5
722 oris r5,r5,MSR_VEC@h
723 MTMSRD(r5) /* enable use of AltiVec now */
724 isync
725 /*
726 * For SMP, we don't do lazy AltiVec switching because it just gets too
727 * horrendously complex, especially when a task switches from one CPU
728 * to another. Instead we call giveup_altivec in switch_to.
729 */
730 #ifndef CONFIG_SMP
731 tophys(r6,0)
732 addis r3,r6,last_task_used_altivec@ha
733 lwz r4,last_task_used_altivec@l(r3)
734 cmpwi 0,r4,0
735 beq 1f
736 add r4,r4,r6
737 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
738 SAVE_32VRS(0,r10,r4)
739 mfvscr vr0
740 li r10,THREAD_VSCR
741 stvx vr0,r10,r4
742 lwz r5,PT_REGS(r4)
743 add r5,r5,r6
744 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
745 lis r10,MSR_VEC@h
746 andc r4,r4,r10 /* disable altivec for previous task */
747 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
748 1:
749 #endif /* CONFIG_SMP */
750 /* enable use of AltiVec after return */
751 oris r9,r9,MSR_VEC@h
752 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
753 li r4,1
754 li r10,THREAD_VSCR
755 stw r4,THREAD_USED_VR(r5)
756 lvx vr0,r10,r5
757 mtvscr vr0
758 REST_32VRS(0,r10,r5)
759 #ifndef CONFIG_SMP
760 subi r4,r5,THREAD
761 sub r4,r4,r6
762 stw r4,last_task_used_altivec@l(r3)
763 #endif /* CONFIG_SMP */
764 /* restore registers and return */
765 /* we haven't used ctr or xer or lr */
766 b fast_exception_return
767
768 /*
769 * giveup_altivec(tsk)
770 * Disable AltiVec for the task given as the argument,
771 * and save the AltiVec registers in its thread_struct.
772 * Enables AltiVec for use in the kernel on return.
773 */
774
775 .globl giveup_altivec
776 giveup_altivec:
777 mfmsr r5
778 oris r5,r5,MSR_VEC@h
779 SYNC
780 MTMSRD(r5) /* enable use of AltiVec now */
781 isync
782 cmpwi 0,r3,0
783 beqlr- /* if no previous owner, done */
784 addi r3,r3,THREAD /* want THREAD of task */
785 lwz r5,PT_REGS(r3)
786 cmpwi 0,r5,0
787 SAVE_32VRS(0, r4, r3)
788 mfvscr vr0
789 li r4,THREAD_VSCR
790 stvx vr0,r4,r3
791 beq 1f
792 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
793 lis r3,MSR_VEC@h
794 andc r4,r4,r3 /* disable AltiVec for previous task */
795 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
796 1:
797 #ifndef CONFIG_SMP
798 li r5,0
799 lis r4,last_task_used_altivec@ha
800 stw r5,last_task_used_altivec@l(r4)
801 #endif /* CONFIG_SMP */
802 blr
803 #endif /* CONFIG_ALTIVEC */
804
805 /*
806 * This code is jumped to from the startup code to copy
807 * the kernel image to physical address 0.
808 */
809 relocate_kernel:
810 addis r9,r26,klimit@ha /* fetch klimit */
811 lwz r25,klimit@l(r9)
812 addis r25,r25,-KERNELBASE@h
813 li r3,0 /* Destination base address */
814 li r6,0 /* Destination offset */
815 li r5,0x4000 /* # bytes of memory to copy */
816 bl copy_and_flush /* copy the first 0x4000 bytes */
817 addi r0,r3,4f@l /* jump to the address of 4f */
818 mtctr r0 /* in copy and do the rest. */
819 bctr /* jump to the copy */
820 4: mr r5,r25
821 bl copy_and_flush /* copy the rest */
822 b turn_on_mmu
823
824 /*
825 * Copy routine used to copy the kernel to start at physical address 0
826 * and flush and invalidate the caches as needed.
827 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
828 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
829 */
830 _ENTRY(copy_and_flush)
831 addi r5,r5,-4
832 addi r6,r6,-4
833 4: li r0,L1_CACHE_BYTES/4
834 mtctr r0
835 3: addi r6,r6,4 /* copy a cache line */
836 lwzx r0,r6,r4
837 stwx r0,r6,r3
838 bdnz 3b
839 dcbst r6,r3 /* write it to memory */
840 sync
841 icbi r6,r3 /* flush the icache line */
842 cmplw 0,r6,r5
843 blt 4b
844 sync /* additional sync needed on g4 */
845 isync
846 addi r5,r5,4
847 addi r6,r6,4
848 blr
849
850 #ifdef CONFIG_SMP
851 #ifdef CONFIG_GEMINI
852 .globl __secondary_start_gemini
853 __secondary_start_gemini:
854 mfspr r4,SPRN_HID0
855 ori r4,r4,HID0_ICFI
856 li r3,0
857 ori r3,r3,HID0_ICE
858 andc r4,r4,r3
859 mtspr SPRN_HID0,r4
860 sync
861 b __secondary_start
862 #endif /* CONFIG_GEMINI */
863
864 .globl __secondary_start_mpc86xx
865 __secondary_start_mpc86xx:
866 mfspr r3, SPRN_PIR
867 stw r3, __secondary_hold_acknowledge@l(0)
868 mr r24, r3 /* cpu # */
869 b __secondary_start
870
871 .globl __secondary_start_pmac_0
872 __secondary_start_pmac_0:
873 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
874 li r24,0
875 b 1f
876 li r24,1
877 b 1f
878 li r24,2
879 b 1f
880 li r24,3
881 1:
882 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
883 set to map the 0xf0000000 - 0xffffffff region */
884 mfmsr r0
885 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
886 SYNC
887 mtmsr r0
888 isync
889
890 .globl __secondary_start
891 __secondary_start:
892 /* Copy some CPU settings from CPU 0 */
893 bl __restore_cpu_setup
894
895 lis r3,-KERNELBASE@h
896 mr r4,r24
897 bl call_setup_cpu /* Call setup_cpu for this CPU */
898 #ifdef CONFIG_6xx
899 lis r3,-KERNELBASE@h
900 bl init_idle_6xx
901 #endif /* CONFIG_6xx */
902
903 /* get current_thread_info and current */
904 lis r1,secondary_ti@ha
905 tophys(r1,r1)
906 lwz r1,secondary_ti@l(r1)
907 tophys(r2,r1)
908 lwz r2,TI_TASK(r2)
909
910 /* stack */
911 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
912 li r0,0
913 tophys(r3,r1)
914 stw r0,0(r3)
915
916 /* load up the MMU */
917 bl load_up_mmu
918
919 /* ptr to phys current thread */
920 tophys(r4,r2)
921 addi r4,r4,THREAD /* phys address of our thread_struct */
922 CLR_TOP32(r4)
923 mtspr SPRN_SPRG3,r4
924 li r3,0
925 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
926
927 /* enable MMU and jump to start_secondary */
928 li r4,MSR_KERNEL
929 FIX_SRR1(r4,r5)
930 lis r3,start_secondary@h
931 ori r3,r3,start_secondary@l
932 mtspr SPRN_SRR0,r3
933 mtspr SPRN_SRR1,r4
934 SYNC
935 RFI
936 #endif /* CONFIG_SMP */
937
938 /*
939 * Those generic dummy functions are kept for CPUs not
940 * included in CONFIG_6xx
941 */
942 #if !defined(CONFIG_6xx)
943 _ENTRY(__save_cpu_setup)
944 blr
945 _ENTRY(__restore_cpu_setup)
946 blr
947 #endif /* !defined(CONFIG_6xx) */
948
949
950 /*
951 * Load stuff into the MMU. Intended to be called with
952 * IR=0 and DR=0.
953 */
954 load_up_mmu:
955 sync /* Force all PTE updates to finish */
956 isync
957 tlbia /* Clear all TLB entries */
958 sync /* wait for tlbia/tlbie to finish */
959 TLBSYNC /* ... on all CPUs */
960 /* Load the SDR1 register (hash table base & size) */
961 lis r6,_SDR1@ha
962 tophys(r6,r6)
963 lwz r6,_SDR1@l(r6)
964 mtspr SPRN_SDR1,r6
965 li r0,16 /* load up segment register values */
966 mtctr r0 /* for context 0 */
967 lis r3,0x2000 /* Ku = 1, VSID = 0 */
968 li r4,0
969 3: mtsrin r3,r4
970 addi r3,r3,0x111 /* increment VSID */
971 addis r4,r4,0x1000 /* address of next segment */
972 bdnz 3b
973
974 /* Load the BAT registers with the values set up by MMU_init.
975 MMU_init takes care of whether we're on a 601 or not. */
976 mfpvr r3
977 srwi r3,r3,16
978 cmpwi r3,1
979 lis r3,BATS@ha
980 addi r3,r3,BATS@l
981 tophys(r3,r3)
982 LOAD_BAT(0,r3,r4,r5)
983 LOAD_BAT(1,r3,r4,r5)
984 LOAD_BAT(2,r3,r4,r5)
985 LOAD_BAT(3,r3,r4,r5)
986 BEGIN_FTR_SECTION
987 LOAD_BAT(4,r3,r4,r5)
988 LOAD_BAT(5,r3,r4,r5)
989 LOAD_BAT(6,r3,r4,r5)
990 LOAD_BAT(7,r3,r4,r5)
991 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
992 blr
993
994 /*
995 * This is where the main kernel code starts.
996 */
997 start_here:
998 /* ptr to current */
999 lis r2,init_task@h
1000 ori r2,r2,init_task@l
1001 /* Set up for using our exception vectors */
1002 /* ptr to phys current thread */
1003 tophys(r4,r2)
1004 addi r4,r4,THREAD /* init task's THREAD */
1005 CLR_TOP32(r4)
1006 mtspr SPRN_SPRG3,r4
1007 li r3,0
1008 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1009
1010 /* stack */
1011 lis r1,init_thread_union@ha
1012 addi r1,r1,init_thread_union@l
1013 li r0,0
1014 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1015 /*
1016 * Do early platform-specific initialization,
1017 * and set up the MMU.
1018 */
1019 mr r3,r31
1020 mr r4,r30
1021 bl machine_init
1022 bl __save_cpu_setup
1023 bl MMU_init
1024
1025 /*
1026 * Go back to running unmapped so we can load up new values
1027 * for SDR1 (hash table pointer) and the segment registers
1028 * and change to using our exception vectors.
1029 */
1030 lis r4,2f@h
1031 ori r4,r4,2f@l
1032 tophys(r4,r4)
1033 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1034 FIX_SRR1(r3,r5)
1035 mtspr SPRN_SRR0,r4
1036 mtspr SPRN_SRR1,r3
1037 SYNC
1038 RFI
1039 /* Load up the kernel context */
1040 2: bl load_up_mmu
1041
1042 #ifdef CONFIG_BDI_SWITCH
1043 /* Add helper information for the Abatron bdiGDB debugger.
1044 * We do this here because we know the mmu is disabled, and
1045 * will be enabled for real in just a few instructions.
1046 */
1047 lis r5, abatron_pteptrs@h
1048 ori r5, r5, abatron_pteptrs@l
1049 stw r5, 0xf0(r0) /* This much match your Abatron config */
1050 lis r6, swapper_pg_dir@h
1051 ori r6, r6, swapper_pg_dir@l
1052 tophys(r5, r5)
1053 stw r6, 0(r5)
1054 #endif /* CONFIG_BDI_SWITCH */
1055
1056 /* Now turn on the MMU for real! */
1057 li r4,MSR_KERNEL
1058 FIX_SRR1(r4,r5)
1059 lis r3,start_kernel@h
1060 ori r3,r3,start_kernel@l
1061 mtspr SPRN_SRR0,r3
1062 mtspr SPRN_SRR1,r4
1063 SYNC
1064 RFI
1065
1066 /*
1067 * Set up the segment registers for a new context.
1068 */
1069 _ENTRY(set_context)
1070 mulli r3,r3,897 /* multiply context by skew factor */
1071 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1072 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1073 li r0,NUM_USER_SEGMENTS
1074 mtctr r0
1075
1076 #ifdef CONFIG_BDI_SWITCH
1077 /* Context switch the PTE pointer for the Abatron BDI2000.
1078 * The PGDIR is passed as second argument.
1079 */
1080 lis r5, KERNELBASE@h
1081 lwz r5, 0xf0(r5)
1082 stw r4, 0x4(r5)
1083 #endif
1084 li r4,0
1085 isync
1086 3:
1087 mtsrin r3,r4
1088 addi r3,r3,0x111 /* next VSID */
1089 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1090 addis r4,r4,0x1000 /* address of next segment */
1091 bdnz 3b
1092 sync
1093 isync
1094 blr
1095
1096 /*
1097 * An undocumented "feature" of 604e requires that the v bit
1098 * be cleared before changing BAT values.
1099 *
1100 * Also, newer IBM firmware does not clear bat3 and 4 so
1101 * this makes sure it's done.
1102 * -- Cort
1103 */
1104 clear_bats:
1105 li r10,0
1106 mfspr r9,SPRN_PVR
1107 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1108 cmpwi r9, 1
1109 beq 1f
1110
1111 mtspr SPRN_DBAT0U,r10
1112 mtspr SPRN_DBAT0L,r10
1113 mtspr SPRN_DBAT1U,r10
1114 mtspr SPRN_DBAT1L,r10
1115 mtspr SPRN_DBAT2U,r10
1116 mtspr SPRN_DBAT2L,r10
1117 mtspr SPRN_DBAT3U,r10
1118 mtspr SPRN_DBAT3L,r10
1119 1:
1120 mtspr SPRN_IBAT0U,r10
1121 mtspr SPRN_IBAT0L,r10
1122 mtspr SPRN_IBAT1U,r10
1123 mtspr SPRN_IBAT1L,r10
1124 mtspr SPRN_IBAT2U,r10
1125 mtspr SPRN_IBAT2L,r10
1126 mtspr SPRN_IBAT3U,r10
1127 mtspr SPRN_IBAT3L,r10
1128 BEGIN_FTR_SECTION
1129 /* Here's a tweak: at this point, CPU setup have
1130 * not been called yet, so HIGH_BAT_EN may not be
1131 * set in HID0 for the 745x processors. However, it
1132 * seems that doesn't affect our ability to actually
1133 * write to these SPRs.
1134 */
1135 mtspr SPRN_DBAT4U,r10
1136 mtspr SPRN_DBAT4L,r10
1137 mtspr SPRN_DBAT5U,r10
1138 mtspr SPRN_DBAT5L,r10
1139 mtspr SPRN_DBAT6U,r10
1140 mtspr SPRN_DBAT6L,r10
1141 mtspr SPRN_DBAT7U,r10
1142 mtspr SPRN_DBAT7L,r10
1143 mtspr SPRN_IBAT4U,r10
1144 mtspr SPRN_IBAT4L,r10
1145 mtspr SPRN_IBAT5U,r10
1146 mtspr SPRN_IBAT5L,r10
1147 mtspr SPRN_IBAT6U,r10
1148 mtspr SPRN_IBAT6L,r10
1149 mtspr SPRN_IBAT7U,r10
1150 mtspr SPRN_IBAT7L,r10
1151 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1152 blr
1153
1154 flush_tlbs:
1155 lis r10, 0x40
1156 1: addic. r10, r10, -0x1000
1157 tlbie r10
1158 bgt 1b
1159 sync
1160 blr
1161
1162 mmu_off:
1163 addi r4, r3, __after_mmu_off - _start
1164 mfmsr r3
1165 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1166 beqlr
1167 andc r3,r3,r0
1168 mtspr SPRN_SRR0,r4
1169 mtspr SPRN_SRR1,r3
1170 sync
1171 RFI
1172
1173 /*
1174 * Use the first pair of BAT registers to map the 1st 16MB
1175 * of RAM to KERNELBASE. From this point on we can't safely
1176 * call OF any more.
1177 */
1178 initial_bats:
1179 lis r11,KERNELBASE@h
1180 mfspr r9,SPRN_PVR
1181 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1182 cmpwi 0,r9,1
1183 bne 4f
1184 ori r11,r11,4 /* set up BAT registers for 601 */
1185 li r8,0x7f /* valid, block length = 8MB */
1186 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1187 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1188 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1189 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1190 mtspr SPRN_IBAT1U,r9
1191 mtspr SPRN_IBAT1L,r10
1192 isync
1193 blr
1194
1195 4: tophys(r8,r11)
1196 #ifdef CONFIG_SMP
1197 ori r8,r8,0x12 /* R/W access, M=1 */
1198 #else
1199 ori r8,r8,2 /* R/W access */
1200 #endif /* CONFIG_SMP */
1201 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1202
1203 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1204 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1205 mtspr SPRN_IBAT0L,r8
1206 mtspr SPRN_IBAT0U,r11
1207 isync
1208 blr
1209
1210
1211 #ifdef CONFIG_BOOTX_TEXT
1212 setup_disp_bat:
1213 /*
1214 * setup the display bat prepared for us in prom.c
1215 */
1216 mflr r8
1217 bl reloc_offset
1218 mtlr r8
1219 addis r8,r3,disp_BAT@ha
1220 addi r8,r8,disp_BAT@l
1221 cmpwi cr0,r8,0
1222 beqlr
1223 lwz r11,0(r8)
1224 lwz r8,4(r8)
1225 mfspr r9,SPRN_PVR
1226 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1227 cmpwi 0,r9,1
1228 beq 1f
1229 mtspr SPRN_DBAT3L,r8
1230 mtspr SPRN_DBAT3U,r11
1231 blr
1232 1: mtspr SPRN_IBAT3L,r8
1233 mtspr SPRN_IBAT3U,r11
1234 blr
1235 #endif /* CONFIG_BOOTX_TEXT */
1236
1237 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1238 setup_cpm_bat:
1239 lis r8, 0xf000
1240 ori r8, r8, 0x002a
1241 mtspr SPRN_DBAT1L, r8
1242
1243 lis r11, 0xf000
1244 ori r11, r11, (BL_1M << 2) | 2
1245 mtspr SPRN_DBAT1U, r11
1246
1247 blr
1248 #endif
1249
1250 #ifdef CONFIG_8260
1251 /* Jump into the system reset for the rom.
1252 * We first disable the MMU, and then jump to the ROM reset address.
1253 *
1254 * r3 is the board info structure, r4 is the location for starting.
1255 * I use this for building a small kernel that can load other kernels,
1256 * rather than trying to write or rely on a rom monitor that can tftp load.
1257 */
1258 .globl m8260_gorom
1259 m8260_gorom:
1260 mfmsr r0
1261 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1262 sync
1263 mtmsr r0
1264 sync
1265 mfspr r11, SPRN_HID0
1266 lis r10, 0
1267 ori r10,r10,HID0_ICE|HID0_DCE
1268 andc r11, r11, r10
1269 mtspr SPRN_HID0, r11
1270 isync
1271 li r5, MSR_ME|MSR_RI
1272 lis r6,2f@h
1273 addis r6,r6,-KERNELBASE@h
1274 ori r6,r6,2f@l
1275 mtspr SPRN_SRR0,r6
1276 mtspr SPRN_SRR1,r5
1277 isync
1278 sync
1279 rfi
1280 2:
1281 mtlr r4
1282 blr
1283 #endif
1284
1285
1286 /*
1287 * We put a few things here that have to be page-aligned.
1288 * This stuff goes at the beginning of the data segment,
1289 * which is page-aligned.
1290 */
1291 .data
1292 .globl sdata
1293 sdata:
1294 .globl empty_zero_page
1295 empty_zero_page:
1296 .space 4096
1297
1298 .globl swapper_pg_dir
1299 swapper_pg_dir:
1300 .space PGD_TABLE_SIZE
1301
1302 .globl intercept_table
1303 intercept_table:
1304 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1305 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1306 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1307 .long 0, 0, 0, 0, 0, 0, 0, 0
1308 .long 0, 0, 0, 0, 0, 0, 0, 0
1309 .long 0, 0, 0, 0, 0, 0, 0, 0
1310
1311 /* Room for two PTE pointers, usually the kernel and current user pointers
1312 * to their respective root page table.
1313 */
1314 abatron_pteptrs:
1315 .space 8
Linux kernel - Deliverables
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