arch/powerpc/kernel/head_44x.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2005 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *
  25  * This program is free software; you can redistribute  it and/or modify it
  26  * under  the terms of  the GNU General  Public License as published by the
  27  * Free Software Foundation;  either version 2 of the  License, or (at your
  28  * option) any later version.
  29  */
  30
  31 #include <asm/processor.h>
  32 #include <asm/page.h>
  33 #include <asm/mmu.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/cputable.h>
  36 #include <asm/thread_info.h>
  37 #include <asm/ppc_asm.h>
  38 #include <asm/asm-offsets.h>
  39 #include "head_booke.h"
  40
  41
  42 /* As with the other PowerPC ports, it is expected that when code
  43  * execution begins here, the following registers contain valid, yet
  44  * optional, information:
  45  *
  46  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  47  *   r4 - Starting address of the init RAM disk
  48  *   r5 - Ending address of the init RAM disk
  49  *   r6 - Start of kernel command line string (e.g. "mem=128")
  50  *   r7 - End of kernel command line string
  51  *
  52  */
  53         .section        .text.head, "ax"
  54 _ENTRY(_stext);
  55 _ENTRY(_start);
  56         /*
  57          * Reserve a word at a fixed location to store the address
  58          * of abatron_pteptrs
  59          */
  60         nop
  61 /*
  62  * Save parameters we are passed
  63  */
  64         mr      r31,r3
  65         mr      r30,r4
  66         mr      r29,r5
  67         mr      r28,r6
  68         mr      r27,r7
  69         li      r24,0           /* CPU number */
  70
  71 /*
  72  * Set up the initial MMU state
  73  *
  74  * We are still executing code at the virtual address
  75  * mappings set by the firmware for the base of RAM.
  76  *
  77  * We first invalidate all TLB entries but the one
  78  * we are running from.  We then load the KERNELBASE
  79  * mappings so we can begin to use kernel addresses
  80  * natively and so the interrupt vector locations are
  81  * permanently pinned (necessary since Book E
  82  * implementations always have translation enabled).
  83  *
  84  * TODO: Use the known TLB entry we are running from to
  85  *       determine which physical region we are located
  86  *       in.  This can be used to determine where in RAM
  87  *       (on a shared CPU system) or PCI memory space
  88  *       (on a DRAMless system) we are located.
  89  *       For now, we assume a perfect world which means
  90  *       we are located at the base of DRAM (physical 0).
  91  */
  92
  93 /*
  94  * Search TLB for entry that we are currently using.
  95  * Invalidate all entries but the one we are using.
  96  */
  97         /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
  98         mfspr   r3,SPRN_PID                     /* Get PID */
  99         mfmsr   r4                              /* Get MSR */
 100         andi.   r4,r4,MSR_IS@l                  /* TS=1? */
 101         beq     wmmucr                          /* If not, leave STS=0 */
 102         oris    r3,r3,PPC44x_MMUCR_STS@h        /* Set STS=1 */
 103 wmmucr: mtspr   SPRN_MMUCR,r3                   /* Put MMUCR */
 104         sync
 105
 106         bl      invstr                          /* Find our address */
 107 invstr: mflr    r5                              /* Make it accessible */
 108         tlbsx   r23,0,r5                        /* Find entry we are in */
 109         li      r4,0                            /* Start at TLB entry 0 */
 110         li      r3,0                            /* Set PAGEID inval value */
 111 1:      cmpw    r23,r4                          /* Is this our entry? */
 112         beq     skpinv                          /* If so, skip the inval */
 113         tlbwe   r3,r4,PPC44x_TLB_PAGEID         /* If not, inval the entry */
 114 skpinv: addi    r4,r4,1                         /* Increment */
 115         cmpwi   r4,64                           /* Are we done? */
 116         bne     1b                              /* If not, repeat */
 117         isync                                   /* If so, context change */
 118
 119 /*
 120  * Configure and load pinned entry into TLB slot 63.
 121  */
 122
 123         lis     r3,PAGE_OFFSET@h
 124         ori     r3,r3,PAGE_OFFSET@l
 125
 126         /* Kernel is at the base of RAM */
 127         li r4, 0                        /* Load the kernel physical address */
 128
 129         /* Load the kernel PID = 0 */
 130         li      r0,0
 131         mtspr   SPRN_PID,r0
 132         sync
 133
 134         /* Initialize MMUCR */
 135         li      r5,0
 136         mtspr   SPRN_MMUCR,r5
 137         sync
 138
 139         /* pageid fields */
 140         clrrwi  r3,r3,10                /* Mask off the effective page number */
 141         ori     r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
 142
 143         /* xlat fields */
 144         clrrwi  r4,r4,10                /* Mask off the real page number */
 145                                         /* ERPN is 0 for first 4GB page */
 146
 147         /* attrib fields */
 148         /* Added guarded bit to protect against speculative loads/stores */
 149         li      r5,0
 150         ori     r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
 151
 152         li      r0,63                    /* TLB slot 63 */
 153
 154         tlbwe   r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
 155         tlbwe   r4,r0,PPC44x_TLB_XLAT   /* Load the translation fields */
 156         tlbwe   r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
 157
 158         /* Force context change */
 159         mfmsr   r0
 160         mtspr   SPRN_SRR1, r0
 161         lis     r0,3f@h
 162         ori     r0,r0,3f@l
 163         mtspr   SPRN_SRR0,r0
 164         sync
 165         rfi
 166
 167         /* If necessary, invalidate original entry we used */
 168 3:      cmpwi   r23,63
 169         beq     4f
 170         li      r6,0
 171         tlbwe   r6,r23,PPC44x_TLB_PAGEID
 172         isync
 173
 174 4:
 175 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
 176         /* Add UART mapping for early debug. */
 177
 178         /* pageid fields */
 179         lis     r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
 180         ori     r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K
 181
 182         /* xlat fields */
 183         lis     r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
 184         ori     r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
 185
 186         /* attrib fields */
 187         li      r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
 188         li      r0,62                    /* TLB slot 0 */
 189
 190         tlbwe   r3,r0,PPC44x_TLB_PAGEID
 191         tlbwe   r4,r0,PPC44x_TLB_XLAT
 192         tlbwe   r5,r0,PPC44x_TLB_ATTRIB
 193
 194         /* Force context change */
 195         isync
 196 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
 197
 198         /* Establish the interrupt vector offsets */
 199         SET_IVOR(0,  CriticalInput);
 200         SET_IVOR(1,  MachineCheck);
 201         SET_IVOR(2,  DataStorage);
 202         SET_IVOR(3,  InstructionStorage);
 203         SET_IVOR(4,  ExternalInput);
 204         SET_IVOR(5,  Alignment);
 205         SET_IVOR(6,  Program);
 206         SET_IVOR(7,  FloatingPointUnavailable);
 207         SET_IVOR(8,  SystemCall);
 208         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 209         SET_IVOR(10, Decrementer);
 210         SET_IVOR(11, FixedIntervalTimer);
 211         SET_IVOR(12, WatchdogTimer);
 212         SET_IVOR(13, DataTLBError);
 213         SET_IVOR(14, InstructionTLBError);
 214         SET_IVOR(15, DebugCrit);
 215
 216         /* Establish the interrupt vector base */
 217         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 218         mtspr   SPRN_IVPR,r4
 219
 220         /*
 221          * This is where the main kernel code starts.
 222          */
 223
 224         /* ptr to current */
 225         lis     r2,init_task@h
 226         ori     r2,r2,init_task@l
 227
 228         /* ptr to current thread */
 229         addi    r4,r2,THREAD    /* init task's THREAD */
 230         mtspr   SPRN_SPRG3,r4
 231
 232         /* stack */
 233         lis     r1,init_thread_union@h
 234         ori     r1,r1,init_thread_union@l
 235         li      r0,0
 236         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 237
 238         bl      early_init
 239
 240 /*
 241  * Decide what sort of machine this is and initialize the MMU.
 242  */
 243         mr      r3,r31
 244         mr      r4,r30
 245         mr      r5,r29
 246         mr      r6,r28
 247         mr      r7,r27
 248         bl      machine_init
 249         bl      MMU_init
 250
 251         /* Setup PTE pointers for the Abatron bdiGDB */
 252         lis     r6, swapper_pg_dir@h
 253         ori     r6, r6, swapper_pg_dir@l
 254         lis     r5, abatron_pteptrs@h
 255         ori     r5, r5, abatron_pteptrs@l
 256         lis     r4, KERNELBASE@h
 257         ori     r4, r4, KERNELBASE@l
 258         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 259         stw     r6, 0(r5)
 260
 261         /* Let's move on */
 262         lis     r4,start_kernel@h
 263         ori     r4,r4,start_kernel@l
 264         lis     r3,MSR_KERNEL@h
 265         ori     r3,r3,MSR_KERNEL@l
 266         mtspr   SPRN_SRR0,r4
 267         mtspr   SPRN_SRR1,r3
 268         rfi                     /* change context and jump to start_kernel */
 269
 270 /*
 271  * Interrupt vector entry code
 272  *
 273  * The Book E MMUs are always on so we don't need to handle
 274  * interrupts in real mode as with previous PPC processors. In
 275  * this case we handle interrupts in the kernel virtual address
 276  * space.
 277  *
 278  * Interrupt vectors are dynamically placed relative to the
 279  * interrupt prefix as determined by the address of interrupt_base.
 280  * The interrupt vectors offsets are programmed using the labels
 281  * for each interrupt vector entry.
 282  *
 283  * Interrupt vectors must be aligned on a 16 byte boundary.
 284  * We align on a 32 byte cache line boundary for good measure.
 285  */
 286
 287 interrupt_base:
 288         /* Critical Input Interrupt */
 289         CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
 290
 291         /* Machine Check Interrupt */
 292         CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 293         MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception)
 294
 295         /* Data Storage Interrupt */
 296         START_EXCEPTION(DataStorage)
 297         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 298         mtspr   SPRN_SPRG1, r11
 299         mtspr   SPRN_SPRG4W, r12
 300         mtspr   SPRN_SPRG5W, r13
 301         mfcr    r11
 302         mtspr   SPRN_SPRG7W, r11
 303
 304         /*
 305          * Check if it was a store fault, if not then bail
 306          * because a user tried to access a kernel or
 307          * read-protected page.  Otherwise, get the
 308          * offending address and handle it.
 309          */
 310         mfspr   r10, SPRN_ESR
 311         andis.  r10, r10, ESR_ST@h
 312         beq     2f
 313
 314         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 315
 316         /* If we are faulting a kernel address, we have to use the
 317          * kernel page tables.
 318          */
 319         lis     r11, PAGE_OFFSET@h
 320         cmplw   r10, r11
 321         blt+    3f
 322         lis     r11, swapper_pg_dir@h
 323         ori     r11, r11, swapper_pg_dir@l
 324
 325         mfspr   r12,SPRN_MMUCR
 326         rlwinm  r12,r12,0,0,23          /* Clear TID */
 327
 328         b       4f
 329
 330         /* Get the PGD for the current thread */
 331 3:
 332         mfspr   r11,SPRN_SPRG3
 333         lwz     r11,PGDIR(r11)
 334
 335         /* Load PID into MMUCR TID */
 336         mfspr   r12,SPRN_MMUCR          /* Get MMUCR */
 337         mfspr   r13,SPRN_PID            /* Get PID */
 338         rlwimi  r12,r13,0,24,31         /* Set TID */
 339
 340 4:
 341         mtspr   SPRN_MMUCR,r12
 342
 343         rlwinm  r12, r10, 13, 19, 29    /* Compute pgdir/pmd offset */
 344         lwzx    r11, r12, r11           /* Get pgd/pmd entry */
 345         rlwinm. r12, r11, 0, 0, 20      /* Extract pt base address */
 346         beq     2f                      /* Bail if no table */
 347
 348         rlwimi  r12, r10, 23, 20, 28    /* Compute pte address */
 349         lwz     r11, 4(r12)             /* Get pte entry */
 350
 351         andi.   r13, r11, _PAGE_RW      /* Is it writeable? */
 352         beq     2f                      /* Bail if not */
 353
 354         /* Update 'changed'.
 355         */
 356         ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 357         stw     r11, 4(r12)             /* Update Linux page table */
 358
 359         li      r13, PPC44x_TLB_SR@l    /* Set SR */
 360         rlwimi  r13, r11, 29, 29, 29    /* SX = _PAGE_HWEXEC */
 361         rlwimi  r13, r11, 0, 30, 30     /* SW = _PAGE_RW */
 362         rlwimi  r13, r11, 29, 28, 28    /* UR = _PAGE_USER */
 363         rlwimi  r12, r11, 31, 26, 26    /* (_PAGE_USER>>1)->r12 */
 364         rlwimi  r12, r11, 29, 30, 30    /* (_PAGE_USER>>3)->r12 */
 365         and     r12, r12, r11           /* HWEXEC/RW & USER */
 366         rlwimi  r13, r12, 0, 26, 26     /* UX = HWEXEC & USER */
 367         rlwimi  r13, r12, 3, 27, 27     /* UW = RW & USER */
 368
 369         rlwimi  r11,r13,0,26,31         /* Insert static perms */
 370
 371         /*
 372          * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added
 373          * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see
 374          * include/asm-powerpc/pgtable-ppc32.h for details).
 375          */
 376         rlwinm  r11,r11,0,20,10
 377
 378         /* find the TLB index that caused the fault.  It has to be here. */
 379         tlbsx   r10, 0, r10
 380
 381         tlbwe   r11, r10, PPC44x_TLB_ATTRIB     /* Write ATTRIB */
 382
 383         /* Done...restore registers and get out of here.
 384         */
 385         mfspr   r11, SPRN_SPRG7R
 386         mtcr    r11
 387         mfspr   r13, SPRN_SPRG5R
 388         mfspr   r12, SPRN_SPRG4R
 389
 390         mfspr   r11, SPRN_SPRG1
 391         mfspr   r10, SPRN_SPRG0
 392         rfi                     /* Force context change */
 393
 394 2:
 395         /*
 396          * The bailout.  Restore registers to pre-exception conditions
 397          * and call the heavyweights to help us out.
 398          */
 399         mfspr   r11, SPRN_SPRG7R
 400         mtcr    r11
 401         mfspr   r13, SPRN_SPRG5R
 402         mfspr   r12, SPRN_SPRG4R
 403
 404         mfspr   r11, SPRN_SPRG1
 405         mfspr   r10, SPRN_SPRG0
 406         b       data_access
 407
 408         /* Instruction Storage Interrupt */
 409         INSTRUCTION_STORAGE_EXCEPTION
 410
 411         /* External Input Interrupt */
 412         EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
 413
 414         /* Alignment Interrupt */
 415         ALIGNMENT_EXCEPTION
 416
 417         /* Program Interrupt */
 418         PROGRAM_EXCEPTION
 419
 420         /* Floating Point Unavailable Interrupt */
 421 #ifdef CONFIG_PPC_FPU
 422         FP_UNAVAILABLE_EXCEPTION
 423 #else
 424         EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
 425 #endif
 426
 427         /* System Call Interrupt */
 428         START_EXCEPTION(SystemCall)
 429         NORMAL_EXCEPTION_PROLOG
 430         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 431
 432         /* Auxillary Processor Unavailable Interrupt */
 433         EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
 434
 435         /* Decrementer Interrupt */
 436         DECREMENTER_EXCEPTION
 437
 438         /* Fixed Internal Timer Interrupt */
 439         /* TODO: Add FIT support */
 440         EXCEPTION(0x1010, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
 441
 442         /* Watchdog Timer Interrupt */
 443         /* TODO: Add watchdog support */
 444 #ifdef CONFIG_BOOKE_WDT
 445         CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException)
 446 #else
 447         CRITICAL_EXCEPTION(0x1020, WatchdogTimer, unknown_exception)
 448 #endif
 449
 450         /* Data TLB Error Interrupt */
 451         START_EXCEPTION(DataTLBError)
 452         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 453         mtspr   SPRN_SPRG1, r11
 454         mtspr   SPRN_SPRG4W, r12
 455         mtspr   SPRN_SPRG5W, r13
 456         mfcr    r11
 457         mtspr   SPRN_SPRG7W, r11
 458         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 459
 460         /* If we are faulting a kernel address, we have to use the
 461          * kernel page tables.
 462          */
 463         lis     r11, PAGE_OFFSET@h
 464         cmplw   r10, r11
 465         blt+    3f
 466         lis     r11, swapper_pg_dir@h
 467         ori     r11, r11, swapper_pg_dir@l
 468
 469         mfspr   r12,SPRN_MMUCR
 470         rlwinm  r12,r12,0,0,23          /* Clear TID */
 471
 472         b       4f
 473
 474         /* Get the PGD for the current thread */
 475 3:
 476         mfspr   r11,SPRN_SPRG3
 477         lwz     r11,PGDIR(r11)
 478
 479         /* Load PID into MMUCR TID */
 480         mfspr   r12,SPRN_MMUCR
 481         mfspr   r13,SPRN_PID            /* Get PID */
 482         rlwimi  r12,r13,0,24,31         /* Set TID */
 483
 484 4:
 485         mtspr   SPRN_MMUCR,r12
 486
 487         rlwinm  r12, r10, 13, 19, 29    /* Compute pgdir/pmd offset */
 488         lwzx    r11, r12, r11           /* Get pgd/pmd entry */
 489         rlwinm. r12, r11, 0, 0, 20      /* Extract pt base address */
 490         beq     2f                      /* Bail if no table */
 491
 492         rlwimi  r12, r10, 23, 20, 28    /* Compute pte address */
 493         lwz     r11, 4(r12)             /* Get pte entry */
 494         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 495         beq     2f                      /* Bail if not present */
 496
 497         ori     r11, r11, _PAGE_ACCESSED
 498         stw     r11, 4(r12)
 499
 500          /* Jump to common tlb load */
 501         b       finish_tlb_load
 502
 503 2:
 504         /* The bailout.  Restore registers to pre-exception conditions
 505          * and call the heavyweights to help us out.
 506          */
 507         mfspr   r11, SPRN_SPRG7R
 508         mtcr    r11
 509         mfspr   r13, SPRN_SPRG5R
 510         mfspr   r12, SPRN_SPRG4R
 511         mfspr   r11, SPRN_SPRG1
 512         mfspr   r10, SPRN_SPRG0
 513         b       data_access
 514
 515         /* Instruction TLB Error Interrupt */
 516         /*
 517          * Nearly the same as above, except we get our
 518          * information from different registers and bailout
 519          * to a different point.
 520          */
 521         START_EXCEPTION(InstructionTLBError)
 522         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 523         mtspr   SPRN_SPRG1, r11
 524         mtspr   SPRN_SPRG4W, r12
 525         mtspr   SPRN_SPRG5W, r13
 526         mfcr    r11
 527         mtspr   SPRN_SPRG7W, r11
 528         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 529
 530         /* If we are faulting a kernel address, we have to use the
 531          * kernel page tables.
 532          */
 533         lis     r11, PAGE_OFFSET@h
 534         cmplw   r10, r11
 535         blt+    3f
 536         lis     r11, swapper_pg_dir@h
 537         ori     r11, r11, swapper_pg_dir@l
 538
 539         mfspr   r12,SPRN_MMUCR
 540         rlwinm  r12,r12,0,0,23          /* Clear TID */
 541
 542         b       4f
 543
 544         /* Get the PGD for the current thread */
 545 3:
 546         mfspr   r11,SPRN_SPRG3
 547         lwz     r11,PGDIR(r11)
 548
 549         /* Load PID into MMUCR TID */
 550         mfspr   r12,SPRN_MMUCR
 551         mfspr   r13,SPRN_PID            /* Get PID */
 552         rlwimi  r12,r13,0,24,31         /* Set TID */
 553
 554 4:
 555         mtspr   SPRN_MMUCR,r12
 556
 557         rlwinm  r12, r10, 13, 19, 29    /* Compute pgdir/pmd offset */
 558         lwzx    r11, r12, r11           /* Get pgd/pmd entry */
 559         rlwinm. r12, r11, 0, 0, 20      /* Extract pt base address */
 560         beq     2f                      /* Bail if no table */
 561
 562         rlwimi  r12, r10, 23, 20, 28    /* Compute pte address */
 563         lwz     r11, 4(r12)             /* Get pte entry */
 564         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 565         beq     2f                      /* Bail if not present */
 566
 567         ori     r11, r11, _PAGE_ACCESSED
 568         stw     r11, 4(r12)
 569
 570         /* Jump to common TLB load point */
 571         b       finish_tlb_load
 572
 573 2:
 574         /* The bailout.  Restore registers to pre-exception conditions
 575          * and call the heavyweights to help us out.
 576          */
 577         mfspr   r11, SPRN_SPRG7R
 578         mtcr    r11
 579         mfspr   r13, SPRN_SPRG5R
 580         mfspr   r12, SPRN_SPRG4R
 581         mfspr   r11, SPRN_SPRG1
 582         mfspr   r10, SPRN_SPRG0
 583         b       InstructionStorage
 584
 585         /* Debug Interrupt */
 586         DEBUG_CRIT_EXCEPTION
 587
 588 /*
 589  * Local functions
 590  */
 591         /*
 592          * Data TLB exceptions will bail out to this point
 593          * if they can't resolve the lightweight TLB fault.
 594          */
 595 data_access:
 596         NORMAL_EXCEPTION_PROLOG
 597         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 598         stw     r5,_ESR(r11)
 599         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 600         EXC_XFER_EE_LITE(0x0300, handle_page_fault)
 601
 602 /*
 603
 604  * Both the instruction and data TLB miss get to this
 605  * point to load the TLB.
 606  *      r10 - EA of fault
 607  *      r11 - available to use
 608  *      r12 - Pointer to the 64-bit PTE
 609  *      r13 - available to use
 610  *      MMUCR - loaded with proper value when we get here
 611  *      Upon exit, we reload everything and RFI.
 612  */
 613 finish_tlb_load:
 614         /*
 615          * We set execute, because we don't have the granularity to
 616          * properly set this at the page level (Linux problem).
 617          * If shared is set, we cause a zero PID->TID load.
 618          * Many of these bits are software only.  Bits we don't set
 619          * here we (properly should) assume have the appropriate value.
 620          */
 621
 622         /* Load the next available TLB index */
 623         lis     r13, tlb_44x_index@ha
 624         lwz     r13, tlb_44x_index@l(r13)
 625         /* Load the TLB high watermark */
 626         lis     r11, tlb_44x_hwater@ha
 627         lwz     r11, tlb_44x_hwater@l(r11)
 628
 629         /* Increment, rollover, and store TLB index */
 630         addi    r13, r13, 1
 631         cmpw    0, r13, r11                     /* reserve entries */
 632         ble     7f
 633         li      r13, 0
 634 7:
 635         /* Store the next available TLB index */
 636         lis     r11, tlb_44x_index@ha
 637         stw     r13, tlb_44x_index@l(r11)
 638
 639         lwz     r11, 0(r12)                     /* Get MS word of PTE */
 640         lwz     r12, 4(r12)                     /* Get LS word of PTE */
 641         rlwimi  r11, r12, 0, 0 , 19             /* Insert RPN */
 642         tlbwe   r11, r13, PPC44x_TLB_XLAT       /* Write XLAT */
 643
 644         /*
 645          * Create PAGEID. This is the faulting address,
 646          * page size, and valid flag.
 647          */
 648         li      r11, PPC44x_TLB_VALID | PPC44x_TLB_4K
 649         rlwimi  r10, r11, 0, 20, 31             /* Insert valid and page size */
 650         tlbwe   r10, r13, PPC44x_TLB_PAGEID     /* Write PAGEID */
 651
 652         li      r10, PPC44x_TLB_SR@l            /* Set SR */
 653         rlwimi  r10, r12, 0, 30, 30             /* Set SW = _PAGE_RW */
 654         rlwimi  r10, r12, 29, 29, 29            /* SX = _PAGE_HWEXEC */
 655         rlwimi  r10, r12, 29, 28, 28            /* UR = _PAGE_USER */
 656         rlwimi  r11, r12, 31, 26, 26            /* (_PAGE_USER>>1)->r12 */
 657         and     r11, r12, r11                   /* HWEXEC & USER */
 658         rlwimi  r10, r11, 0, 26, 26             /* UX = HWEXEC & USER */
 659
 660         rlwimi  r12, r10, 0, 26, 31             /* Insert static perms */
 661
 662         /*
 663          * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added
 664          * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see
 665          * include/asm-powerpc/pgtable-ppc32.h for details).
 666          */
 667         rlwinm  r12, r12, 0, 20, 10
 668
 669         tlbwe   r12, r13, PPC44x_TLB_ATTRIB     /* Write ATTRIB */
 670
 671         /* Done...restore registers and get out of here.
 672         */
 673         mfspr   r11, SPRN_SPRG7R
 674         mtcr    r11
 675         mfspr   r13, SPRN_SPRG5R
 676         mfspr   r12, SPRN_SPRG4R
 677         mfspr   r11, SPRN_SPRG1
 678         mfspr   r10, SPRN_SPRG0
 679         rfi                                     /* Force context change */
 680
 681 /*
 682  * Global functions
 683  */
 684
 685 /*
 686  * Adjust the machine check IVOR on 440A cores
 687  */
 688 _GLOBAL(__fixup_440A_mcheck)
 689         li      r3,MachineCheckA@l
 690         mtspr   SPRN_IVOR1,r3
 691         sync
 692         blr
 693
 694 /*
 695  * extern void giveup_altivec(struct task_struct *prev)
 696  *
 697  * The 44x core does not have an AltiVec unit.
 698  */
 699 _GLOBAL(giveup_altivec)
 700         blr
 701
 702 /*
 703  * extern void giveup_fpu(struct task_struct *prev)
 704  *
 705  * The 44x core does not have an FPU.
 706  */
 707 #ifndef CONFIG_PPC_FPU
 708 _GLOBAL(giveup_fpu)
 709         blr
 710 #endif
 711
 712 _GLOBAL(set_context)
 713
 714 #ifdef CONFIG_BDI_SWITCH
 715         /* Context switch the PTE pointer for the Abatron BDI2000.
 716          * The PGDIR is the second parameter.
 717          */
 718         lis     r5, abatron_pteptrs@h
 719         ori     r5, r5, abatron_pteptrs@l
 720         stw     r4, 0x4(r5)
 721 #endif
 722         mtspr   SPRN_PID,r3
 723         isync                   /* Force context change */
 724         blr
 725
 726 /*
 727  * We put a few things here that have to be page-aligned. This stuff
 728  * goes at the beginning of the data segment, which is page-aligned.
 729  */
 730         .data
 731         .align  12
 732         .globl  sdata
 733 sdata:
 734         .globl  empty_zero_page
 735 empty_zero_page:
 736         .space  4096
 737
 738 /*
 739  * To support >32-bit physical addresses, we use an 8KB pgdir.
 740  */
 741         .globl  swapper_pg_dir
 742 swapper_pg_dir:
 743         .space  PGD_TABLE_SIZE
 744
 745 /* Reserved 4k for the critical exception stack & 4k for the machine
 746  * check stack per CPU for kernel mode exceptions */
 747         .section .bss
 748         .align 12
 749 exception_stack_bottom:
 750         .space  BOOKE_EXCEPTION_STACK_SIZE
 751         .globl  exception_stack_top
 752 exception_stack_top:
 753
 754 /*
 755  * Room for two PTE pointers, usually the kernel and current user pointers
 756  * to their respective root page table.
 757  */
 758 abatron_pteptrs:
 759         .space  8