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[PATCH] powerpc64: remove broken/bitrotted HMT support
[deliverable/linux.git] / arch / powerpc / kernel / head_64.S
1 /*
2 * arch/ppc64/kernel/head.S
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 *
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
13 *
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 *
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
24 */
25
26 #include <linux/config.h>
27 #include <linux/threads.h>
28 #include <asm/reg.h>
29 #include <asm/page.h>
30 #include <asm/mmu.h>
31 #include <asm/ppc_asm.h>
32 #include <asm/asm-offsets.h>
33 #include <asm/bug.h>
34 #include <asm/cputable.h>
35 #include <asm/setup.h>
36 #include <asm/hvcall.h>
37 #include <asm/iseries/lpar_map.h>
38 #include <asm/thread_info.h>
39
40 #ifdef CONFIG_PPC_ISERIES
41 #define DO_SOFT_DISABLE
42 #endif
43
44 /*
45 * We layout physical memory as follows:
46 * 0x0000 - 0x00ff : Secondary processor spin code
47 * 0x0100 - 0x2fff : pSeries Interrupt prologs
48 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
49 * 0x6000 - 0x6fff : Initial (CPU0) segment table
50 * 0x7000 - 0x7fff : FWNMI data area
51 * 0x8000 - : Early init and support code
52 */
53
54 /*
55 * SPRG Usage
56 *
57 * Register Definition
58 *
59 * SPRG0 reserved for hypervisor
60 * SPRG1 temp - used to save gpr
61 * SPRG2 temp - used to save gpr
62 * SPRG3 virt addr of paca
63 */
64
65 /*
66 * Entering into this code we make the following assumptions:
67 * For pSeries:
68 * 1. The MMU is off & open firmware is running in real mode.
69 * 2. The kernel is entered at __start
70 *
71 * For iSeries:
72 * 1. The MMU is on (as it always is for iSeries)
73 * 2. The kernel is entered at system_reset_iSeries
74 */
75
76 .text
77 .globl _stext
78 _stext:
79 #ifdef CONFIG_PPC_MULTIPLATFORM
80 _GLOBAL(__start)
81 /* NOP this out unconditionally */
82 BEGIN_FTR_SECTION
83 b .__start_initialization_multiplatform
84 END_FTR_SECTION(0, 1)
85 #endif /* CONFIG_PPC_MULTIPLATFORM */
86
87 /* Catch branch to 0 in real mode */
88 trap
89
90 #ifdef CONFIG_PPC_ISERIES
91 /*
92 * At offset 0x20, there is a pointer to iSeries LPAR data.
93 * This is required by the hypervisor
94 */
95 . = 0x20
96 .llong hvReleaseData-KERNELBASE
97
98 /*
99 * At offset 0x28 and 0x30 are offsets to the mschunks_map
100 * array (used by the iSeries LPAR debugger to do translation
101 * between physical addresses and absolute addresses) and
102 * to the pidhash table (also used by the debugger)
103 */
104 .llong mschunks_map-KERNELBASE
105 .llong 0 /* pidhash-KERNELBASE SFRXXX */
106
107 /* Offset 0x38 - Pointer to start of embedded System.map */
108 .globl embedded_sysmap_start
109 embedded_sysmap_start:
110 .llong 0
111 /* Offset 0x40 - Pointer to end of embedded System.map */
112 .globl embedded_sysmap_end
113 embedded_sysmap_end:
114 .llong 0
115
116 #endif /* CONFIG_PPC_ISERIES */
117
118 /* Secondary processors spin on this value until it goes to 1. */
119 .globl __secondary_hold_spinloop
120 __secondary_hold_spinloop:
121 .llong 0x0
122
123 /* Secondary processors write this value with their cpu # */
124 /* after they enter the spin loop immediately below. */
125 .globl __secondary_hold_acknowledge
126 __secondary_hold_acknowledge:
127 .llong 0x0
128
129 . = 0x60
130 /*
131 * The following code is used on pSeries to hold secondary processors
132 * in a spin loop after they have been freed from OpenFirmware, but
133 * before the bulk of the kernel has been relocated. This code
134 * is relocated to physical address 0x60 before prom_init is run.
135 * All of it must fit below the first exception vector at 0x100.
136 */
137 _GLOBAL(__secondary_hold)
138 mfmsr r24
139 ori r24,r24,MSR_RI
140 mtmsrd r24 /* RI on */
141
142 /* Grab our physical cpu number */
143 mr r24,r3
144
145 /* Tell the master cpu we're here */
146 /* Relocation is off & we are located at an address less */
147 /* than 0x100, so only need to grab low order offset. */
148 std r24,__secondary_hold_acknowledge@l(0)
149 sync
150
151 /* All secondary cpus wait here until told to start. */
152 100: ld r4,__secondary_hold_spinloop@l(0)
153 cmpdi 0,r4,1
154 bne 100b
155
156 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
157 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
158 mtctr r4
159 mr r3,r24
160 bctr
161 #else
162 BUG_OPCODE
163 #endif
164
165 /* This value is used to mark exception frames on the stack. */
166 .section ".toc","aw"
167 exception_marker:
168 .tc ID_72656773_68657265[TC],0x7265677368657265
169 .text
170
171 /*
172 * The following macros define the code that appears as
173 * the prologue to each of the exception handlers. They
174 * are split into two parts to allow a single kernel binary
175 * to be used for pSeries and iSeries.
176 * LOL. One day... - paulus
177 */
178
179 /*
180 * We make as much of the exception code common between native
181 * exception handlers (including pSeries LPAR) and iSeries LPAR
182 * implementations as possible.
183 */
184
185 /*
186 * This is the start of the interrupt handlers for pSeries
187 * This code runs with relocation off.
188 */
189 #define EX_R9 0
190 #define EX_R10 8
191 #define EX_R11 16
192 #define EX_R12 24
193 #define EX_R13 32
194 #define EX_SRR0 40
195 #define EX_DAR 48
196 #define EX_DSISR 56
197 #define EX_CCR 60
198 #define EX_R3 64
199 #define EX_LR 72
200
201 /*
202 * We're short on space and time in the exception prolog, so we can't
203 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
204 * low halfword of the address, but for Kdump we need the whole low
205 * word.
206 */
207 #ifdef CONFIG_CRASH_DUMP
208 #define LOAD_HANDLER(reg, label) \
209 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
210 ori reg,reg,(label)@l; /* .. and the rest */
211 #else
212 #define LOAD_HANDLER(reg, label) \
213 ori reg,reg,(label)@l; /* virt addr of handler ... */
214 #endif
215
216 #define EXCEPTION_PROLOG_PSERIES(area, label) \
217 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
218 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
219 std r10,area+EX_R10(r13); \
220 std r11,area+EX_R11(r13); \
221 std r12,area+EX_R12(r13); \
222 mfspr r9,SPRN_SPRG1; \
223 std r9,area+EX_R13(r13); \
224 mfcr r9; \
225 clrrdi r12,r13,32; /* get high part of &label */ \
226 mfmsr r10; \
227 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
228 LOAD_HANDLER(r12,label) \
229 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
230 mtspr SPRN_SRR0,r12; \
231 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
232 mtspr SPRN_SRR1,r10; \
233 rfid; \
234 b . /* prevent speculative execution */
235
236 /*
237 * This is the start of the interrupt handlers for iSeries
238 * This code runs with relocation on.
239 */
240 #define EXCEPTION_PROLOG_ISERIES_1(area) \
241 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
242 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
243 std r10,area+EX_R10(r13); \
244 std r11,area+EX_R11(r13); \
245 std r12,area+EX_R12(r13); \
246 mfspr r9,SPRN_SPRG1; \
247 std r9,area+EX_R13(r13); \
248 mfcr r9
249
250 #define EXCEPTION_PROLOG_ISERIES_2 \
251 mfmsr r10; \
252 ld r12,PACALPPACAPTR(r13); \
253 ld r11,LPPACASRR0(r12); \
254 ld r12,LPPACASRR1(r12); \
255 ori r10,r10,MSR_RI; \
256 mtmsrd r10,1
257
258 /*
259 * The common exception prolog is used for all except a few exceptions
260 * such as a segment miss on a kernel address. We have to be prepared
261 * to take another exception from the point where we first touch the
262 * kernel stack onwards.
263 *
264 * On entry r13 points to the paca, r9-r13 are saved in the paca,
265 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
266 * SRR1, and relocation is on.
267 */
268 #define EXCEPTION_PROLOG_COMMON(n, area) \
269 andi. r10,r12,MSR_PR; /* See if coming from user */ \
270 mr r10,r1; /* Save r1 */ \
271 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
272 beq- 1f; \
273 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
274 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
275 bge- cr1,bad_stack; /* abort if it is */ \
276 std r9,_CCR(r1); /* save CR in stackframe */ \
277 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
278 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
279 std r10,0(r1); /* make stack chain pointer */ \
280 std r0,GPR0(r1); /* save r0 in stackframe */ \
281 std r10,GPR1(r1); /* save r1 in stackframe */ \
282 std r2,GPR2(r1); /* save r2 in stackframe */ \
283 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
284 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
285 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
286 ld r10,area+EX_R10(r13); \
287 std r9,GPR9(r1); \
288 std r10,GPR10(r1); \
289 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
290 ld r10,area+EX_R12(r13); \
291 ld r11,area+EX_R13(r13); \
292 std r9,GPR11(r1); \
293 std r10,GPR12(r1); \
294 std r11,GPR13(r1); \
295 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
296 mflr r9; /* save LR in stackframe */ \
297 std r9,_LINK(r1); \
298 mfctr r10; /* save CTR in stackframe */ \
299 std r10,_CTR(r1); \
300 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
301 std r11,_XER(r1); \
302 li r9,(n)+1; \
303 std r9,_TRAP(r1); /* set trap number */ \
304 li r10,0; \
305 ld r11,exception_marker@toc(r2); \
306 std r10,RESULT(r1); /* clear regs->result */ \
307 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
308
309 /*
310 * Exception vectors.
311 */
312 #define STD_EXCEPTION_PSERIES(n, label) \
313 . = n; \
314 .globl label##_pSeries; \
315 label##_pSeries: \
316 HMT_MEDIUM; \
317 mtspr SPRN_SPRG1,r13; /* save r13 */ \
318 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
319
320 #define STD_EXCEPTION_ISERIES(n, label, area) \
321 .globl label##_iSeries; \
322 label##_iSeries: \
323 HMT_MEDIUM; \
324 mtspr SPRN_SPRG1,r13; /* save r13 */ \
325 EXCEPTION_PROLOG_ISERIES_1(area); \
326 EXCEPTION_PROLOG_ISERIES_2; \
327 b label##_common
328
329 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
330 .globl label##_iSeries; \
331 label##_iSeries: \
332 HMT_MEDIUM; \
333 mtspr SPRN_SPRG1,r13; /* save r13 */ \
334 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
335 lbz r10,PACAPROCENABLED(r13); \
336 cmpwi 0,r10,0; \
337 beq- label##_iSeries_masked; \
338 EXCEPTION_PROLOG_ISERIES_2; \
339 b label##_common; \
340
341 #ifdef DO_SOFT_DISABLE
342 #define DISABLE_INTS \
343 lbz r10,PACAPROCENABLED(r13); \
344 li r11,0; \
345 std r10,SOFTE(r1); \
346 mfmsr r10; \
347 stb r11,PACAPROCENABLED(r13); \
348 ori r10,r10,MSR_EE; \
349 mtmsrd r10,1
350
351 #define ENABLE_INTS \
352 lbz r10,PACAPROCENABLED(r13); \
353 mfmsr r11; \
354 std r10,SOFTE(r1); \
355 ori r11,r11,MSR_EE; \
356 mtmsrd r11,1
357
358 #else /* hard enable/disable interrupts */
359 #define DISABLE_INTS
360
361 #define ENABLE_INTS \
362 ld r12,_MSR(r1); \
363 mfmsr r11; \
364 rlwimi r11,r12,0,MSR_EE; \
365 mtmsrd r11,1
366
367 #endif
368
369 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
370 .align 7; \
371 .globl label##_common; \
372 label##_common: \
373 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
374 DISABLE_INTS; \
375 bl .save_nvgprs; \
376 addi r3,r1,STACK_FRAME_OVERHEAD; \
377 bl hdlr; \
378 b .ret_from_except
379
380 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
381 .align 7; \
382 .globl label##_common; \
383 label##_common: \
384 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
385 DISABLE_INTS; \
386 bl .ppc64_runlatch_on; \
387 addi r3,r1,STACK_FRAME_OVERHEAD; \
388 bl hdlr; \
389 b .ret_from_except_lite
390
391 /*
392 * Start of pSeries system interrupt routines
393 */
394 . = 0x100
395 .globl __start_interrupts
396 __start_interrupts:
397
398 STD_EXCEPTION_PSERIES(0x100, system_reset)
399
400 . = 0x200
401 _machine_check_pSeries:
402 HMT_MEDIUM
403 mtspr SPRN_SPRG1,r13 /* save r13 */
404 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
405
406 . = 0x300
407 .globl data_access_pSeries
408 data_access_pSeries:
409 HMT_MEDIUM
410 mtspr SPRN_SPRG1,r13
411 BEGIN_FTR_SECTION
412 mtspr SPRN_SPRG2,r12
413 mfspr r13,SPRN_DAR
414 mfspr r12,SPRN_DSISR
415 srdi r13,r13,60
416 rlwimi r13,r12,16,0x20
417 mfcr r12
418 cmpwi r13,0x2c
419 beq .do_stab_bolted_pSeries
420 mtcrf 0x80,r12
421 mfspr r12,SPRN_SPRG2
422 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
423 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
424
425 . = 0x380
426 .globl data_access_slb_pSeries
427 data_access_slb_pSeries:
428 HMT_MEDIUM
429 mtspr SPRN_SPRG1,r13
430 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
431 std r3,PACA_EXSLB+EX_R3(r13)
432 mfspr r3,SPRN_DAR
433 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
434 mfcr r9
435 #ifdef __DISABLED__
436 /* Keep that around for when we re-implement dynamic VSIDs */
437 cmpdi r3,0
438 bge slb_miss_user_pseries
439 #endif /* __DISABLED__ */
440 std r10,PACA_EXSLB+EX_R10(r13)
441 std r11,PACA_EXSLB+EX_R11(r13)
442 std r12,PACA_EXSLB+EX_R12(r13)
443 mfspr r10,SPRN_SPRG1
444 std r10,PACA_EXSLB+EX_R13(r13)
445 mfspr r12,SPRN_SRR1 /* and SRR1 */
446 b .slb_miss_realmode /* Rel. branch works in real mode */
447
448 STD_EXCEPTION_PSERIES(0x400, instruction_access)
449
450 . = 0x480
451 .globl instruction_access_slb_pSeries
452 instruction_access_slb_pSeries:
453 HMT_MEDIUM
454 mtspr SPRN_SPRG1,r13
455 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
456 std r3,PACA_EXSLB+EX_R3(r13)
457 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
458 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
459 mfcr r9
460 #ifdef __DISABLED__
461 /* Keep that around for when we re-implement dynamic VSIDs */
462 cmpdi r3,0
463 bge slb_miss_user_pseries
464 #endif /* __DISABLED__ */
465 std r10,PACA_EXSLB+EX_R10(r13)
466 std r11,PACA_EXSLB+EX_R11(r13)
467 std r12,PACA_EXSLB+EX_R12(r13)
468 mfspr r10,SPRN_SPRG1
469 std r10,PACA_EXSLB+EX_R13(r13)
470 mfspr r12,SPRN_SRR1 /* and SRR1 */
471 b .slb_miss_realmode /* Rel. branch works in real mode */
472
473 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
474 STD_EXCEPTION_PSERIES(0x600, alignment)
475 STD_EXCEPTION_PSERIES(0x700, program_check)
476 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
477 STD_EXCEPTION_PSERIES(0x900, decrementer)
478 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
479 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
480
481 . = 0xc00
482 .globl system_call_pSeries
483 system_call_pSeries:
484 HMT_MEDIUM
485 mr r9,r13
486 mfmsr r10
487 mfspr r13,SPRN_SPRG3
488 mfspr r11,SPRN_SRR0
489 clrrdi r12,r13,32
490 oris r12,r12,system_call_common@h
491 ori r12,r12,system_call_common@l
492 mtspr SPRN_SRR0,r12
493 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
494 mfspr r12,SPRN_SRR1
495 mtspr SPRN_SRR1,r10
496 rfid
497 b . /* prevent speculative execution */
498
499 STD_EXCEPTION_PSERIES(0xd00, single_step)
500 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
501
502 /* We need to deal with the Altivec unavailable exception
503 * here which is at 0xf20, thus in the middle of the
504 * prolog code of the PerformanceMonitor one. A little
505 * trickery is thus necessary
506 */
507 . = 0xf00
508 b performance_monitor_pSeries
509
510 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
511
512 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
513 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
514
515 . = 0x3000
516
517 /*** pSeries interrupt support ***/
518
519 /* moved from 0xf00 */
520 STD_EXCEPTION_PSERIES(., performance_monitor)
521
522 .align 7
523 _GLOBAL(do_stab_bolted_pSeries)
524 mtcrf 0x80,r12
525 mfspr r12,SPRN_SPRG2
526 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
527
528 /*
529 * We have some room here we use that to put
530 * the peries slb miss user trampoline code so it's reasonably
531 * away from slb_miss_user_common to avoid problems with rfid
532 *
533 * This is used for when the SLB miss handler has to go virtual,
534 * which doesn't happen for now anymore but will once we re-implement
535 * dynamic VSIDs for shared page tables
536 */
537 #ifdef __DISABLED__
538 slb_miss_user_pseries:
539 std r10,PACA_EXGEN+EX_R10(r13)
540 std r11,PACA_EXGEN+EX_R11(r13)
541 std r12,PACA_EXGEN+EX_R12(r13)
542 mfspr r10,SPRG1
543 ld r11,PACA_EXSLB+EX_R9(r13)
544 ld r12,PACA_EXSLB+EX_R3(r13)
545 std r10,PACA_EXGEN+EX_R13(r13)
546 std r11,PACA_EXGEN+EX_R9(r13)
547 std r12,PACA_EXGEN+EX_R3(r13)
548 clrrdi r12,r13,32
549 mfmsr r10
550 mfspr r11,SRR0 /* save SRR0 */
551 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
552 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
553 mtspr SRR0,r12
554 mfspr r12,SRR1 /* and SRR1 */
555 mtspr SRR1,r10
556 rfid
557 b . /* prevent spec. execution */
558 #endif /* __DISABLED__ */
559
560 /*
561 * Vectors for the FWNMI option. Share common code.
562 */
563 .globl system_reset_fwnmi
564 .align 7
565 system_reset_fwnmi:
566 HMT_MEDIUM
567 mtspr SPRN_SPRG1,r13 /* save r13 */
568 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
569
570 .globl machine_check_fwnmi
571 .align 7
572 machine_check_fwnmi:
573 HMT_MEDIUM
574 mtspr SPRN_SPRG1,r13 /* save r13 */
575 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
576
577 #ifdef CONFIG_PPC_ISERIES
578 /*** ISeries-LPAR interrupt handlers ***/
579
580 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
581
582 .globl data_access_iSeries
583 data_access_iSeries:
584 mtspr SPRN_SPRG1,r13
585 BEGIN_FTR_SECTION
586 mtspr SPRN_SPRG2,r12
587 mfspr r13,SPRN_DAR
588 mfspr r12,SPRN_DSISR
589 srdi r13,r13,60
590 rlwimi r13,r12,16,0x20
591 mfcr r12
592 cmpwi r13,0x2c
593 beq .do_stab_bolted_iSeries
594 mtcrf 0x80,r12
595 mfspr r12,SPRN_SPRG2
596 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
597 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
598 EXCEPTION_PROLOG_ISERIES_2
599 b data_access_common
600
601 .do_stab_bolted_iSeries:
602 mtcrf 0x80,r12
603 mfspr r12,SPRN_SPRG2
604 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
605 EXCEPTION_PROLOG_ISERIES_2
606 b .do_stab_bolted
607
608 .globl data_access_slb_iSeries
609 data_access_slb_iSeries:
610 mtspr SPRN_SPRG1,r13 /* save r13 */
611 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
612 std r3,PACA_EXSLB+EX_R3(r13)
613 mfspr r3,SPRN_DAR
614 std r9,PACA_EXSLB+EX_R9(r13)
615 mfcr r9
616 #ifdef __DISABLED__
617 cmpdi r3,0
618 bge slb_miss_user_iseries
619 #endif
620 std r10,PACA_EXSLB+EX_R10(r13)
621 std r11,PACA_EXSLB+EX_R11(r13)
622 std r12,PACA_EXSLB+EX_R12(r13)
623 mfspr r10,SPRN_SPRG1
624 std r10,PACA_EXSLB+EX_R13(r13)
625 ld r12,PACALPPACAPTR(r13)
626 ld r12,LPPACASRR1(r12)
627 b .slb_miss_realmode
628
629 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
630
631 .globl instruction_access_slb_iSeries
632 instruction_access_slb_iSeries:
633 mtspr SPRN_SPRG1,r13 /* save r13 */
634 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
635 std r3,PACA_EXSLB+EX_R3(r13)
636 ld r3,PACALPPACAPTR(r13)
637 ld r3,LPPACASRR0(r3) /* get SRR0 value */
638 std r9,PACA_EXSLB+EX_R9(r13)
639 mfcr r9
640 #ifdef __DISABLED__
641 cmpdi r3,0
642 bge .slb_miss_user_iseries
643 #endif
644 std r10,PACA_EXSLB+EX_R10(r13)
645 std r11,PACA_EXSLB+EX_R11(r13)
646 std r12,PACA_EXSLB+EX_R12(r13)
647 mfspr r10,SPRN_SPRG1
648 std r10,PACA_EXSLB+EX_R13(r13)
649 ld r12,PACALPPACAPTR(r13)
650 ld r12,LPPACASRR1(r12)
651 b .slb_miss_realmode
652
653 #ifdef __DISABLED__
654 slb_miss_user_iseries:
655 std r10,PACA_EXGEN+EX_R10(r13)
656 std r11,PACA_EXGEN+EX_R11(r13)
657 std r12,PACA_EXGEN+EX_R12(r13)
658 mfspr r10,SPRG1
659 ld r11,PACA_EXSLB+EX_R9(r13)
660 ld r12,PACA_EXSLB+EX_R3(r13)
661 std r10,PACA_EXGEN+EX_R13(r13)
662 std r11,PACA_EXGEN+EX_R9(r13)
663 std r12,PACA_EXGEN+EX_R3(r13)
664 EXCEPTION_PROLOG_ISERIES_2
665 b slb_miss_user_common
666 #endif
667
668 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
669 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
670 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
671 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
672 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
673 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
674 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
675
676 .globl system_call_iSeries
677 system_call_iSeries:
678 mr r9,r13
679 mfspr r13,SPRN_SPRG3
680 EXCEPTION_PROLOG_ISERIES_2
681 b system_call_common
682
683 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
684 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
685 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
686
687 .globl system_reset_iSeries
688 system_reset_iSeries:
689 mfspr r13,SPRN_SPRG3 /* Get paca address */
690 mfmsr r24
691 ori r24,r24,MSR_RI
692 mtmsrd r24 /* RI on */
693 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
694 cmpwi 0,r24,0 /* Are we processor 0? */
695 beq .__start_initialization_iSeries /* Start up the first processor */
696 mfspr r4,SPRN_CTRLF
697 li r5,CTRL_RUNLATCH /* Turn off the run light */
698 andc r4,r4,r5
699 mtspr SPRN_CTRLT,r4
700
701 1:
702 HMT_LOW
703 #ifdef CONFIG_SMP
704 lbz r23,PACAPROCSTART(r13) /* Test if this processor
705 * should start */
706 sync
707 LOAD_REG_IMMEDIATE(r3,current_set)
708 sldi r28,r24,3 /* get current_set[cpu#] */
709 ldx r3,r3,r28
710 addi r1,r3,THREAD_SIZE
711 subi r1,r1,STACK_FRAME_OVERHEAD
712
713 cmpwi 0,r23,0
714 beq iSeries_secondary_smp_loop /* Loop until told to go */
715 bne .__secondary_start /* Loop until told to go */
716 iSeries_secondary_smp_loop:
717 /* Let the Hypervisor know we are alive */
718 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
719 lis r3,0x8002
720 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
721 #else /* CONFIG_SMP */
722 /* Yield the processor. This is required for non-SMP kernels
723 which are running on multi-threaded machines. */
724 lis r3,0x8000
725 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
726 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
727 li r4,0 /* "yield timed" */
728 li r5,-1 /* "yield forever" */
729 #endif /* CONFIG_SMP */
730 li r0,-1 /* r0=-1 indicates a Hypervisor call */
731 sc /* Invoke the hypervisor via a system call */
732 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
733 b 1b /* If SMP not configured, secondaries
734 * loop forever */
735
736 .globl decrementer_iSeries_masked
737 decrementer_iSeries_masked:
738 /* We may not have a valid TOC pointer in here. */
739 li r11,1
740 ld r12,PACALPPACAPTR(r13)
741 stb r11,LPPACADECRINT(r12)
742 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
743 lwz r12,0(r12)
744 mtspr SPRN_DEC,r12
745 /* fall through */
746
747 .globl hardware_interrupt_iSeries_masked
748 hardware_interrupt_iSeries_masked:
749 mtcrf 0x80,r9 /* Restore regs */
750 ld r12,PACALPPACAPTR(r13)
751 ld r11,LPPACASRR0(r12)
752 ld r12,LPPACASRR1(r12)
753 mtspr SPRN_SRR0,r11
754 mtspr SPRN_SRR1,r12
755 ld r9,PACA_EXGEN+EX_R9(r13)
756 ld r10,PACA_EXGEN+EX_R10(r13)
757 ld r11,PACA_EXGEN+EX_R11(r13)
758 ld r12,PACA_EXGEN+EX_R12(r13)
759 ld r13,PACA_EXGEN+EX_R13(r13)
760 rfid
761 b . /* prevent speculative execution */
762 #endif /* CONFIG_PPC_ISERIES */
763
764 /*** Common interrupt handlers ***/
765
766 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
767
768 /*
769 * Machine check is different because we use a different
770 * save area: PACA_EXMC instead of PACA_EXGEN.
771 */
772 .align 7
773 .globl machine_check_common
774 machine_check_common:
775 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
776 DISABLE_INTS
777 bl .save_nvgprs
778 addi r3,r1,STACK_FRAME_OVERHEAD
779 bl .machine_check_exception
780 b .ret_from_except
781
782 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
783 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
784 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
785 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
786 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
787 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
788 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
789 #ifdef CONFIG_ALTIVEC
790 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
791 #else
792 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
793 #endif
794
795 /*
796 * Here we have detected that the kernel stack pointer is bad.
797 * R9 contains the saved CR, r13 points to the paca,
798 * r10 contains the (bad) kernel stack pointer,
799 * r11 and r12 contain the saved SRR0 and SRR1.
800 * We switch to using an emergency stack, save the registers there,
801 * and call kernel_bad_stack(), which panics.
802 */
803 bad_stack:
804 ld r1,PACAEMERGSP(r13)
805 subi r1,r1,64+INT_FRAME_SIZE
806 std r9,_CCR(r1)
807 std r10,GPR1(r1)
808 std r11,_NIP(r1)
809 std r12,_MSR(r1)
810 mfspr r11,SPRN_DAR
811 mfspr r12,SPRN_DSISR
812 std r11,_DAR(r1)
813 std r12,_DSISR(r1)
814 mflr r10
815 mfctr r11
816 mfxer r12
817 std r10,_LINK(r1)
818 std r11,_CTR(r1)
819 std r12,_XER(r1)
820 SAVE_GPR(0,r1)
821 SAVE_GPR(2,r1)
822 SAVE_4GPRS(3,r1)
823 SAVE_2GPRS(7,r1)
824 SAVE_10GPRS(12,r1)
825 SAVE_10GPRS(22,r1)
826 addi r11,r1,INT_FRAME_SIZE
827 std r11,0(r1)
828 li r12,0
829 std r12,0(r11)
830 ld r2,PACATOC(r13)
831 1: addi r3,r1,STACK_FRAME_OVERHEAD
832 bl .kernel_bad_stack
833 b 1b
834
835 /*
836 * Return from an exception with minimal checks.
837 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
838 * If interrupts have been enabled, or anything has been
839 * done that might have changed the scheduling status of
840 * any task or sent any task a signal, you should use
841 * ret_from_except or ret_from_except_lite instead of this.
842 */
843 .globl fast_exception_return
844 fast_exception_return:
845 ld r12,_MSR(r1)
846 ld r11,_NIP(r1)
847 andi. r3,r12,MSR_RI /* check if RI is set */
848 beq- unrecov_fer
849 ld r3,_CCR(r1)
850 ld r4,_LINK(r1)
851 ld r5,_CTR(r1)
852 ld r6,_XER(r1)
853 mtcr r3
854 mtlr r4
855 mtctr r5
856 mtxer r6
857 REST_GPR(0, r1)
858 REST_8GPRS(2, r1)
859
860 mfmsr r10
861 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
862 mtmsrd r10,1
863
864 mtspr SPRN_SRR1,r12
865 mtspr SPRN_SRR0,r11
866 REST_4GPRS(10, r1)
867 ld r1,GPR1(r1)
868 rfid
869 b . /* prevent speculative execution */
870
871 unrecov_fer:
872 bl .save_nvgprs
873 1: addi r3,r1,STACK_FRAME_OVERHEAD
874 bl .unrecoverable_exception
875 b 1b
876
877 /*
878 * Here r13 points to the paca, r9 contains the saved CR,
879 * SRR0 and SRR1 are saved in r11 and r12,
880 * r9 - r13 are saved in paca->exgen.
881 */
882 .align 7
883 .globl data_access_common
884 data_access_common:
885 mfspr r10,SPRN_DAR
886 std r10,PACA_EXGEN+EX_DAR(r13)
887 mfspr r10,SPRN_DSISR
888 stw r10,PACA_EXGEN+EX_DSISR(r13)
889 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
890 ld r3,PACA_EXGEN+EX_DAR(r13)
891 lwz r4,PACA_EXGEN+EX_DSISR(r13)
892 li r5,0x300
893 b .do_hash_page /* Try to handle as hpte fault */
894
895 .align 7
896 .globl instruction_access_common
897 instruction_access_common:
898 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
899 ld r3,_NIP(r1)
900 andis. r4,r12,0x5820
901 li r5,0x400
902 b .do_hash_page /* Try to handle as hpte fault */
903
904 /*
905 * Here is the common SLB miss user that is used when going to virtual
906 * mode for SLB misses, that is currently not used
907 */
908 #ifdef __DISABLED__
909 .align 7
910 .globl slb_miss_user_common
911 slb_miss_user_common:
912 mflr r10
913 std r3,PACA_EXGEN+EX_DAR(r13)
914 stw r9,PACA_EXGEN+EX_CCR(r13)
915 std r10,PACA_EXGEN+EX_LR(r13)
916 std r11,PACA_EXGEN+EX_SRR0(r13)
917 bl .slb_allocate_user
918
919 ld r10,PACA_EXGEN+EX_LR(r13)
920 ld r3,PACA_EXGEN+EX_R3(r13)
921 lwz r9,PACA_EXGEN+EX_CCR(r13)
922 ld r11,PACA_EXGEN+EX_SRR0(r13)
923 mtlr r10
924 beq- slb_miss_fault
925
926 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
927 beq- unrecov_user_slb
928 mfmsr r10
929
930 .machine push
931 .machine "power4"
932 mtcrf 0x80,r9
933 .machine pop
934
935 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
936 mtmsrd r10,1
937
938 mtspr SRR0,r11
939 mtspr SRR1,r12
940
941 ld r9,PACA_EXGEN+EX_R9(r13)
942 ld r10,PACA_EXGEN+EX_R10(r13)
943 ld r11,PACA_EXGEN+EX_R11(r13)
944 ld r12,PACA_EXGEN+EX_R12(r13)
945 ld r13,PACA_EXGEN+EX_R13(r13)
946 rfid
947 b .
948
949 slb_miss_fault:
950 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
951 ld r4,PACA_EXGEN+EX_DAR(r13)
952 li r5,0
953 std r4,_DAR(r1)
954 std r5,_DSISR(r1)
955 b .handle_page_fault
956
957 unrecov_user_slb:
958 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
959 DISABLE_INTS
960 bl .save_nvgprs
961 1: addi r3,r1,STACK_FRAME_OVERHEAD
962 bl .unrecoverable_exception
963 b 1b
964
965 #endif /* __DISABLED__ */
966
967
968 /*
969 * r13 points to the PACA, r9 contains the saved CR,
970 * r12 contain the saved SRR1, SRR0 is still ready for return
971 * r3 has the faulting address
972 * r9 - r13 are saved in paca->exslb.
973 * r3 is saved in paca->slb_r3
974 * We assume we aren't going to take any exceptions during this procedure.
975 */
976 _GLOBAL(slb_miss_realmode)
977 mflr r10
978
979 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
980 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
981
982 bl .slb_allocate_realmode
983
984 /* All done -- return from exception. */
985
986 ld r10,PACA_EXSLB+EX_LR(r13)
987 ld r3,PACA_EXSLB+EX_R3(r13)
988 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
989 #ifdef CONFIG_PPC_ISERIES
990 ld r11,PACALPPACAPTR(r13)
991 ld r11,LPPACASRR0(r11) /* get SRR0 value */
992 #endif /* CONFIG_PPC_ISERIES */
993
994 mtlr r10
995
996 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
997 beq- unrecov_slb
998
999 .machine push
1000 .machine "power4"
1001 mtcrf 0x80,r9
1002 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1003 .machine pop
1004
1005 #ifdef CONFIG_PPC_ISERIES
1006 mtspr SPRN_SRR0,r11
1007 mtspr SPRN_SRR1,r12
1008 #endif /* CONFIG_PPC_ISERIES */
1009 ld r9,PACA_EXSLB+EX_R9(r13)
1010 ld r10,PACA_EXSLB+EX_R10(r13)
1011 ld r11,PACA_EXSLB+EX_R11(r13)
1012 ld r12,PACA_EXSLB+EX_R12(r13)
1013 ld r13,PACA_EXSLB+EX_R13(r13)
1014 rfid
1015 b . /* prevent speculative execution */
1016
1017 unrecov_slb:
1018 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1019 DISABLE_INTS
1020 bl .save_nvgprs
1021 1: addi r3,r1,STACK_FRAME_OVERHEAD
1022 bl .unrecoverable_exception
1023 b 1b
1024
1025 .align 7
1026 .globl hardware_interrupt_common
1027 .globl hardware_interrupt_entry
1028 hardware_interrupt_common:
1029 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1030 hardware_interrupt_entry:
1031 DISABLE_INTS
1032 bl .ppc64_runlatch_on
1033 addi r3,r1,STACK_FRAME_OVERHEAD
1034 bl .do_IRQ
1035 b .ret_from_except_lite
1036
1037 .align 7
1038 .globl alignment_common
1039 alignment_common:
1040 mfspr r10,SPRN_DAR
1041 std r10,PACA_EXGEN+EX_DAR(r13)
1042 mfspr r10,SPRN_DSISR
1043 stw r10,PACA_EXGEN+EX_DSISR(r13)
1044 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1045 ld r3,PACA_EXGEN+EX_DAR(r13)
1046 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1047 std r3,_DAR(r1)
1048 std r4,_DSISR(r1)
1049 bl .save_nvgprs
1050 addi r3,r1,STACK_FRAME_OVERHEAD
1051 ENABLE_INTS
1052 bl .alignment_exception
1053 b .ret_from_except
1054
1055 .align 7
1056 .globl program_check_common
1057 program_check_common:
1058 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1059 bl .save_nvgprs
1060 addi r3,r1,STACK_FRAME_OVERHEAD
1061 ENABLE_INTS
1062 bl .program_check_exception
1063 b .ret_from_except
1064
1065 .align 7
1066 .globl fp_unavailable_common
1067 fp_unavailable_common:
1068 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1069 bne .load_up_fpu /* if from user, just load it up */
1070 bl .save_nvgprs
1071 addi r3,r1,STACK_FRAME_OVERHEAD
1072 ENABLE_INTS
1073 bl .kernel_fp_unavailable_exception
1074 BUG_OPCODE
1075
1076 .align 7
1077 .globl altivec_unavailable_common
1078 altivec_unavailable_common:
1079 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1080 #ifdef CONFIG_ALTIVEC
1081 BEGIN_FTR_SECTION
1082 bne .load_up_altivec /* if from user, just load it up */
1083 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1084 #endif
1085 bl .save_nvgprs
1086 addi r3,r1,STACK_FRAME_OVERHEAD
1087 ENABLE_INTS
1088 bl .altivec_unavailable_exception
1089 b .ret_from_except
1090
1091 #ifdef CONFIG_ALTIVEC
1092 /*
1093 * load_up_altivec(unused, unused, tsk)
1094 * Disable VMX for the task which had it previously,
1095 * and save its vector registers in its thread_struct.
1096 * Enables the VMX for use in the kernel on return.
1097 * On SMP we know the VMX is free, since we give it up every
1098 * switch (ie, no lazy save of the vector registers).
1099 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1100 */
1101 _STATIC(load_up_altivec)
1102 mfmsr r5 /* grab the current MSR */
1103 oris r5,r5,MSR_VEC@h
1104 mtmsrd r5 /* enable use of VMX now */
1105 isync
1106
1107 /*
1108 * For SMP, we don't do lazy VMX switching because it just gets too
1109 * horrendously complex, especially when a task switches from one CPU
1110 * to another. Instead we call giveup_altvec in switch_to.
1111 * VRSAVE isn't dealt with here, that is done in the normal context
1112 * switch code. Note that we could rely on vrsave value to eventually
1113 * avoid saving all of the VREGs here...
1114 */
1115 #ifndef CONFIG_SMP
1116 ld r3,last_task_used_altivec@got(r2)
1117 ld r4,0(r3)
1118 cmpdi 0,r4,0
1119 beq 1f
1120 /* Save VMX state to last_task_used_altivec's THREAD struct */
1121 addi r4,r4,THREAD
1122 SAVE_32VRS(0,r5,r4)
1123 mfvscr vr0
1124 li r10,THREAD_VSCR
1125 stvx vr0,r10,r4
1126 /* Disable VMX for last_task_used_altivec */
1127 ld r5,PT_REGS(r4)
1128 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1129 lis r6,MSR_VEC@h
1130 andc r4,r4,r6
1131 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1132 1:
1133 #endif /* CONFIG_SMP */
1134 /* Hack: if we get an altivec unavailable trap with VRSAVE
1135 * set to all zeros, we assume this is a broken application
1136 * that fails to set it properly, and thus we switch it to
1137 * all 1's
1138 */
1139 mfspr r4,SPRN_VRSAVE
1140 cmpdi 0,r4,0
1141 bne+ 1f
1142 li r4,-1
1143 mtspr SPRN_VRSAVE,r4
1144 1:
1145 /* enable use of VMX after return */
1146 ld r4,PACACURRENT(r13)
1147 addi r5,r4,THREAD /* Get THREAD */
1148 oris r12,r12,MSR_VEC@h
1149 std r12,_MSR(r1)
1150 li r4,1
1151 li r10,THREAD_VSCR
1152 stw r4,THREAD_USED_VR(r5)
1153 lvx vr0,r10,r5
1154 mtvscr vr0
1155 REST_32VRS(0,r4,r5)
1156 #ifndef CONFIG_SMP
1157 /* Update last_task_used_math to 'current' */
1158 subi r4,r5,THREAD /* Back to 'current' */
1159 std r4,0(r3)
1160 #endif /* CONFIG_SMP */
1161 /* restore registers and return */
1162 b fast_exception_return
1163 #endif /* CONFIG_ALTIVEC */
1164
1165 /*
1166 * Hash table stuff
1167 */
1168 .align 7
1169 _GLOBAL(do_hash_page)
1170 std r3,_DAR(r1)
1171 std r4,_DSISR(r1)
1172
1173 andis. r0,r4,0xa450 /* weird error? */
1174 bne- .handle_page_fault /* if not, try to insert a HPTE */
1175 BEGIN_FTR_SECTION
1176 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1177 bne- .do_ste_alloc /* If so handle it */
1178 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1179
1180 /*
1181 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1182 * accessing a userspace segment (even from the kernel). We assume
1183 * kernel addresses always have the high bit set.
1184 */
1185 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1186 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1187 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1188 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1189 ori r4,r4,1 /* add _PAGE_PRESENT */
1190 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1191
1192 /*
1193 * On iSeries, we soft-disable interrupts here, then
1194 * hard-enable interrupts so that the hash_page code can spin on
1195 * the hash_table_lock without problems on a shared processor.
1196 */
1197 DISABLE_INTS
1198
1199 /*
1200 * r3 contains the faulting address
1201 * r4 contains the required access permissions
1202 * r5 contains the trap number
1203 *
1204 * at return r3 = 0 for success
1205 */
1206 bl .hash_page /* build HPTE if possible */
1207 cmpdi r3,0 /* see if hash_page succeeded */
1208
1209 #ifdef DO_SOFT_DISABLE
1210 /*
1211 * If we had interrupts soft-enabled at the point where the
1212 * DSI/ISI occurred, and an interrupt came in during hash_page,
1213 * handle it now.
1214 * We jump to ret_from_except_lite rather than fast_exception_return
1215 * because ret_from_except_lite will check for and handle pending
1216 * interrupts if necessary.
1217 */
1218 beq .ret_from_except_lite
1219 /* For a hash failure, we don't bother re-enabling interrupts */
1220 ble- 12f
1221
1222 /*
1223 * hash_page couldn't handle it, set soft interrupt enable back
1224 * to what it was before the trap. Note that .local_irq_restore
1225 * handles any interrupts pending at this point.
1226 */
1227 ld r3,SOFTE(r1)
1228 bl .local_irq_restore
1229 b 11f
1230 #else
1231 beq fast_exception_return /* Return from exception on success */
1232 ble- 12f /* Failure return from hash_page */
1233
1234 /* fall through */
1235 #endif
1236
1237 /* Here we have a page fault that hash_page can't handle. */
1238 _GLOBAL(handle_page_fault)
1239 ENABLE_INTS
1240 11: ld r4,_DAR(r1)
1241 ld r5,_DSISR(r1)
1242 addi r3,r1,STACK_FRAME_OVERHEAD
1243 bl .do_page_fault
1244 cmpdi r3,0
1245 beq+ .ret_from_except_lite
1246 bl .save_nvgprs
1247 mr r5,r3
1248 addi r3,r1,STACK_FRAME_OVERHEAD
1249 lwz r4,_DAR(r1)
1250 bl .bad_page_fault
1251 b .ret_from_except
1252
1253 /* We have a page fault that hash_page could handle but HV refused
1254 * the PTE insertion
1255 */
1256 12: bl .save_nvgprs
1257 addi r3,r1,STACK_FRAME_OVERHEAD
1258 lwz r4,_DAR(r1)
1259 bl .low_hash_fault
1260 b .ret_from_except
1261
1262 /* here we have a segment miss */
1263 _GLOBAL(do_ste_alloc)
1264 bl .ste_allocate /* try to insert stab entry */
1265 cmpdi r3,0
1266 beq+ fast_exception_return
1267 b .handle_page_fault
1268
1269 /*
1270 * r13 points to the PACA, r9 contains the saved CR,
1271 * r11 and r12 contain the saved SRR0 and SRR1.
1272 * r9 - r13 are saved in paca->exslb.
1273 * We assume we aren't going to take any exceptions during this procedure.
1274 * We assume (DAR >> 60) == 0xc.
1275 */
1276 .align 7
1277 _GLOBAL(do_stab_bolted)
1278 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1279 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1280
1281 /* Hash to the primary group */
1282 ld r10,PACASTABVIRT(r13)
1283 mfspr r11,SPRN_DAR
1284 srdi r11,r11,28
1285 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1286
1287 /* Calculate VSID */
1288 /* This is a kernel address, so protovsid = ESID */
1289 ASM_VSID_SCRAMBLE(r11, r9)
1290 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1291
1292 /* Search the primary group for a free entry */
1293 1: ld r11,0(r10) /* Test valid bit of the current ste */
1294 andi. r11,r11,0x80
1295 beq 2f
1296 addi r10,r10,16
1297 andi. r11,r10,0x70
1298 bne 1b
1299
1300 /* Stick for only searching the primary group for now. */
1301 /* At least for now, we use a very simple random castout scheme */
1302 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1303 mftb r11
1304 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1305 ori r11,r11,0x10
1306
1307 /* r10 currently points to an ste one past the group of interest */
1308 /* make it point to the randomly selected entry */
1309 subi r10,r10,128
1310 or r10,r10,r11 /* r10 is the entry to invalidate */
1311
1312 isync /* mark the entry invalid */
1313 ld r11,0(r10)
1314 rldicl r11,r11,56,1 /* clear the valid bit */
1315 rotldi r11,r11,8
1316 std r11,0(r10)
1317 sync
1318
1319 clrrdi r11,r11,28 /* Get the esid part of the ste */
1320 slbie r11
1321
1322 2: std r9,8(r10) /* Store the vsid part of the ste */
1323 eieio
1324
1325 mfspr r11,SPRN_DAR /* Get the new esid */
1326 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1327 ori r11,r11,0x90 /* Turn on valid and kp */
1328 std r11,0(r10) /* Put new entry back into the stab */
1329
1330 sync
1331
1332 /* All done -- return from exception. */
1333 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1334 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1335
1336 andi. r10,r12,MSR_RI
1337 beq- unrecov_slb
1338
1339 mtcrf 0x80,r9 /* restore CR */
1340
1341 mfmsr r10
1342 clrrdi r10,r10,2
1343 mtmsrd r10,1
1344
1345 mtspr SPRN_SRR0,r11
1346 mtspr SPRN_SRR1,r12
1347 ld r9,PACA_EXSLB+EX_R9(r13)
1348 ld r10,PACA_EXSLB+EX_R10(r13)
1349 ld r11,PACA_EXSLB+EX_R11(r13)
1350 ld r12,PACA_EXSLB+EX_R12(r13)
1351 ld r13,PACA_EXSLB+EX_R13(r13)
1352 rfid
1353 b . /* prevent speculative execution */
1354
1355 /*
1356 * Space for CPU0's segment table.
1357 *
1358 * On iSeries, the hypervisor must fill in at least one entry before
1359 * we get control (with relocate on). The address is give to the hv
1360 * as a page number (see xLparMap in lpardata.c), so this must be at a
1361 * fixed address (the linker can't compute (u64)&initial_stab >>
1362 * PAGE_SHIFT).
1363 */
1364 . = STAB0_OFFSET /* 0x6000 */
1365 .globl initial_stab
1366 initial_stab:
1367 .space 4096
1368
1369 /*
1370 * Data area reserved for FWNMI option.
1371 * This address (0x7000) is fixed by the RPA.
1372 */
1373 .= 0x7000
1374 .globl fwnmi_data_area
1375 fwnmi_data_area:
1376
1377 /* iSeries does not use the FWNMI stuff, so it is safe to put
1378 * this here, even if we later allow kernels that will boot on
1379 * both pSeries and iSeries */
1380 #ifdef CONFIG_PPC_ISERIES
1381 . = LPARMAP_PHYS
1382 #include "lparmap.s"
1383 /*
1384 * This ".text" is here for old compilers that generate a trailing
1385 * .note section when compiling .c files to .s
1386 */
1387 .text
1388 #endif /* CONFIG_PPC_ISERIES */
1389
1390 . = 0x8000
1391
1392 /*
1393 * On pSeries, secondary processors spin in the following code.
1394 * At entry, r3 = this processor's number (physical cpu id)
1395 */
1396 _GLOBAL(pSeries_secondary_smp_init)
1397 mr r24,r3
1398
1399 /* turn on 64-bit mode */
1400 bl .enable_64b_mode
1401 isync
1402
1403 /* Copy some CPU settings from CPU 0 */
1404 bl .__restore_cpu_setup
1405
1406 /* Set up a paca value for this processor. Since we have the
1407 * physical cpu id in r24, we need to search the pacas to find
1408 * which logical id maps to our physical one.
1409 */
1410 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1411 li r5,0 /* logical cpu id */
1412 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1413 cmpw r6,r24 /* Compare to our id */
1414 beq 2f
1415 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1416 addi r5,r5,1
1417 cmpwi r5,NR_CPUS
1418 blt 1b
1419
1420 mr r3,r24 /* not found, copy phys to r3 */
1421 b .kexec_wait /* next kernel might do better */
1422
1423 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1424 /* From now on, r24 is expected to be logical cpuid */
1425 mr r24,r5
1426 3: HMT_LOW
1427 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1428 /* start. */
1429 sync
1430
1431 /* Create a temp kernel stack for use before relocation is on. */
1432 ld r1,PACAEMERGSP(r13)
1433 subi r1,r1,STACK_FRAME_OVERHEAD
1434
1435 cmpwi 0,r23,0
1436 #ifdef CONFIG_SMP
1437 bne .__secondary_start
1438 #endif
1439 b 3b /* Loop until told to go */
1440
1441 #ifdef CONFIG_PPC_ISERIES
1442 _STATIC(__start_initialization_iSeries)
1443 /* Clear out the BSS */
1444 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1445 LOAD_REG_IMMEDIATE(r8,__bss_start)
1446 sub r11,r11,r8 /* bss size */
1447 addi r11,r11,7 /* round up to an even double word */
1448 rldicl. r11,r11,61,3 /* shift right by 3 */
1449 beq 4f
1450 addi r8,r8,-8
1451 li r0,0
1452 mtctr r11 /* zero this many doublewords */
1453 3: stdu r0,8(r8)
1454 bdnz 3b
1455 4:
1456 LOAD_REG_IMMEDIATE(r1,init_thread_union)
1457 addi r1,r1,THREAD_SIZE
1458 li r0,0
1459 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1460
1461 LOAD_REG_IMMEDIATE(r3,cpu_specs)
1462 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1463 li r5,0
1464 bl .identify_cpu
1465
1466 LOAD_REG_IMMEDIATE(r2,__toc_start)
1467 addi r2,r2,0x4000
1468 addi r2,r2,0x4000
1469
1470 bl .iSeries_early_setup
1471 bl .early_setup
1472
1473 /* relocation is on at this point */
1474
1475 b .start_here_common
1476 #endif /* CONFIG_PPC_ISERIES */
1477
1478 #ifdef CONFIG_PPC_MULTIPLATFORM
1479
1480 _STATIC(__mmu_off)
1481 mfmsr r3
1482 andi. r0,r3,MSR_IR|MSR_DR
1483 beqlr
1484 andc r3,r3,r0
1485 mtspr SPRN_SRR0,r4
1486 mtspr SPRN_SRR1,r3
1487 sync
1488 rfid
1489 b . /* prevent speculative execution */
1490
1491
1492 /*
1493 * Here is our main kernel entry point. We support currently 2 kind of entries
1494 * depending on the value of r5.
1495 *
1496 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1497 * in r3...r7
1498 *
1499 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1500 * DT block, r4 is a physical pointer to the kernel itself
1501 *
1502 */
1503 _GLOBAL(__start_initialization_multiplatform)
1504 #ifdef CONFIG_PPC_MULTIPLATFORM
1505 /*
1506 * Are we booted from a PROM Of-type client-interface ?
1507 */
1508 cmpldi cr0,r5,0
1509 bne .__boot_from_prom /* yes -> prom */
1510 #endif
1511
1512 /* Save parameters */
1513 mr r31,r3
1514 mr r30,r4
1515
1516 /* Make sure we are running in 64 bits mode */
1517 bl .enable_64b_mode
1518
1519 /* Setup some critical 970 SPRs before switching MMU off */
1520 bl .__970_cpu_preinit
1521
1522 /* cpu # */
1523 li r24,0
1524
1525 /* Switch off MMU if not already */
1526 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1527 add r4,r4,r30
1528 bl .__mmu_off
1529 b .__after_prom_start
1530
1531 #ifdef CONFIG_PPC_MULTIPLATFORM
1532 _STATIC(__boot_from_prom)
1533 /* Save parameters */
1534 mr r31,r3
1535 mr r30,r4
1536 mr r29,r5
1537 mr r28,r6
1538 mr r27,r7
1539
1540 /* Make sure we are running in 64 bits mode */
1541 bl .enable_64b_mode
1542
1543 /* put a relocation offset into r3 */
1544 bl .reloc_offset
1545
1546 LOAD_REG_IMMEDIATE(r2,__toc_start)
1547 addi r2,r2,0x4000
1548 addi r2,r2,0x4000
1549
1550 /* Relocate the TOC from a virt addr to a real addr */
1551 add r2,r2,r3
1552
1553 /* Restore parameters */
1554 mr r3,r31
1555 mr r4,r30
1556 mr r5,r29
1557 mr r6,r28
1558 mr r7,r27
1559
1560 /* Do all of the interaction with OF client interface */
1561 bl .prom_init
1562 /* We never return */
1563 trap
1564 #endif
1565
1566 /*
1567 * At this point, r3 contains the physical address we are running at,
1568 * returned by prom_init()
1569 */
1570 _STATIC(__after_prom_start)
1571
1572 /*
1573 * We need to run with __start at physical address PHYSICAL_START.
1574 * This will leave some code in the first 256B of
1575 * real memory, which are reserved for software use.
1576 * The remainder of the first page is loaded with the fixed
1577 * interrupt vectors. The next two pages are filled with
1578 * unknown exception placeholders.
1579 *
1580 * Note: This process overwrites the OF exception vectors.
1581 * r26 == relocation offset
1582 * r27 == KERNELBASE
1583 */
1584 bl .reloc_offset
1585 mr r26,r3
1586 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1587
1588 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1589
1590 // XXX FIXME: Use phys returned by OF (r30)
1591 add r4,r27,r26 /* source addr */
1592 /* current address of _start */
1593 /* i.e. where we are running */
1594 /* the source addr */
1595
1596 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1597 sub r5,r5,r27
1598
1599 li r6,0x100 /* Start offset, the first 0x100 */
1600 /* bytes were copied earlier. */
1601
1602 bl .copy_and_flush /* copy the first n bytes */
1603 /* this includes the code being */
1604 /* executed here. */
1605
1606 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1607 mtctr r0 /* that we just made/relocated */
1608 bctr
1609
1610 4: LOAD_REG_IMMEDIATE(r5,klimit)
1611 add r5,r5,r26
1612 ld r5,0(r5) /* get the value of klimit */
1613 sub r5,r5,r27
1614 bl .copy_and_flush /* copy the rest */
1615 b .start_here_multiplatform
1616
1617 #endif /* CONFIG_PPC_MULTIPLATFORM */
1618
1619 /*
1620 * Copy routine used to copy the kernel to start at physical address 0
1621 * and flush and invalidate the caches as needed.
1622 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1623 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1624 *
1625 * Note: this routine *only* clobbers r0, r6 and lr
1626 */
1627 _GLOBAL(copy_and_flush)
1628 addi r5,r5,-8
1629 addi r6,r6,-8
1630 4: li r0,16 /* Use the least common */
1631 /* denominator cache line */
1632 /* size. This results in */
1633 /* extra cache line flushes */
1634 /* but operation is correct. */
1635 /* Can't get cache line size */
1636 /* from NACA as it is being */
1637 /* moved too. */
1638
1639 mtctr r0 /* put # words/line in ctr */
1640 3: addi r6,r6,8 /* copy a cache line */
1641 ldx r0,r6,r4
1642 stdx r0,r6,r3
1643 bdnz 3b
1644 dcbst r6,r3 /* write it to memory */
1645 sync
1646 icbi r6,r3 /* flush the icache line */
1647 cmpld 0,r6,r5
1648 blt 4b
1649 sync
1650 addi r5,r5,8
1651 addi r6,r6,8
1652 blr
1653
1654 .align 8
1655 copy_to_here:
1656
1657 #ifdef CONFIG_SMP
1658 #ifdef CONFIG_PPC_PMAC
1659 /*
1660 * On PowerMac, secondary processors starts from the reset vector, which
1661 * is temporarily turned into a call to one of the functions below.
1662 */
1663 .section ".text";
1664 .align 2 ;
1665
1666 .globl __secondary_start_pmac_0
1667 __secondary_start_pmac_0:
1668 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1669 li r24,0
1670 b 1f
1671 li r24,1
1672 b 1f
1673 li r24,2
1674 b 1f
1675 li r24,3
1676 1:
1677
1678 _GLOBAL(pmac_secondary_start)
1679 /* turn on 64-bit mode */
1680 bl .enable_64b_mode
1681 isync
1682
1683 /* Copy some CPU settings from CPU 0 */
1684 bl .__restore_cpu_setup
1685
1686 /* pSeries do that early though I don't think we really need it */
1687 mfmsr r3
1688 ori r3,r3,MSR_RI
1689 mtmsrd r3 /* RI on */
1690
1691 /* Set up a paca value for this processor. */
1692 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1693 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1694 add r13,r13,r4 /* for this processor. */
1695 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1696
1697 /* Create a temp kernel stack for use before relocation is on. */
1698 ld r1,PACAEMERGSP(r13)
1699 subi r1,r1,STACK_FRAME_OVERHEAD
1700
1701 b .__secondary_start
1702
1703 #endif /* CONFIG_PPC_PMAC */
1704
1705 /*
1706 * This function is called after the master CPU has released the
1707 * secondary processors. The execution environment is relocation off.
1708 * The paca for this processor has the following fields initialized at
1709 * this point:
1710 * 1. Processor number
1711 * 2. Segment table pointer (virtual address)
1712 * On entry the following are set:
1713 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1714 * r24 = cpu# (in Linux terms)
1715 * r13 = paca virtual address
1716 * SPRG3 = paca virtual address
1717 */
1718 _GLOBAL(__secondary_start)
1719 /* Set thread priority to MEDIUM */
1720 HMT_MEDIUM
1721
1722 /* Load TOC */
1723 ld r2,PACATOC(r13)
1724
1725 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1726 bl .early_setup_secondary
1727
1728 /* Initialize the kernel stack. Just a repeat for iSeries. */
1729 LOAD_REG_ADDR(r3, current_set)
1730 sldi r28,r24,3 /* get current_set[cpu#] */
1731 ldx r1,r3,r28
1732 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1733 std r1,PACAKSAVE(r13)
1734
1735 /* Clear backchain so we get nice backtraces */
1736 li r7,0
1737 mtlr r7
1738
1739 /* enable MMU and jump to start_secondary */
1740 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1741 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1742 #ifdef DO_SOFT_DISABLE
1743 ori r4,r4,MSR_EE
1744 #endif
1745 mtspr SPRN_SRR0,r3
1746 mtspr SPRN_SRR1,r4
1747 rfid
1748 b . /* prevent speculative execution */
1749
1750 /*
1751 * Running with relocation on at this point. All we want to do is
1752 * zero the stack back-chain pointer before going into C code.
1753 */
1754 _GLOBAL(start_secondary_prolog)
1755 li r3,0
1756 std r3,0(r1) /* Zero the stack frame pointer */
1757 bl .start_secondary
1758 b .
1759 #endif
1760
1761 /*
1762 * This subroutine clobbers r11 and r12
1763 */
1764 _GLOBAL(enable_64b_mode)
1765 mfmsr r11 /* grab the current MSR */
1766 li r12,1
1767 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1768 or r11,r11,r12
1769 li r12,1
1770 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1771 or r11,r11,r12
1772 mtmsrd r11
1773 isync
1774 blr
1775
1776 #ifdef CONFIG_PPC_MULTIPLATFORM
1777 /*
1778 * This is where the main kernel code starts.
1779 */
1780 _STATIC(start_here_multiplatform)
1781 /* get a new offset, now that the kernel has moved. */
1782 bl .reloc_offset
1783 mr r26,r3
1784
1785 /* Clear out the BSS. It may have been done in prom_init,
1786 * already but that's irrelevant since prom_init will soon
1787 * be detached from the kernel completely. Besides, we need
1788 * to clear it now for kexec-style entry.
1789 */
1790 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1791 LOAD_REG_IMMEDIATE(r8,__bss_start)
1792 sub r11,r11,r8 /* bss size */
1793 addi r11,r11,7 /* round up to an even double word */
1794 rldicl. r11,r11,61,3 /* shift right by 3 */
1795 beq 4f
1796 addi r8,r8,-8
1797 li r0,0
1798 mtctr r11 /* zero this many doublewords */
1799 3: stdu r0,8(r8)
1800 bdnz 3b
1801 4:
1802
1803 mfmsr r6
1804 ori r6,r6,MSR_RI
1805 mtmsrd r6 /* RI on */
1806
1807 /* The following gets the stack and TOC set up with the regs */
1808 /* pointing to the real addr of the kernel stack. This is */
1809 /* all done to support the C function call below which sets */
1810 /* up the htab. This is done because we have relocated the */
1811 /* kernel but are still running in real mode. */
1812
1813 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1814 add r3,r3,r26
1815
1816 /* set up a stack pointer (physical address) */
1817 addi r1,r3,THREAD_SIZE
1818 li r0,0
1819 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1820
1821 /* set up the TOC (physical address) */
1822 LOAD_REG_IMMEDIATE(r2,__toc_start)
1823 addi r2,r2,0x4000
1824 addi r2,r2,0x4000
1825 add r2,r2,r26
1826
1827 LOAD_REG_IMMEDIATE(r3, cpu_specs)
1828 add r3,r3,r26
1829 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1830 add r4,r4,r26
1831 mr r5,r26
1832 bl .identify_cpu
1833
1834 /* Save some low level config HIDs of CPU0 to be copied to
1835 * other CPUs later on, or used for suspend/resume
1836 */
1837 bl .__save_cpu_setup
1838 sync
1839
1840 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1841 * note that boot_cpuid can always be 0 nowadays since there is
1842 * nowhere it can be initialized differently before we reach this
1843 * code
1844 */
1845 LOAD_REG_IMMEDIATE(r27, boot_cpuid)
1846 add r27,r27,r26
1847 lwz r27,0(r27)
1848
1849 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
1850 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1851 add r13,r13,r24 /* for this processor. */
1852 add r13,r13,r26 /* convert to physical addr */
1853 mtspr SPRN_SPRG3,r13
1854
1855 /* Do very early kernel initializations, including initial hash table,
1856 * stab and slb setup before we turn on relocation. */
1857
1858 /* Restore parameters passed from prom_init/kexec */
1859 mr r3,r31
1860 bl .early_setup
1861
1862 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1863 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1864 mtspr SPRN_SRR0,r3
1865 mtspr SPRN_SRR1,r4
1866 rfid
1867 b . /* prevent speculative execution */
1868 #endif /* CONFIG_PPC_MULTIPLATFORM */
1869
1870 /* This is where all platforms converge execution */
1871 _STATIC(start_here_common)
1872 /* relocation is on at this point */
1873
1874 /* The following code sets up the SP and TOC now that we are */
1875 /* running with translation enabled. */
1876
1877 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1878
1879 /* set up the stack */
1880 addi r1,r3,THREAD_SIZE
1881 li r0,0
1882 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1883
1884 /* Apply the CPUs-specific fixups (nop out sections not relevant
1885 * to this CPU
1886 */
1887 li r3,0
1888 bl .do_cpu_ftr_fixups
1889
1890 LOAD_REG_IMMEDIATE(r26, boot_cpuid)
1891 lwz r26,0(r26)
1892
1893 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
1894 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1895 add r13,r13,r24 /* for this processor. */
1896 mtspr SPRN_SPRG3,r13
1897
1898 /* ptr to current */
1899 LOAD_REG_IMMEDIATE(r4, init_task)
1900 std r4,PACACURRENT(r13)
1901
1902 /* Load the TOC */
1903 ld r2,PACATOC(r13)
1904 std r1,PACAKSAVE(r13)
1905
1906 bl .setup_system
1907
1908 /* Load up the kernel context */
1909 5:
1910 #ifdef DO_SOFT_DISABLE
1911 li r5,0
1912 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1913 mfmsr r5
1914 ori r5,r5,MSR_EE /* Hard Enabled */
1915 mtmsrd r5
1916 #endif
1917
1918 bl .start_kernel
1919
1920 /* Not reached */
1921 BUG_OPCODE
1922
1923 /*
1924 * We put a few things here that have to be page-aligned.
1925 * This stuff goes at the beginning of the bss, which is page-aligned.
1926 */
1927 .section ".bss"
1928
1929 .align PAGE_SHIFT
1930
1931 .globl empty_zero_page
1932 empty_zero_page:
1933 .space PAGE_SIZE
1934
1935 .globl swapper_pg_dir
1936 swapper_pg_dir:
1937 .space PAGE_SIZE
1938
1939 /*
1940 * This space gets a copy of optional info passed to us by the bootstrap
1941 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1942 */
1943 .globl cmd_line
1944 cmd_line:
1945 .space COMMAND_LINE_SIZE
Linux kernel - Deliverables
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