arch/powerpc/kernel/head_64.S

   1 /*
   2  *  PowerPC version
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *  Adapted for Power Macintosh by Paul Mackerras.
   8  *  Low-level exception handlers and MMU support
   9  *  rewritten by Paul Mackerras.
  10  *    Copyright (C) 1996 Paul Mackerras.
  11  *
  12  *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
  13  *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
  14  *
  15  *  This file contains the low-level support and setup for the
  16  *  PowerPC-64 platform, including trap and interrupt dispatch.
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  */
  23
  24 #include <linux/threads.h>
  25 #include <asm/reg.h>
  26 #include <asm/page.h>
  27 #include <asm/mmu.h>
  28 #include <asm/ppc_asm.h>
  29 #include <asm/asm-offsets.h>
  30 #include <asm/bug.h>
  31 #include <asm/cputable.h>
  32 #include <asm/setup.h>
  33 #include <asm/hvcall.h>
  34 #include <asm/iseries/lpar_map.h>
  35 #include <asm/thread_info.h>
  36 #include <asm/firmware.h>
  37
  38 #ifdef CONFIG_PPC_ISERIES
  39 #define DO_SOFT_DISABLE
  40 #endif
  41
  42 /*
  43  * We layout physical memory as follows:
  44  * 0x0000 - 0x00ff : Secondary processor spin code
  45  * 0x0100 - 0x2fff : pSeries Interrupt prologs
  46  * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
  47  * 0x6000 - 0x6fff : Initial (CPU0) segment table
  48  * 0x7000 - 0x7fff : FWNMI data area
  49  * 0x8000 -        : Early init and support code
  50  */
  51
  52 /*
  53  *   SPRG Usage
  54  *
  55  *   Register   Definition
  56  *
  57  *   SPRG0      reserved for hypervisor
  58  *   SPRG1      temp - used to save gpr
  59  *   SPRG2      temp - used to save gpr
  60  *   SPRG3      virt addr of paca
  61  */
  62
  63 /*
  64  * Entering into this code we make the following assumptions:
  65  *  For pSeries:
  66  *   1. The MMU is off & open firmware is running in real mode.
  67  *   2. The kernel is entered at __start
  68  *
  69  *  For iSeries:
  70  *   1. The MMU is on (as it always is for iSeries)
  71  *   2. The kernel is entered at system_reset_iSeries
  72  */
  73
  74         .text
  75         .globl  _stext
  76 _stext:
  77 #ifdef CONFIG_PPC_MULTIPLATFORM
  78 _GLOBAL(__start)
  79         /* NOP this out unconditionally */
  80 BEGIN_FTR_SECTION
  81         b       .__start_initialization_multiplatform
  82 END_FTR_SECTION(0, 1)
  83 #endif /* CONFIG_PPC_MULTIPLATFORM */
  84
  85         /* Catch branch to 0 in real mode */
  86         trap
  87
  88         /* Secondary processors spin on this value until it goes to 1. */
  89         .globl  __secondary_hold_spinloop
  90 __secondary_hold_spinloop:
  91         .llong  0x0
  92
  93         /* Secondary processors write this value with their cpu # */
  94         /* after they enter the spin loop immediately below.      */
  95         .globl  __secondary_hold_acknowledge
  96 __secondary_hold_acknowledge:
  97         .llong  0x0
  98
  99 #ifdef CONFIG_PPC_ISERIES
 100         /*
 101          * At offset 0x20, there is a pointer to iSeries LPAR data.
 102          * This is required by the hypervisor
 103          */
 104         . = 0x20
 105         .llong hvReleaseData-KERNELBASE
 106 #endif /* CONFIG_PPC_ISERIES */
 107
 108         . = 0x60
 109 /*
 110  * The following code is used on pSeries to hold secondary processors
 111  * in a spin loop after they have been freed from OpenFirmware, but
 112  * before the bulk of the kernel has been relocated.  This code
 113  * is relocated to physical address 0x60 before prom_init is run.
 114  * All of it must fit below the first exception vector at 0x100.
 115  */
 116 _GLOBAL(__secondary_hold)
 117         mfmsr   r24
 118         ori     r24,r24,MSR_RI
 119         mtmsrd  r24                     /* RI on */
 120
 121         /* Grab our physical cpu number */
 122         mr      r24,r3
 123
 124         /* Tell the master cpu we're here */
 125         /* Relocation is off & we are located at an address less */
 126         /* than 0x100, so only need to grab low order offset.    */
 127         std     r24,__secondary_hold_acknowledge@l(0)
 128         sync
 129
 130         /* All secondary cpus wait here until told to start. */
 131 100:    ld      r4,__secondary_hold_spinloop@l(0)
 132         cmpdi   0,r4,1
 133         bne     100b
 134
 135 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
 136         LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
 137         mtctr   r4
 138         mr      r3,r24
 139         bctr
 140 #else
 141         BUG_OPCODE
 142 #endif
 143
 144 /* This value is used to mark exception frames on the stack. */
 145         .section ".toc","aw"
 146 exception_marker:
 147         .tc     ID_72656773_68657265[TC],0x7265677368657265
 148         .text
 149
 150 /*
 151  * The following macros define the code that appears as
 152  * the prologue to each of the exception handlers.  They
 153  * are split into two parts to allow a single kernel binary
 154  * to be used for pSeries and iSeries.
 155  * LOL.  One day... - paulus
 156  */
 157
 158 /*
 159  * We make as much of the exception code common between native
 160  * exception handlers (including pSeries LPAR) and iSeries LPAR
 161  * implementations as possible.
 162  */
 163
 164 /*
 165  * This is the start of the interrupt handlers for pSeries
 166  * This code runs with relocation off.
 167  */
 168 #define EX_R9           0
 169 #define EX_R10          8
 170 #define EX_R11          16
 171 #define EX_R12          24
 172 #define EX_R13          32
 173 #define EX_SRR0         40
 174 #define EX_DAR          48
 175 #define EX_DSISR        56
 176 #define EX_CCR          60
 177 #define EX_R3           64
 178 #define EX_LR           72
 179
 180 /*
 181  * We're short on space and time in the exception prolog, so we can't
 182  * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
 183  * low halfword of the address, but for Kdump we need the whole low
 184  * word.
 185  */
 186 #ifdef CONFIG_CRASH_DUMP
 187 #define LOAD_HANDLER(reg, label)                                        \
 188         oris    reg,reg,(label)@h;      /* virt addr of handler ... */  \
 189         ori     reg,reg,(label)@l;      /* .. and the rest */
 190 #else
 191 #define LOAD_HANDLER(reg, label)                                        \
 192         ori     reg,reg,(label)@l;      /* virt addr of handler ... */
 193 #endif
 194
 195 /*
 196  * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
 197  * The firmware calls the registered system_reset_fwnmi and
 198  * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
 199  * a 32bit application at the time of the event.
 200  * This firmware bug is present on POWER4 and JS20.
 201  */
 202 #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label)               \
 203         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 204         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 205         std     r10,area+EX_R10(r13);                                   \
 206         std     r11,area+EX_R11(r13);                                   \
 207         std     r12,area+EX_R12(r13);                                   \
 208         mfspr   r9,SPRN_SPRG1;                                          \
 209         std     r9,area+EX_R13(r13);                                    \
 210         mfcr    r9;                                                     \
 211         clrrdi  r12,r13,32;             /* get high part of &label */   \
 212         mfmsr   r10;                                                    \
 213         /* force 64bit mode */                                          \
 214         li      r11,5;                  /* MSR_SF_LG|MSR_ISF_LG */      \
 215         rldimi  r10,r11,61,0;           /* insert into top 3 bits */    \
 216         /* done 64bit mode */                                           \
 217         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
 218         LOAD_HANDLER(r12,label)                                         \
 219         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
 220         mtspr   SPRN_SRR0,r12;                                          \
 221         mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
 222         mtspr   SPRN_SRR1,r10;                                          \
 223         rfid;                                                           \
 224         b       .       /* prevent speculative execution */
 225
 226 #define EXCEPTION_PROLOG_PSERIES(area, label)                           \
 227         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 228         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 229         std     r10,area+EX_R10(r13);                                   \
 230         std     r11,area+EX_R11(r13);                                   \
 231         std     r12,area+EX_R12(r13);                                   \
 232         mfspr   r9,SPRN_SPRG1;                                          \
 233         std     r9,area+EX_R13(r13);                                    \
 234         mfcr    r9;                                                     \
 235         clrrdi  r12,r13,32;             /* get high part of &label */   \
 236         mfmsr   r10;                                                    \
 237         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
 238         LOAD_HANDLER(r12,label)                                         \
 239         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
 240         mtspr   SPRN_SRR0,r12;                                          \
 241         mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
 242         mtspr   SPRN_SRR1,r10;                                          \
 243         rfid;                                                           \
 244         b       .       /* prevent speculative execution */
 245
 246 /*
 247  * This is the start of the interrupt handlers for iSeries
 248  * This code runs with relocation on.
 249  */
 250 #define EXCEPTION_PROLOG_ISERIES_1(area)                                \
 251         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 252         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 253         std     r10,area+EX_R10(r13);                                   \
 254         std     r11,area+EX_R11(r13);                                   \
 255         std     r12,area+EX_R12(r13);                                   \
 256         mfspr   r9,SPRN_SPRG1;                                          \
 257         std     r9,area+EX_R13(r13);                                    \
 258         mfcr    r9
 259
 260 #define EXCEPTION_PROLOG_ISERIES_2                                      \
 261         mfmsr   r10;                                                    \
 262         ld      r12,PACALPPACAPTR(r13);                                 \
 263         ld      r11,LPPACASRR0(r12);                                    \
 264         ld      r12,LPPACASRR1(r12);                                    \
 265         ori     r10,r10,MSR_RI;                                         \
 266         mtmsrd  r10,1
 267
 268 /*
 269  * The common exception prolog is used for all except a few exceptions
 270  * such as a segment miss on a kernel address.  We have to be prepared
 271  * to take another exception from the point where we first touch the
 272  * kernel stack onwards.
 273  *
 274  * On entry r13 points to the paca, r9-r13 are saved in the paca,
 275  * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
 276  * SRR1, and relocation is on.
 277  */
 278 #define EXCEPTION_PROLOG_COMMON(n, area)                                   \
 279         andi.   r10,r12,MSR_PR;         /* See if coming from user      */ \
 280         mr      r10,r1;                 /* Save r1                      */ \
 281         subi    r1,r1,INT_FRAME_SIZE;   /* alloc frame on kernel stack  */ \
 282         beq-    1f;                                                        \
 283         ld      r1,PACAKSAVE(r13);      /* kernel stack to use          */ \
 284 1:      cmpdi   cr1,r1,0;               /* check if r1 is in userspace  */ \
 285         bge-    cr1,bad_stack;          /* abort if it is               */ \
 286         std     r9,_CCR(r1);            /* save CR in stackframe        */ \
 287         std     r11,_NIP(r1);           /* save SRR0 in stackframe      */ \
 288         std     r12,_MSR(r1);           /* save SRR1 in stackframe      */ \
 289         std     r10,0(r1);              /* make stack chain pointer     */ \
 290         std     r0,GPR0(r1);            /* save r0 in stackframe        */ \
 291         std     r10,GPR1(r1);           /* save r1 in stackframe        */ \
 292         ACCOUNT_CPU_USER_ENTRY(r9, r10);                                   \
 293         std     r2,GPR2(r1);            /* save r2 in stackframe        */ \
 294         SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe   */ \
 295         SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe    */ \
 296         ld      r9,area+EX_R9(r13);     /* move r9, r10 to stackframe   */ \
 297         ld      r10,area+EX_R10(r13);                                      \
 298         std     r9,GPR9(r1);                                               \
 299         std     r10,GPR10(r1);                                             \
 300         ld      r9,area+EX_R11(r13);    /* move r11 - r13 to stackframe */ \
 301         ld      r10,area+EX_R12(r13);                                      \
 302         ld      r11,area+EX_R13(r13);                                      \
 303         std     r9,GPR11(r1);                                              \
 304         std     r10,GPR12(r1);                                             \
 305         std     r11,GPR13(r1);                                             \
 306         ld      r2,PACATOC(r13);        /* get kernel TOC into r2       */ \
 307         mflr    r9;                     /* save LR in stackframe        */ \
 308         std     r9,_LINK(r1);                                              \
 309         mfctr   r10;                    /* save CTR in stackframe       */ \
 310         std     r10,_CTR(r1);                                              \
 311         mfspr   r11,SPRN_XER;           /* save XER in stackframe       */ \
 312         std     r11,_XER(r1);                                              \
 313         li      r9,(n)+1;                                                  \
 314         std     r9,_TRAP(r1);           /* set trap number              */ \
 315         li      r10,0;                                                     \
 316         ld      r11,exception_marker@toc(r2);                              \
 317         std     r10,RESULT(r1);         /* clear regs->result           */ \
 318         std     r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame      */
 319
 320 /*
 321  * Exception vectors.
 322  */
 323 #define STD_EXCEPTION_PSERIES(n, label)                 \
 324         . = n;                                          \
 325         .globl label##_pSeries;                         \
 326 label##_pSeries:                                        \
 327         HMT_MEDIUM;                                     \
 328         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 329         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 330
 331 #define HSTD_EXCEPTION_PSERIES(n, label)                \
 332         . = n;                                          \
 333         .globl label##_pSeries;                         \
 334 label##_pSeries:                                        \
 335         HMT_MEDIUM;                                     \
 336         mtspr   SPRN_SPRG1,r20;         /* save r20 */  \
 337         mfspr   r20,SPRN_HSRR0;         /* copy HSRR0 to SRR0 */ \
 338         mtspr   SPRN_SRR0,r20;                          \
 339         mfspr   r20,SPRN_HSRR1;         /* copy HSRR0 to SRR0 */ \
 340         mtspr   SPRN_SRR1,r20;                          \
 341         mfspr   r20,SPRN_SPRG1;         /* restore r20 */ \
 342         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 343         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 344
 345
 346 #define STD_EXCEPTION_ISERIES(n, label, area)           \
 347         .globl label##_iSeries;                         \
 348 label##_iSeries:                                        \
 349         HMT_MEDIUM;                                     \
 350         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 351         EXCEPTION_PROLOG_ISERIES_1(area);               \
 352         EXCEPTION_PROLOG_ISERIES_2;                     \
 353         b       label##_common
 354
 355 #define MASKABLE_EXCEPTION_ISERIES(n, label)                            \
 356         .globl label##_iSeries;                                         \
 357 label##_iSeries:                                                        \
 358         HMT_MEDIUM;                                                     \
 359         mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
 360         EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN);                         \
 361         lbz     r10,PACAPROCENABLED(r13);                               \
 362         cmpwi   0,r10,0;                                                \
 363         beq-    label##_iSeries_masked;                                 \
 364         EXCEPTION_PROLOG_ISERIES_2;                                     \
 365         b       label##_common;                                         \
 366
 367 #ifdef DO_SOFT_DISABLE
 368 #define DISABLE_INTS                            \
 369 BEGIN_FW_FTR_SECTION;                           \
 370         lbz     r10,PACAPROCENABLED(r13);       \
 371         li      r11,0;                          \
 372         std     r10,SOFTE(r1);                  \
 373         mfmsr   r10;                            \
 374         stb     r11,PACAPROCENABLED(r13);       \
 375         ori     r10,r10,MSR_EE;                 \
 376         mtmsrd  r10,1;                          \
 377 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 378
 379 #define ENABLE_INTS                             \
 380 BEGIN_FW_FTR_SECTION;                           \
 381         lbz     r10,PACAPROCENABLED(r13);       \
 382         mfmsr   r11;                            \
 383         std     r10,SOFTE(r1);                  \
 384         ori     r11,r11,MSR_EE;                 \
 385 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES);   \
 386 BEGIN_FW_FTR_SECTION;                           \
 387         ld      r12,_MSR(r1);                   \
 388         mfmsr   r11;                            \
 389         rlwimi  r11,r12,0,MSR_EE;               \
 390 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES);   \
 391         mtmsrd  r11,1
 392
 393 #else   /* hard enable/disable interrupts */
 394 #define DISABLE_INTS
 395
 396 #define ENABLE_INTS                             \
 397         ld      r12,_MSR(r1);                   \
 398         mfmsr   r11;                            \
 399         rlwimi  r11,r12,0,MSR_EE;               \
 400         mtmsrd  r11,1
 401
 402 #endif
 403
 404 #define STD_EXCEPTION_COMMON(trap, label, hdlr)         \
 405         .align  7;                                      \
 406         .globl label##_common;                          \
 407 label##_common:                                         \
 408         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 409         DISABLE_INTS;                                   \
 410         bl      .save_nvgprs;                           \
 411         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 412         bl      hdlr;                                   \
 413         b       .ret_from_except
 414
 415 /*
 416  * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
 417  * in the idle task and therefore need the special idle handling.
 418  */
 419 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr)    \
 420         .align  7;                                      \
 421         .globl label##_common;                          \
 422 label##_common:                                         \
 423         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 424         FINISH_NAP;                                     \
 425         DISABLE_INTS;                                   \
 426         bl      .save_nvgprs;                           \
 427         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 428         bl      hdlr;                                   \
 429         b       .ret_from_except
 430
 431 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr)    \
 432         .align  7;                                      \
 433         .globl label##_common;                          \
 434 label##_common:                                         \
 435         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 436         FINISH_NAP;                                     \
 437         DISABLE_INTS;                                   \
 438         bl      .ppc64_runlatch_on;                     \
 439         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 440         bl      hdlr;                                   \
 441         b       .ret_from_except_lite
 442
 443 /*
 444  * When the idle code in power4_idle puts the CPU into NAP mode,
 445  * it has to do so in a loop, and relies on the external interrupt
 446  * and decrementer interrupt entry code to get it out of the loop.
 447  * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
 448  * to signal that it is in the loop and needs help to get out.
 449  */
 450 #ifdef CONFIG_PPC_970_NAP
 451 #define FINISH_NAP                              \
 452 BEGIN_FTR_SECTION                               \
 453         clrrdi  r11,r1,THREAD_SHIFT;            \
 454         ld      r9,TI_LOCAL_FLAGS(r11);         \
 455         andi.   r10,r9,_TLF_NAPPING;            \
 456         bnel    power4_fixup_nap;               \
 457 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
 458 #else
 459 #define FINISH_NAP
 460 #endif
 461
 462 /*
 463  * Start of pSeries system interrupt routines
 464  */
 465         . = 0x100
 466         .globl __start_interrupts
 467 __start_interrupts:
 468
 469         STD_EXCEPTION_PSERIES(0x100, system_reset)
 470
 471         . = 0x200
 472 _machine_check_pSeries:
 473         HMT_MEDIUM
 474         mtspr   SPRN_SPRG1,r13          /* save r13 */
 475         EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
 476
 477         . = 0x300
 478         .globl data_access_pSeries
 479 data_access_pSeries:
 480         HMT_MEDIUM
 481         mtspr   SPRN_SPRG1,r13
 482 BEGIN_FTR_SECTION
 483         mtspr   SPRN_SPRG2,r12
 484         mfspr   r13,SPRN_DAR
 485         mfspr   r12,SPRN_DSISR
 486         srdi    r13,r13,60
 487         rlwimi  r13,r12,16,0x20
 488         mfcr    r12
 489         cmpwi   r13,0x2c
 490         beq     do_stab_bolted_pSeries
 491         mtcrf   0x80,r12
 492         mfspr   r12,SPRN_SPRG2
 493 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
 494         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
 495
 496         . = 0x380
 497         .globl data_access_slb_pSeries
 498 data_access_slb_pSeries:
 499         HMT_MEDIUM
 500         mtspr   SPRN_SPRG1,r13
 501         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 502         std     r3,PACA_EXSLB+EX_R3(r13)
 503         mfspr   r3,SPRN_DAR
 504         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
 505         mfcr    r9
 506 #ifdef __DISABLED__
 507         /* Keep that around for when we re-implement dynamic VSIDs */
 508         cmpdi   r3,0
 509         bge     slb_miss_user_pseries
 510 #endif /* __DISABLED__ */
 511         std     r10,PACA_EXSLB+EX_R10(r13)
 512         std     r11,PACA_EXSLB+EX_R11(r13)
 513         std     r12,PACA_EXSLB+EX_R12(r13)
 514         mfspr   r10,SPRN_SPRG1
 515         std     r10,PACA_EXSLB+EX_R13(r13)
 516         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 517         b       .slb_miss_realmode      /* Rel. branch works in real mode */
 518
 519         STD_EXCEPTION_PSERIES(0x400, instruction_access)
 520
 521         . = 0x480
 522         .globl instruction_access_slb_pSeries
 523 instruction_access_slb_pSeries:
 524         HMT_MEDIUM
 525         mtspr   SPRN_SPRG1,r13
 526         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 527         std     r3,PACA_EXSLB+EX_R3(r13)
 528         mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
 529         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
 530         mfcr    r9
 531 #ifdef __DISABLED__
 532         /* Keep that around for when we re-implement dynamic VSIDs */
 533         cmpdi   r3,0
 534         bge     slb_miss_user_pseries
 535 #endif /* __DISABLED__ */
 536         std     r10,PACA_EXSLB+EX_R10(r13)
 537         std     r11,PACA_EXSLB+EX_R11(r13)
 538         std     r12,PACA_EXSLB+EX_R12(r13)
 539         mfspr   r10,SPRN_SPRG1
 540         std     r10,PACA_EXSLB+EX_R13(r13)
 541         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 542         b       .slb_miss_realmode      /* Rel. branch works in real mode */
 543
 544         STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
 545         STD_EXCEPTION_PSERIES(0x600, alignment)
 546         STD_EXCEPTION_PSERIES(0x700, program_check)
 547         STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
 548         STD_EXCEPTION_PSERIES(0x900, decrementer)
 549         STD_EXCEPTION_PSERIES(0xa00, trap_0a)
 550         STD_EXCEPTION_PSERIES(0xb00, trap_0b)
 551
 552         . = 0xc00
 553         .globl  system_call_pSeries
 554 system_call_pSeries:
 555         HMT_MEDIUM
 556         mr      r9,r13
 557         mfmsr   r10
 558         mfspr   r13,SPRN_SPRG3
 559         mfspr   r11,SPRN_SRR0
 560         clrrdi  r12,r13,32
 561         oris    r12,r12,system_call_common@h
 562         ori     r12,r12,system_call_common@l
 563         mtspr   SPRN_SRR0,r12
 564         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
 565         mfspr   r12,SPRN_SRR1
 566         mtspr   SPRN_SRR1,r10
 567         rfid
 568         b       .       /* prevent speculative execution */
 569
 570         STD_EXCEPTION_PSERIES(0xd00, single_step)
 571         STD_EXCEPTION_PSERIES(0xe00, trap_0e)
 572
 573         /* We need to deal with the Altivec unavailable exception
 574          * here which is at 0xf20, thus in the middle of the
 575          * prolog code of the PerformanceMonitor one. A little
 576          * trickery is thus necessary
 577          */
 578         . = 0xf00
 579         b       performance_monitor_pSeries
 580
 581         STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
 582
 583 #ifdef CONFIG_CBE_RAS
 584         HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
 585 #endif /* CONFIG_CBE_RAS */
 586         STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
 587 #ifdef CONFIG_CBE_RAS
 588         HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
 589 #endif /* CONFIG_CBE_RAS */
 590         STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
 591 #ifdef CONFIG_CBE_RAS
 592         HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
 593 #endif /* CONFIG_CBE_RAS */
 594
 595         . = 0x3000
 596
 597 /*** pSeries interrupt support ***/
 598
 599         /* moved from 0xf00 */
 600         STD_EXCEPTION_PSERIES(., performance_monitor)
 601
 602         .align  7
 603 do_stab_bolted_pSeries:
 604         mtcrf   0x80,r12
 605         mfspr   r12,SPRN_SPRG2
 606         EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
 607
 608 /*
 609  * We have some room here  we use that to put
 610  * the peries slb miss user trampoline code so it's reasonably
 611  * away from slb_miss_user_common to avoid problems with rfid
 612  *
 613  * This is used for when the SLB miss handler has to go virtual,
 614  * which doesn't happen for now anymore but will once we re-implement
 615  * dynamic VSIDs for shared page tables
 616  */
 617 #ifdef __DISABLED__
 618 slb_miss_user_pseries:
 619         std     r10,PACA_EXGEN+EX_R10(r13)
 620         std     r11,PACA_EXGEN+EX_R11(r13)
 621         std     r12,PACA_EXGEN+EX_R12(r13)
 622         mfspr   r10,SPRG1
 623         ld      r11,PACA_EXSLB+EX_R9(r13)
 624         ld      r12,PACA_EXSLB+EX_R3(r13)
 625         std     r10,PACA_EXGEN+EX_R13(r13)
 626         std     r11,PACA_EXGEN+EX_R9(r13)
 627         std     r12,PACA_EXGEN+EX_R3(r13)
 628         clrrdi  r12,r13,32
 629         mfmsr   r10
 630         mfspr   r11,SRR0                        /* save SRR0 */
 631         ori     r12,r12,slb_miss_user_common@l  /* virt addr of handler */
 632         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
 633         mtspr   SRR0,r12
 634         mfspr   r12,SRR1                        /* and SRR1 */
 635         mtspr   SRR1,r10
 636         rfid
 637         b       .                               /* prevent spec. execution */
 638 #endif /* __DISABLED__ */
 639
 640 /*
 641  * Vectors for the FWNMI option.  Share common code.
 642  */
 643         .globl system_reset_fwnmi
 644       .align 7
 645 system_reset_fwnmi:
 646         HMT_MEDIUM
 647         mtspr   SPRN_SPRG1,r13          /* save r13 */
 648         EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
 649
 650         .globl machine_check_fwnmi
 651       .align 7
 652 machine_check_fwnmi:
 653         HMT_MEDIUM
 654         mtspr   SPRN_SPRG1,r13          /* save r13 */
 655         EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
 656
 657 #ifdef CONFIG_PPC_ISERIES
 658 /***  ISeries-LPAR interrupt handlers ***/
 659
 660         STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
 661
 662         .globl data_access_iSeries
 663 data_access_iSeries:
 664         mtspr   SPRN_SPRG1,r13
 665 BEGIN_FTR_SECTION
 666         mtspr   SPRN_SPRG2,r12
 667         mfspr   r13,SPRN_DAR
 668         mfspr   r12,SPRN_DSISR
 669         srdi    r13,r13,60
 670         rlwimi  r13,r12,16,0x20
 671         mfcr    r12
 672         cmpwi   r13,0x2c
 673         beq     .do_stab_bolted_iSeries
 674         mtcrf   0x80,r12
 675         mfspr   r12,SPRN_SPRG2
 676 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
 677         EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
 678         EXCEPTION_PROLOG_ISERIES_2
 679         b       data_access_common
 680
 681 .do_stab_bolted_iSeries:
 682         mtcrf   0x80,r12
 683         mfspr   r12,SPRN_SPRG2
 684         EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
 685         EXCEPTION_PROLOG_ISERIES_2
 686         b       .do_stab_bolted
 687
 688         .globl  data_access_slb_iSeries
 689 data_access_slb_iSeries:
 690         mtspr   SPRN_SPRG1,r13          /* save r13 */
 691         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 692         std     r3,PACA_EXSLB+EX_R3(r13)
 693         mfspr   r3,SPRN_DAR
 694         std     r9,PACA_EXSLB+EX_R9(r13)
 695         mfcr    r9
 696 #ifdef __DISABLED__
 697         cmpdi   r3,0
 698         bge     slb_miss_user_iseries
 699 #endif
 700         std     r10,PACA_EXSLB+EX_R10(r13)
 701         std     r11,PACA_EXSLB+EX_R11(r13)
 702         std     r12,PACA_EXSLB+EX_R12(r13)
 703         mfspr   r10,SPRN_SPRG1
 704         std     r10,PACA_EXSLB+EX_R13(r13)
 705         ld      r12,PACALPPACAPTR(r13)
 706         ld      r12,LPPACASRR1(r12)
 707         b       .slb_miss_realmode
 708
 709         STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
 710
 711         .globl  instruction_access_slb_iSeries
 712 instruction_access_slb_iSeries:
 713         mtspr   SPRN_SPRG1,r13          /* save r13 */
 714         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 715         std     r3,PACA_EXSLB+EX_R3(r13)
 716         ld      r3,PACALPPACAPTR(r13)
 717         ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
 718         std     r9,PACA_EXSLB+EX_R9(r13)
 719         mfcr    r9
 720 #ifdef __DISABLED__
 721         cmpdi   r3,0
 722         bge     .slb_miss_user_iseries
 723 #endif
 724         std     r10,PACA_EXSLB+EX_R10(r13)
 725         std     r11,PACA_EXSLB+EX_R11(r13)
 726         std     r12,PACA_EXSLB+EX_R12(r13)
 727         mfspr   r10,SPRN_SPRG1
 728         std     r10,PACA_EXSLB+EX_R13(r13)
 729         ld      r12,PACALPPACAPTR(r13)
 730         ld      r12,LPPACASRR1(r12)
 731         b       .slb_miss_realmode
 732
 733 #ifdef __DISABLED__
 734 slb_miss_user_iseries:
 735         std     r10,PACA_EXGEN+EX_R10(r13)
 736         std     r11,PACA_EXGEN+EX_R11(r13)
 737         std     r12,PACA_EXGEN+EX_R12(r13)
 738         mfspr   r10,SPRG1
 739         ld      r11,PACA_EXSLB+EX_R9(r13)
 740         ld      r12,PACA_EXSLB+EX_R3(r13)
 741         std     r10,PACA_EXGEN+EX_R13(r13)
 742         std     r11,PACA_EXGEN+EX_R9(r13)
 743         std     r12,PACA_EXGEN+EX_R3(r13)
 744         EXCEPTION_PROLOG_ISERIES_2
 745         b       slb_miss_user_common
 746 #endif
 747
 748         MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
 749         STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
 750         STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
 751         STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
 752         MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
 753         STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
 754         STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
 755
 756         .globl  system_call_iSeries
 757 system_call_iSeries:
 758         mr      r9,r13
 759         mfspr   r13,SPRN_SPRG3
 760         EXCEPTION_PROLOG_ISERIES_2
 761         b       system_call_common
 762
 763         STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
 764         STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
 765         STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
 766
 767         .globl system_reset_iSeries
 768 system_reset_iSeries:
 769         mfspr   r13,SPRN_SPRG3          /* Get paca address */
 770         mfmsr   r24
 771         ori     r24,r24,MSR_RI
 772         mtmsrd  r24                     /* RI on */
 773         lhz     r24,PACAPACAINDEX(r13)  /* Get processor # */
 774         cmpwi   0,r24,0                 /* Are we processor 0? */
 775         beq     .__start_initialization_iSeries /* Start up the first processor */
 776         mfspr   r4,SPRN_CTRLF
 777         li      r5,CTRL_RUNLATCH        /* Turn off the run light */
 778         andc    r4,r4,r5
 779         mtspr   SPRN_CTRLT,r4
 780
 781 1:
 782         HMT_LOW
 783 #ifdef CONFIG_SMP
 784         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor
 785                                          * should start */
 786         sync
 787         LOAD_REG_IMMEDIATE(r3,current_set)
 788         sldi    r28,r24,3               /* get current_set[cpu#] */
 789         ldx     r3,r3,r28
 790         addi    r1,r3,THREAD_SIZE
 791         subi    r1,r1,STACK_FRAME_OVERHEAD
 792
 793         cmpwi   0,r23,0
 794         beq     iSeries_secondary_smp_loop      /* Loop until told to go */
 795         bne     .__secondary_start              /* Loop until told to go */
 796 iSeries_secondary_smp_loop:
 797         /* Let the Hypervisor know we are alive */
 798         /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
 799         lis     r3,0x8002
 800         rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
 801 #else /* CONFIG_SMP */
 802         /* Yield the processor.  This is required for non-SMP kernels
 803                 which are running on multi-threaded machines. */
 804         lis     r3,0x8000
 805         rldicr  r3,r3,32,15             /* r3 = (r3 << 32) & 0xffff000000000000 */
 806         addi    r3,r3,18                /* r3 = 0x8000000000000012 which is "yield" */
 807         li      r4,0                    /* "yield timed" */
 808         li      r5,-1                   /* "yield forever" */
 809 #endif /* CONFIG_SMP */
 810         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
 811         sc                              /* Invoke the hypervisor via a system call */
 812         mfspr   r13,SPRN_SPRG3          /* Put r13 back ???? */
 813         b       1b                      /* If SMP not configured, secondaries
 814                                          * loop forever */
 815
 816         .globl decrementer_iSeries_masked
 817 decrementer_iSeries_masked:
 818         /* We may not have a valid TOC pointer in here. */
 819         li      r11,1
 820         ld      r12,PACALPPACAPTR(r13)
 821         stb     r11,LPPACADECRINT(r12)
 822         LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
 823         lwz     r12,0(r12)
 824         mtspr   SPRN_DEC,r12
 825         /* fall through */
 826
 827         .globl hardware_interrupt_iSeries_masked
 828 hardware_interrupt_iSeries_masked:
 829         mtcrf   0x80,r9         /* Restore regs */
 830         ld      r12,PACALPPACAPTR(r13)
 831         ld      r11,LPPACASRR0(r12)
 832         ld      r12,LPPACASRR1(r12)
 833         mtspr   SPRN_SRR0,r11
 834         mtspr   SPRN_SRR1,r12
 835         ld      r9,PACA_EXGEN+EX_R9(r13)
 836         ld      r10,PACA_EXGEN+EX_R10(r13)
 837         ld      r11,PACA_EXGEN+EX_R11(r13)
 838         ld      r12,PACA_EXGEN+EX_R12(r13)
 839         ld      r13,PACA_EXGEN+EX_R13(r13)
 840         rfid
 841         b       .       /* prevent speculative execution */
 842 #endif /* CONFIG_PPC_ISERIES */
 843
 844 /*** Common interrupt handlers ***/
 845
 846         STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
 847
 848         /*
 849          * Machine check is different because we use a different
 850          * save area: PACA_EXMC instead of PACA_EXGEN.
 851          */
 852         .align  7
 853         .globl machine_check_common
 854 machine_check_common:
 855         EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
 856         FINISH_NAP
 857         DISABLE_INTS
 858         bl      .save_nvgprs
 859         addi    r3,r1,STACK_FRAME_OVERHEAD
 860         bl      .machine_check_exception
 861         b       .ret_from_except
 862
 863         STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
 864         STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
 865         STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
 866         STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
 867         STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
 868         STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
 869         STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
 870 #ifdef CONFIG_ALTIVEC
 871         STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
 872 #else
 873         STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
 874 #endif
 875 #ifdef CONFIG_CBE_RAS
 876         STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
 877         STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
 878         STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
 879 #endif /* CONFIG_CBE_RAS */
 880
 881 /*
 882  * Here we have detected that the kernel stack pointer is bad.
 883  * R9 contains the saved CR, r13 points to the paca,
 884  * r10 contains the (bad) kernel stack pointer,
 885  * r11 and r12 contain the saved SRR0 and SRR1.
 886  * We switch to using an emergency stack, save the registers there,
 887  * and call kernel_bad_stack(), which panics.
 888  */
 889 bad_stack:
 890         ld      r1,PACAEMERGSP(r13)
 891         subi    r1,r1,64+INT_FRAME_SIZE
 892         std     r9,_CCR(r1)
 893         std     r10,GPR1(r1)
 894         std     r11,_NIP(r1)
 895         std     r12,_MSR(r1)
 896         mfspr   r11,SPRN_DAR
 897         mfspr   r12,SPRN_DSISR
 898         std     r11,_DAR(r1)
 899         std     r12,_DSISR(r1)
 900         mflr    r10
 901         mfctr   r11
 902         mfxer   r12
 903         std     r10,_LINK(r1)
 904         std     r11,_CTR(r1)
 905         std     r12,_XER(r1)
 906         SAVE_GPR(0,r1)
 907         SAVE_GPR(2,r1)
 908         SAVE_4GPRS(3,r1)
 909         SAVE_2GPRS(7,r1)
 910         SAVE_10GPRS(12,r1)
 911         SAVE_10GPRS(22,r1)
 912         addi    r11,r1,INT_FRAME_SIZE
 913         std     r11,0(r1)
 914         li      r12,0
 915         std     r12,0(r11)
 916         ld      r2,PACATOC(r13)
 917 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 918         bl      .kernel_bad_stack
 919         b       1b
 920
 921 /*
 922  * Return from an exception with minimal checks.
 923  * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
 924  * If interrupts have been enabled, or anything has been
 925  * done that might have changed the scheduling status of
 926  * any task or sent any task a signal, you should use
 927  * ret_from_except or ret_from_except_lite instead of this.
 928  */
 929         .globl  fast_exception_return
 930 fast_exception_return:
 931         ld      r12,_MSR(r1)
 932         ld      r11,_NIP(r1)
 933         andi.   r3,r12,MSR_RI           /* check if RI is set */
 934         beq-    unrecov_fer
 935
 936 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 937         andi.   r3,r12,MSR_PR
 938         beq     2f
 939         ACCOUNT_CPU_USER_EXIT(r3, r4)
 940 2:
 941 #endif
 942
 943         ld      r3,_CCR(r1)
 944         ld      r4,_LINK(r1)
 945         ld      r5,_CTR(r1)
 946         ld      r6,_XER(r1)
 947         mtcr    r3
 948         mtlr    r4
 949         mtctr   r5
 950         mtxer   r6
 951         REST_GPR(0, r1)
 952         REST_8GPRS(2, r1)
 953
 954         mfmsr   r10
 955         clrrdi  r10,r10,2               /* clear RI (LE is 0 already) */
 956         mtmsrd  r10,1
 957
 958         mtspr   SPRN_SRR1,r12
 959         mtspr   SPRN_SRR0,r11
 960         REST_4GPRS(10, r1)
 961         ld      r1,GPR1(r1)
 962         rfid
 963         b       .       /* prevent speculative execution */
 964
 965 unrecov_fer:
 966         bl      .save_nvgprs
 967 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 968         bl      .unrecoverable_exception
 969         b       1b
 970
 971 /*
 972  * Here r13 points to the paca, r9 contains the saved CR,
 973  * SRR0 and SRR1 are saved in r11 and r12,
 974  * r9 - r13 are saved in paca->exgen.
 975  */
 976         .align  7
 977         .globl data_access_common
 978 data_access_common:
 979         mfspr   r10,SPRN_DAR
 980         std     r10,PACA_EXGEN+EX_DAR(r13)
 981         mfspr   r10,SPRN_DSISR
 982         stw     r10,PACA_EXGEN+EX_DSISR(r13)
 983         EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
 984         ld      r3,PACA_EXGEN+EX_DAR(r13)
 985         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
 986         li      r5,0x300
 987         b       .do_hash_page           /* Try to handle as hpte fault */
 988
 989         .align  7
 990         .globl instruction_access_common
 991 instruction_access_common:
 992         EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
 993         ld      r3,_NIP(r1)
 994         andis.  r4,r12,0x5820
 995         li      r5,0x400
 996         b       .do_hash_page           /* Try to handle as hpte fault */
 997
 998 /*
 999  * Here is the common SLB miss user that is used when going to virtual
1000  * mode for SLB misses, that is currently not used
1001  */
1002 #ifdef __DISABLED__
1003         .align  7
1004         .globl  slb_miss_user_common
1005 slb_miss_user_common:
1006         mflr    r10
1007         std     r3,PACA_EXGEN+EX_DAR(r13)
1008         stw     r9,PACA_EXGEN+EX_CCR(r13)
1009         std     r10,PACA_EXGEN+EX_LR(r13)
1010         std     r11,PACA_EXGEN+EX_SRR0(r13)
1011         bl      .slb_allocate_user
1012
1013         ld      r10,PACA_EXGEN+EX_LR(r13)
1014         ld      r3,PACA_EXGEN+EX_R3(r13)
1015         lwz     r9,PACA_EXGEN+EX_CCR(r13)
1016         ld      r11,PACA_EXGEN+EX_SRR0(r13)
1017         mtlr    r10
1018         beq-    slb_miss_fault
1019
1020         andi.   r10,r12,MSR_RI          /* check for unrecoverable exception */
1021         beq-    unrecov_user_slb
1022         mfmsr   r10
1023
1024 .machine push
1025 .machine "power4"
1026         mtcrf   0x80,r9
1027 .machine pop
1028
1029         clrrdi  r10,r10,2               /* clear RI before setting SRR0/1 */
1030         mtmsrd  r10,1
1031
1032         mtspr   SRR0,r11
1033         mtspr   SRR1,r12
1034
1035         ld      r9,PACA_EXGEN+EX_R9(r13)
1036         ld      r10,PACA_EXGEN+EX_R10(r13)
1037         ld      r11,PACA_EXGEN+EX_R11(r13)
1038         ld      r12,PACA_EXGEN+EX_R12(r13)
1039         ld      r13,PACA_EXGEN+EX_R13(r13)
1040         rfid
1041         b       .
1042
1043 slb_miss_fault:
1044         EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1045         ld      r4,PACA_EXGEN+EX_DAR(r13)
1046         li      r5,0
1047         std     r4,_DAR(r1)
1048         std     r5,_DSISR(r1)
1049         b       handle_page_fault
1050
1051 unrecov_user_slb:
1052         EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1053         DISABLE_INTS
1054         bl      .save_nvgprs
1055 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1056         bl      .unrecoverable_exception
1057         b       1b
1058
1059 #endif /* __DISABLED__ */
1060
1061
1062 /*
1063  * r13 points to the PACA, r9 contains the saved CR,
1064  * r12 contain the saved SRR1, SRR0 is still ready for return
1065  * r3 has the faulting address
1066  * r9 - r13 are saved in paca->exslb.
1067  * r3 is saved in paca->slb_r3
1068  * We assume we aren't going to take any exceptions during this procedure.
1069  */
1070 _GLOBAL(slb_miss_realmode)
1071         mflr    r10
1072
1073         stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
1074         std     r10,PACA_EXSLB+EX_LR(r13)       /* save LR */
1075
1076         bl      .slb_allocate_realmode
1077
1078         /* All done -- return from exception. */
1079
1080         ld      r10,PACA_EXSLB+EX_LR(r13)
1081         ld      r3,PACA_EXSLB+EX_R3(r13)
1082         lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
1083 #ifdef CONFIG_PPC_ISERIES
1084 BEGIN_FW_FTR_SECTION
1085         ld      r11,PACALPPACAPTR(r13)
1086         ld      r11,LPPACASRR0(r11)             /* get SRR0 value */
1087 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1088 #endif /* CONFIG_PPC_ISERIES */
1089
1090         mtlr    r10
1091
1092         andi.   r10,r12,MSR_RI  /* check for unrecoverable exception */
1093         beq-    unrecov_slb
1094
1095 .machine        push
1096 .machine        "power4"
1097         mtcrf   0x80,r9
1098         mtcrf   0x01,r9         /* slb_allocate uses cr0 and cr7 */
1099 .machine        pop
1100
1101 #ifdef CONFIG_PPC_ISERIES
1102 BEGIN_FW_FTR_SECTION
1103         mtspr   SPRN_SRR0,r11
1104         mtspr   SPRN_SRR1,r12
1105 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1106 #endif /* CONFIG_PPC_ISERIES */
1107         ld      r9,PACA_EXSLB+EX_R9(r13)
1108         ld      r10,PACA_EXSLB+EX_R10(r13)
1109         ld      r11,PACA_EXSLB+EX_R11(r13)
1110         ld      r12,PACA_EXSLB+EX_R12(r13)
1111         ld      r13,PACA_EXSLB+EX_R13(r13)
1112         rfid
1113         b       .       /* prevent speculative execution */
1114
1115 unrecov_slb:
1116         EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1117         DISABLE_INTS
1118         bl      .save_nvgprs
1119 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1120         bl      .unrecoverable_exception
1121         b       1b
1122
1123         .align  7
1124         .globl hardware_interrupt_common
1125         .globl hardware_interrupt_entry
1126 hardware_interrupt_common:
1127         EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1128         FINISH_NAP
1129 hardware_interrupt_entry:
1130         DISABLE_INTS
1131         bl      .ppc64_runlatch_on
1132         addi    r3,r1,STACK_FRAME_OVERHEAD
1133         bl      .do_IRQ
1134         b       .ret_from_except_lite
1135
1136 #ifdef CONFIG_PPC_970_NAP
1137 power4_fixup_nap:
1138         andc    r9,r9,r10
1139         std     r9,TI_LOCAL_FLAGS(r11)
1140         ld      r10,_LINK(r1)           /* make idle task do the */
1141         std     r10,_NIP(r1)            /* equivalent of a blr */
1142         blr
1143 #endif
1144
1145         .align  7
1146         .globl alignment_common
1147 alignment_common:
1148         mfspr   r10,SPRN_DAR
1149         std     r10,PACA_EXGEN+EX_DAR(r13)
1150         mfspr   r10,SPRN_DSISR
1151         stw     r10,PACA_EXGEN+EX_DSISR(r13)
1152         EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1153         ld      r3,PACA_EXGEN+EX_DAR(r13)
1154         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
1155         std     r3,_DAR(r1)
1156         std     r4,_DSISR(r1)
1157         bl      .save_nvgprs
1158         addi    r3,r1,STACK_FRAME_OVERHEAD
1159         ENABLE_INTS
1160         bl      .alignment_exception
1161         b       .ret_from_except
1162
1163         .align  7
1164         .globl program_check_common
1165 program_check_common:
1166         EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1167         bl      .save_nvgprs
1168         addi    r3,r1,STACK_FRAME_OVERHEAD
1169         ENABLE_INTS
1170         bl      .program_check_exception
1171         b       .ret_from_except
1172
1173         .align  7
1174         .globl fp_unavailable_common
1175 fp_unavailable_common:
1176         EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1177         bne     1f                      /* if from user, just load it up */
1178         bl      .save_nvgprs
1179         addi    r3,r1,STACK_FRAME_OVERHEAD
1180         ENABLE_INTS
1181         bl      .kernel_fp_unavailable_exception
1182         BUG_OPCODE
1183 1:      b       .load_up_fpu
1184
1185         .align  7
1186         .globl altivec_unavailable_common
1187 altivec_unavailable_common:
1188         EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1189 #ifdef CONFIG_ALTIVEC
1190 BEGIN_FTR_SECTION
1191         bne     .load_up_altivec        /* if from user, just load it up */
1192 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1193 #endif
1194         bl      .save_nvgprs
1195         addi    r3,r1,STACK_FRAME_OVERHEAD
1196         ENABLE_INTS
1197         bl      .altivec_unavailable_exception
1198         b       .ret_from_except
1199
1200 #ifdef CONFIG_ALTIVEC
1201 /*
1202  * load_up_altivec(unused, unused, tsk)
1203  * Disable VMX for the task which had it previously,
1204  * and save its vector registers in its thread_struct.
1205  * Enables the VMX for use in the kernel on return.
1206  * On SMP we know the VMX is free, since we give it up every
1207  * switch (ie, no lazy save of the vector registers).
1208  * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1209  */
1210 _STATIC(load_up_altivec)
1211         mfmsr   r5                      /* grab the current MSR */
1212         oris    r5,r5,MSR_VEC@h
1213         mtmsrd  r5                      /* enable use of VMX now */
1214         isync
1215
1216 /*
1217  * For SMP, we don't do lazy VMX switching because it just gets too
1218  * horrendously complex, especially when a task switches from one CPU
1219  * to another.  Instead we call giveup_altvec in switch_to.
1220  * VRSAVE isn't dealt with here, that is done in the normal context
1221  * switch code. Note that we could rely on vrsave value to eventually
1222  * avoid saving all of the VREGs here...
1223  */
1224 #ifndef CONFIG_SMP
1225         ld      r3,last_task_used_altivec@got(r2)
1226         ld      r4,0(r3)
1227         cmpdi   0,r4,0
1228         beq     1f
1229         /* Save VMX state to last_task_used_altivec's THREAD struct */
1230         addi    r4,r4,THREAD
1231         SAVE_32VRS(0,r5,r4)
1232         mfvscr  vr0
1233         li      r10,THREAD_VSCR
1234         stvx    vr0,r10,r4
1235         /* Disable VMX for last_task_used_altivec */
1236         ld      r5,PT_REGS(r4)
1237         ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1238         lis     r6,MSR_VEC@h
1239         andc    r4,r4,r6
1240         std     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1241 1:
1242 #endif /* CONFIG_SMP */
1243         /* Hack: if we get an altivec unavailable trap with VRSAVE
1244          * set to all zeros, we assume this is a broken application
1245          * that fails to set it properly, and thus we switch it to
1246          * all 1's
1247          */
1248         mfspr   r4,SPRN_VRSAVE
1249         cmpdi   0,r4,0
1250         bne+    1f
1251         li      r4,-1
1252         mtspr   SPRN_VRSAVE,r4
1253 1:
1254         /* enable use of VMX after return */
1255         ld      r4,PACACURRENT(r13)
1256         addi    r5,r4,THREAD            /* Get THREAD */
1257         oris    r12,r12,MSR_VEC@h
1258         std     r12,_MSR(r1)
1259         li      r4,1
1260         li      r10,THREAD_VSCR
1261         stw     r4,THREAD_USED_VR(r5)
1262         lvx     vr0,r10,r5
1263         mtvscr  vr0
1264         REST_32VRS(0,r4,r5)
1265 #ifndef CONFIG_SMP
1266         /* Update last_task_used_math to 'current' */
1267         subi    r4,r5,THREAD            /* Back to 'current' */
1268         std     r4,0(r3)
1269 #endif /* CONFIG_SMP */
1270         /* restore registers and return */
1271         b       fast_exception_return
1272 #endif /* CONFIG_ALTIVEC */
1273
1274 /*
1275  * Hash table stuff
1276  */
1277         .align  7
1278 _GLOBAL(do_hash_page)
1279         std     r3,_DAR(r1)
1280         std     r4,_DSISR(r1)
1281
1282         andis.  r0,r4,0xa450            /* weird error? */
1283         bne-    handle_page_fault       /* if not, try to insert a HPTE */
1284 BEGIN_FTR_SECTION
1285         andis.  r0,r4,0x0020            /* Is it a segment table fault? */
1286         bne-    do_ste_alloc            /* If so handle it */
1287 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1288
1289         /*
1290          * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1291          * accessing a userspace segment (even from the kernel). We assume
1292          * kernel addresses always have the high bit set.
1293          */
1294         rlwinm  r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1295         rotldi  r0,r3,15                /* Move high bit into MSR_PR posn */
1296         orc     r0,r12,r0               /* MSR_PR | ~high_bit */
1297         rlwimi  r4,r0,32-13,30,30       /* becomes _PAGE_USER access bit */
1298         ori     r4,r4,1                 /* add _PAGE_PRESENT */
1299         rlwimi  r4,r5,22+2,31-2,31-2    /* Set _PAGE_EXEC if trap is 0x400 */
1300
1301         /*
1302          * On iSeries, we soft-disable interrupts here, then
1303          * hard-enable interrupts so that the hash_page code can spin on
1304          * the hash_table_lock without problems on a shared processor.
1305          */
1306         DISABLE_INTS
1307
1308         /*
1309          * r3 contains the faulting address
1310          * r4 contains the required access permissions
1311          * r5 contains the trap number
1312          *
1313          * at return r3 = 0 for success
1314          */
1315         bl      .hash_page              /* build HPTE if possible */
1316         cmpdi   r3,0                    /* see if hash_page succeeded */
1317
1318 #ifdef DO_SOFT_DISABLE
1319 BEGIN_FW_FTR_SECTION
1320         /*
1321          * If we had interrupts soft-enabled at the point where the
1322          * DSI/ISI occurred, and an interrupt came in during hash_page,
1323          * handle it now.
1324          * We jump to ret_from_except_lite rather than fast_exception_return
1325          * because ret_from_except_lite will check for and handle pending
1326          * interrupts if necessary.
1327          */
1328         beq     13f
1329         /* For a hash failure, we don't bother re-enabling interrupts */
1330         ble-    12f
1331
1332         /*
1333          * hash_page couldn't handle it, set soft interrupt enable back
1334          * to what it was before the trap.  Note that .local_irq_restore
1335          * handles any interrupts pending at this point.
1336          */
1337         ld      r3,SOFTE(r1)
1338         bl      .local_irq_restore
1339         b       11f
1340 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1341 #endif
1342 BEGIN_FW_FTR_SECTION
1343         beq     fast_exception_return   /* Return from exception on success */
1344         ble-    12f                     /* Failure return from hash_page */
1345
1346         /* fall through */
1347 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1348
1349 /* Here we have a page fault that hash_page can't handle. */
1350 handle_page_fault:
1351         ENABLE_INTS
1352 11:     ld      r4,_DAR(r1)
1353         ld      r5,_DSISR(r1)
1354         addi    r3,r1,STACK_FRAME_OVERHEAD
1355         bl      .do_page_fault
1356         cmpdi   r3,0
1357         beq+    13f
1358         bl      .save_nvgprs
1359         mr      r5,r3
1360         addi    r3,r1,STACK_FRAME_OVERHEAD
1361         lwz     r4,_DAR(r1)
1362         bl      .bad_page_fault
1363         b       .ret_from_except
1364
1365 /* We have a page fault that hash_page could handle but HV refused
1366  * the PTE insertion
1367  */
1368 12:     bl      .save_nvgprs
1369         addi    r3,r1,STACK_FRAME_OVERHEAD
1370         lwz     r4,_DAR(r1)
1371         bl      .low_hash_fault
1372         b       .ret_from_except
1373
1374 13:     b       .ret_from_except_lite
1375
1376         /* here we have a segment miss */
1377 do_ste_alloc:
1378         bl      .ste_allocate           /* try to insert stab entry */
1379         cmpdi   r3,0
1380         bne-    handle_page_fault
1381         b       fast_exception_return
1382
1383 /*
1384  * r13 points to the PACA, r9 contains the saved CR,
1385  * r11 and r12 contain the saved SRR0 and SRR1.
1386  * r9 - r13 are saved in paca->exslb.
1387  * We assume we aren't going to take any exceptions during this procedure.
1388  * We assume (DAR >> 60) == 0xc.
1389  */
1390         .align  7
1391 _GLOBAL(do_stab_bolted)
1392         stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
1393         std     r11,PACA_EXSLB+EX_SRR0(r13)     /* save SRR0 in exc. frame */
1394
1395         /* Hash to the primary group */
1396         ld      r10,PACASTABVIRT(r13)
1397         mfspr   r11,SPRN_DAR
1398         srdi    r11,r11,28
1399         rldimi  r10,r11,7,52    /* r10 = first ste of the group */
1400
1401         /* Calculate VSID */
1402         /* This is a kernel address, so protovsid = ESID */
1403         ASM_VSID_SCRAMBLE(r11, r9)
1404         rldic   r9,r11,12,16    /* r9 = vsid << 12 */
1405
1406         /* Search the primary group for a free entry */
1407 1:      ld      r11,0(r10)      /* Test valid bit of the current ste    */
1408         andi.   r11,r11,0x80
1409         beq     2f
1410         addi    r10,r10,16
1411         andi.   r11,r10,0x70
1412         bne     1b
1413
1414         /* Stick for only searching the primary group for now.          */
1415         /* At least for now, we use a very simple random castout scheme */
1416         /* Use the TB as a random number ;  OR in 1 to avoid entry 0    */
1417         mftb    r11
1418         rldic   r11,r11,4,57    /* r11 = (r11 << 4) & 0x70 */
1419         ori     r11,r11,0x10
1420
1421         /* r10 currently points to an ste one past the group of interest */
1422         /* make it point to the randomly selected entry                 */
1423         subi    r10,r10,128
1424         or      r10,r10,r11     /* r10 is the entry to invalidate       */
1425
1426         isync                   /* mark the entry invalid               */
1427         ld      r11,0(r10)
1428         rldicl  r11,r11,56,1    /* clear the valid bit */
1429         rotldi  r11,r11,8
1430         std     r11,0(r10)
1431         sync
1432
1433         clrrdi  r11,r11,28      /* Get the esid part of the ste         */
1434         slbie   r11
1435
1436 2:      std     r9,8(r10)       /* Store the vsid part of the ste       */
1437         eieio
1438
1439         mfspr   r11,SPRN_DAR            /* Get the new esid                     */
1440         clrrdi  r11,r11,28      /* Permits a full 32b of ESID           */
1441         ori     r11,r11,0x90    /* Turn on valid and kp                 */
1442         std     r11,0(r10)      /* Put new entry back into the stab     */
1443
1444         sync
1445
1446         /* All done -- return from exception. */
1447         lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
1448         ld      r11,PACA_EXSLB+EX_SRR0(r13)     /* get saved SRR0 */
1449
1450         andi.   r10,r12,MSR_RI
1451         beq-    unrecov_slb
1452
1453         mtcrf   0x80,r9                 /* restore CR */
1454
1455         mfmsr   r10
1456         clrrdi  r10,r10,2
1457         mtmsrd  r10,1
1458
1459         mtspr   SPRN_SRR0,r11
1460         mtspr   SPRN_SRR1,r12
1461         ld      r9,PACA_EXSLB+EX_R9(r13)
1462         ld      r10,PACA_EXSLB+EX_R10(r13)
1463         ld      r11,PACA_EXSLB+EX_R11(r13)
1464         ld      r12,PACA_EXSLB+EX_R12(r13)
1465         ld      r13,PACA_EXSLB+EX_R13(r13)
1466         rfid
1467         b       .       /* prevent speculative execution */
1468
1469 /*
1470  * Space for CPU0's segment table.
1471  *
1472  * On iSeries, the hypervisor must fill in at least one entry before
1473  * we get control (with relocate on).  The address is give to the hv
1474  * as a page number (see xLparMap in lpardata.c), so this must be at a
1475  * fixed address (the linker can't compute (u64)&initial_stab >>
1476  * PAGE_SHIFT).
1477  */
1478         . = STAB0_OFFSET        /* 0x6000 */
1479         .globl initial_stab
1480 initial_stab:
1481         .space  4096
1482
1483 /*
1484  * Data area reserved for FWNMI option.
1485  * This address (0x7000) is fixed by the RPA.
1486  */
1487         .= 0x7000
1488         .globl fwnmi_data_area
1489 fwnmi_data_area:
1490
1491         /* iSeries does not use the FWNMI stuff, so it is safe to put
1492          * this here, even if we later allow kernels that will boot on
1493          * both pSeries and iSeries */
1494 #ifdef CONFIG_PPC_ISERIES
1495         . = LPARMAP_PHYS
1496 #include "lparmap.s"
1497 /*
1498  * This ".text" is here for old compilers that generate a trailing
1499  * .note section when compiling .c files to .s
1500  */
1501         .text
1502 #endif /* CONFIG_PPC_ISERIES */
1503
1504         . = 0x8000
1505
1506 /*
1507  * On pSeries and most other platforms, secondary processors spin
1508  * in the following code.
1509  * At entry, r3 = this processor's number (physical cpu id)
1510  */
1511 _GLOBAL(generic_secondary_smp_init)
1512         mr      r24,r3
1513
1514         /* turn on 64-bit mode */
1515         bl      .enable_64b_mode
1516         isync
1517
1518         /* Set up a paca value for this processor. Since we have the
1519          * physical cpu id in r24, we need to search the pacas to find
1520          * which logical id maps to our physical one.
1521          */
1522         LOAD_REG_IMMEDIATE(r13, paca)   /* Get base vaddr of paca array  */
1523         li      r5,0                    /* logical cpu id                */
1524 1:      lhz     r6,PACAHWCPUID(r13)     /* Load HW procid from paca      */
1525         cmpw    r6,r24                  /* Compare to our id             */
1526         beq     2f
1527         addi    r13,r13,PACA_SIZE       /* Loop to next PACA on miss     */
1528         addi    r5,r5,1
1529         cmpwi   r5,NR_CPUS
1530         blt     1b
1531
1532         mr      r3,r24                  /* not found, copy phys to r3    */
1533         b       .kexec_wait             /* next kernel might do better   */
1534
1535 2:      mtspr   SPRN_SPRG3,r13          /* Save vaddr of paca in SPRG3   */
1536         /* From now on, r24 is expected to be logical cpuid */
1537         mr      r24,r5
1538 3:      HMT_LOW
1539         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor should */
1540                                         /* start.                        */
1541         sync
1542
1543 #ifndef CONFIG_SMP
1544         b       3b                      /* Never go on non-SMP           */
1545 #else
1546         cmpwi   0,r23,0
1547         beq     3b                      /* Loop until told to go         */
1548
1549         /* See if we need to call a cpu state restore handler */
1550         LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1551         ld      r23,0(r23)
1552         ld      r23,CPU_SPEC_RESTORE(r23)
1553         cmpdi   0,r23,0
1554         beq     4f
1555         ld      r23,0(r23)
1556         mtctr   r23
1557         bctrl
1558
1559 4:      /* Create a temp kernel stack for use before relocation is on.  */
1560         ld      r1,PACAEMERGSP(r13)
1561         subi    r1,r1,STACK_FRAME_OVERHEAD
1562
1563         b       .__secondary_start
1564 #endif
1565
1566 #ifdef CONFIG_PPC_ISERIES
1567 _STATIC(__start_initialization_iSeries)
1568         /* Clear out the BSS */
1569         LOAD_REG_IMMEDIATE(r11,__bss_stop)
1570         LOAD_REG_IMMEDIATE(r8,__bss_start)
1571         sub     r11,r11,r8              /* bss size                     */
1572         addi    r11,r11,7               /* round up to an even double word */
1573         rldicl. r11,r11,61,3            /* shift right by 3             */
1574         beq     4f
1575         addi    r8,r8,-8
1576         li      r0,0
1577         mtctr   r11                     /* zero this many doublewords   */
1578 3:      stdu    r0,8(r8)
1579         bdnz    3b
1580 4:
1581         LOAD_REG_IMMEDIATE(r1,init_thread_union)
1582         addi    r1,r1,THREAD_SIZE
1583         li      r0,0
1584         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
1585
1586         LOAD_REG_IMMEDIATE(r2,__toc_start)
1587         addi    r2,r2,0x4000
1588         addi    r2,r2,0x4000
1589
1590         bl      .iSeries_early_setup
1591         bl      .early_setup
1592
1593         /* relocation is on at this point */
1594
1595         b       .start_here_common
1596 #endif /* CONFIG_PPC_ISERIES */
1597
1598 #ifdef CONFIG_PPC_MULTIPLATFORM
1599
1600 _STATIC(__mmu_off)
1601         mfmsr   r3
1602         andi.   r0,r3,MSR_IR|MSR_DR
1603         beqlr
1604         andc    r3,r3,r0
1605         mtspr   SPRN_SRR0,r4
1606         mtspr   SPRN_SRR1,r3
1607         sync
1608         rfid
1609         b       .       /* prevent speculative execution */
1610
1611
1612 /*
1613  * Here is our main kernel entry point. We support currently 2 kind of entries
1614  * depending on the value of r5.
1615  *
1616  *   r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1617  *                 in r3...r7
1618  *
1619  *   r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1620  *                 DT block, r4 is a physical pointer to the kernel itself
1621  *
1622  */
1623 _GLOBAL(__start_initialization_multiplatform)
1624 #ifdef CONFIG_PPC_MULTIPLATFORM
1625         /*
1626          * Are we booted from a PROM Of-type client-interface ?
1627          */
1628         cmpldi  cr0,r5,0
1629         bne     .__boot_from_prom               /* yes -> prom */
1630 #endif
1631
1632         /* Save parameters */
1633         mr      r31,r3
1634         mr      r30,r4
1635
1636         /* Make sure we are running in 64 bits mode */
1637         bl      .enable_64b_mode
1638
1639         /* Setup some critical 970 SPRs before switching MMU off */
1640         mfspr   r0,SPRN_PVR
1641         srwi    r0,r0,16
1642         cmpwi   r0,0x39         /* 970 */
1643         beq     1f
1644         cmpwi   r0,0x3c         /* 970FX */
1645         beq     1f
1646         cmpwi   r0,0x44         /* 970MP */
1647         beq     1f
1648         cmpwi   r0,0x45         /* 970GX */
1649         bne     2f
1650 1:      bl      .__cpu_preinit_ppc970
1651 2:
1652
1653         /* Switch off MMU if not already */
1654         LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1655         add     r4,r4,r30
1656         bl      .__mmu_off
1657         b       .__after_prom_start
1658
1659 #ifdef CONFIG_PPC_MULTIPLATFORM
1660 _STATIC(__boot_from_prom)
1661         /* Save parameters */
1662         mr      r31,r3
1663         mr      r30,r4
1664         mr      r29,r5
1665         mr      r28,r6
1666         mr      r27,r7
1667
1668         /*
1669          * Align the stack to 16-byte boundary
1670          * Depending on the size and layout of the ELF sections in the initial
1671          * boot binary, the stack pointer will be unalignet on PowerMac
1672          */
1673         rldicr  r1,r1,0,59
1674
1675         /* Make sure we are running in 64 bits mode */
1676         bl      .enable_64b_mode
1677
1678         /* put a relocation offset into r3 */
1679         bl      .reloc_offset
1680
1681         LOAD_REG_IMMEDIATE(r2,__toc_start)
1682         addi    r2,r2,0x4000
1683         addi    r2,r2,0x4000
1684
1685         /* Relocate the TOC from a virt addr to a real addr */
1686         add     r2,r2,r3
1687
1688         /* Restore parameters */
1689         mr      r3,r31
1690         mr      r4,r30
1691         mr      r5,r29
1692         mr      r6,r28
1693         mr      r7,r27
1694
1695         /* Do all of the interaction with OF client interface */
1696         bl      .prom_init
1697         /* We never return */
1698         trap
1699 #endif
1700
1701 /*
1702  * At this point, r3 contains the physical address we are running at,
1703  * returned by prom_init()
1704  */
1705 _STATIC(__after_prom_start)
1706
1707 /*
1708  * We need to run with __start at physical address PHYSICAL_START.
1709  * This will leave some code in the first 256B of
1710  * real memory, which are reserved for software use.
1711  * The remainder of the first page is loaded with the fixed
1712  * interrupt vectors.  The next two pages are filled with
1713  * unknown exception placeholders.
1714  *
1715  * Note: This process overwrites the OF exception vectors.
1716  *      r26 == relocation offset
1717  *      r27 == KERNELBASE
1718  */
1719         bl      .reloc_offset
1720         mr      r26,r3
1721         LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1722
1723         LOAD_REG_IMMEDIATE(r3, PHYSICAL_START)  /* target addr */
1724
1725         // XXX FIXME: Use phys returned by OF (r30)
1726         add     r4,r27,r26              /* source addr                   */
1727                                         /* current address of _start     */
1728                                         /*   i.e. where we are running   */
1729                                         /*      the source addr          */
1730
1731         cmpdi   r4,0                    /* In some cases the loader may  */
1732         beq     .start_here_multiplatform /* have already put us at zero */
1733                                         /* so we can skip the copy.      */
1734         LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1735         sub     r5,r5,r27
1736
1737         li      r6,0x100                /* Start offset, the first 0x100 */
1738                                         /* bytes were copied earlier.    */
1739
1740         bl      .copy_and_flush         /* copy the first n bytes        */
1741                                         /* this includes the code being  */
1742                                         /* executed here.                */
1743
1744         LOAD_REG_IMMEDIATE(r0, 4f)      /* Jump to the copy of this code */
1745         mtctr   r0                      /* that we just made/relocated   */
1746         bctr
1747
1748 4:      LOAD_REG_IMMEDIATE(r5,klimit)
1749         add     r5,r5,r26
1750         ld      r5,0(r5)                /* get the value of klimit */
1751         sub     r5,r5,r27
1752         bl      .copy_and_flush         /* copy the rest */
1753         b       .start_here_multiplatform
1754
1755 #endif /* CONFIG_PPC_MULTIPLATFORM */
1756
1757 /*
1758  * Copy routine used to copy the kernel to start at physical address 0
1759  * and flush and invalidate the caches as needed.
1760  * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1761  * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1762  *
1763  * Note: this routine *only* clobbers r0, r6 and lr
1764  */
1765 _GLOBAL(copy_and_flush)
1766         addi    r5,r5,-8
1767         addi    r6,r6,-8
1768 4:      li      r0,8                    /* Use the smallest common      */
1769                                         /* denominator cache line       */
1770                                         /* size.  This results in       */
1771                                         /* extra cache line flushes     */
1772                                         /* but operation is correct.    */
1773                                         /* Can't get cache line size    */
1774                                         /* from NACA as it is being     */
1775                                         /* moved too.                   */
1776
1777         mtctr   r0                      /* put # words/line in ctr      */
1778 3:      addi    r6,r6,8                 /* copy a cache line            */
1779         ldx     r0,r6,r4
1780         stdx    r0,r6,r3
1781         bdnz    3b
1782         dcbst   r6,r3                   /* write it to memory           */
1783         sync
1784         icbi    r6,r3                   /* flush the icache line        */
1785         cmpld   0,r6,r5
1786         blt     4b
1787         sync
1788         addi    r5,r5,8
1789         addi    r6,r6,8
1790         blr
1791
1792 .align 8
1793 copy_to_here:
1794
1795 #ifdef CONFIG_SMP
1796 #ifdef CONFIG_PPC_PMAC
1797 /*
1798  * On PowerMac, secondary processors starts from the reset vector, which
1799  * is temporarily turned into a call to one of the functions below.
1800  */
1801         .section ".text";
1802         .align 2 ;
1803
1804         .globl  __secondary_start_pmac_0
1805 __secondary_start_pmac_0:
1806         /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1807         li      r24,0
1808         b       1f
1809         li      r24,1
1810         b       1f
1811         li      r24,2
1812         b       1f
1813         li      r24,3
1814 1:
1815
1816 _GLOBAL(pmac_secondary_start)
1817         /* turn on 64-bit mode */
1818         bl      .enable_64b_mode
1819         isync
1820
1821         /* Copy some CPU settings from CPU 0 */
1822         bl      .__restore_cpu_ppc970
1823
1824         /* pSeries do that early though I don't think we really need it */
1825         mfmsr   r3
1826         ori     r3,r3,MSR_RI
1827         mtmsrd  r3                      /* RI on */
1828
1829         /* Set up a paca value for this processor. */
1830         LOAD_REG_IMMEDIATE(r4, paca)    /* Get base vaddr of paca array */
1831         mulli   r13,r24,PACA_SIZE        /* Calculate vaddr of right paca */
1832         add     r13,r13,r4              /* for this processor.          */
1833         mtspr   SPRN_SPRG3,r13           /* Save vaddr of paca in SPRG3 */
1834
1835         /* Create a temp kernel stack for use before relocation is on.  */
1836         ld      r1,PACAEMERGSP(r13)
1837         subi    r1,r1,STACK_FRAME_OVERHEAD
1838
1839         b       .__secondary_start
1840
1841 #endif /* CONFIG_PPC_PMAC */
1842
1843 /*
1844  * This function is called after the master CPU has released the
1845  * secondary processors.  The execution environment is relocation off.
1846  * The paca for this processor has the following fields initialized at
1847  * this point:
1848  *   1. Processor number
1849  *   2. Segment table pointer (virtual address)
1850  * On entry the following are set:
1851  *   r1 = stack pointer.  vaddr for iSeries, raddr (temp stack) for pSeries
1852  *   r24   = cpu# (in Linux terms)
1853  *   r13   = paca virtual address
1854  *   SPRG3 = paca virtual address
1855  */
1856 _GLOBAL(__secondary_start)
1857         /* Set thread priority to MEDIUM */
1858         HMT_MEDIUM
1859
1860         /* Load TOC */
1861         ld      r2,PACATOC(r13)
1862
1863         /* Do early setup for that CPU (stab, slb, hash table pointer) */
1864         bl      .early_setup_secondary
1865
1866         /* Initialize the kernel stack.  Just a repeat for iSeries.      */
1867         LOAD_REG_ADDR(r3, current_set)
1868         sldi    r28,r24,3               /* get current_set[cpu#]         */
1869         ldx     r1,r3,r28
1870         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1871         std     r1,PACAKSAVE(r13)
1872
1873         /* Clear backchain so we get nice backtraces */
1874         li      r7,0
1875         mtlr    r7
1876
1877         /* enable MMU and jump to start_secondary */
1878         LOAD_REG_ADDR(r3, .start_secondary_prolog)
1879         LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1880 #ifdef DO_SOFT_DISABLE
1881 BEGIN_FW_FTR_SECTION
1882         ori     r4,r4,MSR_EE
1883 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1884 #endif
1885         mtspr   SPRN_SRR0,r3
1886         mtspr   SPRN_SRR1,r4
1887         rfid
1888         b       .       /* prevent speculative execution */
1889
1890 /*
1891  * Running with relocation on at this point.  All we want to do is
1892  * zero the stack back-chain pointer before going into C code.
1893  */
1894 _GLOBAL(start_secondary_prolog)
1895         li      r3,0
1896         std     r3,0(r1)                /* Zero the stack frame pointer */
1897         bl      .start_secondary
1898         b       .
1899 #endif
1900
1901 /*
1902  * This subroutine clobbers r11 and r12
1903  */
1904 _GLOBAL(enable_64b_mode)
1905         mfmsr   r11                     /* grab the current MSR */
1906         li      r12,1
1907         rldicr  r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1908         or      r11,r11,r12
1909         li      r12,1
1910         rldicr  r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1911         or      r11,r11,r12
1912         mtmsrd  r11
1913         isync
1914         blr
1915
1916 #ifdef CONFIG_PPC_MULTIPLATFORM
1917 /*
1918  * This is where the main kernel code starts.
1919  */
1920 _STATIC(start_here_multiplatform)
1921         /* get a new offset, now that the kernel has moved. */
1922         bl      .reloc_offset
1923         mr      r26,r3
1924
1925         /* Clear out the BSS. It may have been done in prom_init,
1926          * already but that's irrelevant since prom_init will soon
1927          * be detached from the kernel completely. Besides, we need
1928          * to clear it now for kexec-style entry.
1929          */
1930         LOAD_REG_IMMEDIATE(r11,__bss_stop)
1931         LOAD_REG_IMMEDIATE(r8,__bss_start)
1932         sub     r11,r11,r8              /* bss size                     */
1933         addi    r11,r11,7               /* round up to an even double word */
1934         rldicl. r11,r11,61,3            /* shift right by 3             */
1935         beq     4f
1936         addi    r8,r8,-8
1937         li      r0,0
1938         mtctr   r11                     /* zero this many doublewords   */
1939 3:      stdu    r0,8(r8)
1940         bdnz    3b
1941 4:
1942
1943         mfmsr   r6
1944         ori     r6,r6,MSR_RI
1945         mtmsrd  r6                      /* RI on */
1946
1947         /* The following gets the stack and TOC set up with the regs */
1948         /* pointing to the real addr of the kernel stack.  This is   */
1949         /* all done to support the C function call below which sets  */
1950         /* up the htab.  This is done because we have relocated the  */
1951         /* kernel but are still running in real mode. */
1952
1953         LOAD_REG_IMMEDIATE(r3,init_thread_union)
1954         add     r3,r3,r26
1955
1956         /* set up a stack pointer (physical address) */
1957         addi    r1,r3,THREAD_SIZE
1958         li      r0,0
1959         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
1960
1961         /* set up the TOC (physical address) */
1962         LOAD_REG_IMMEDIATE(r2,__toc_start)
1963         addi    r2,r2,0x4000
1964         addi    r2,r2,0x4000
1965         add     r2,r2,r26
1966
1967         /* Do very early kernel initializations, including initial hash table,
1968          * stab and slb setup before we turn on relocation.     */
1969
1970         /* Restore parameters passed from prom_init/kexec */
1971         mr      r3,r31
1972         bl      .early_setup
1973
1974         LOAD_REG_IMMEDIATE(r3, .start_here_common)
1975         LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1976         mtspr   SPRN_SRR0,r3
1977         mtspr   SPRN_SRR1,r4
1978         rfid
1979         b       .       /* prevent speculative execution */
1980 #endif /* CONFIG_PPC_MULTIPLATFORM */
1981
1982         /* This is where all platforms converge execution */
1983 _STATIC(start_here_common)
1984         /* relocation is on at this point */
1985
1986         /* The following code sets up the SP and TOC now that we are */
1987         /* running with translation enabled. */
1988
1989         LOAD_REG_IMMEDIATE(r3,init_thread_union)
1990
1991         /* set up the stack */
1992         addi    r1,r3,THREAD_SIZE
1993         li      r0,0
1994         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
1995
1996         /* ptr to current */
1997         LOAD_REG_IMMEDIATE(r4, init_task)
1998         std     r4,PACACURRENT(r13)
1999
2000         /* Load the TOC */
2001         ld      r2,PACATOC(r13)
2002         std     r1,PACAKSAVE(r13)
2003
2004         bl      .setup_system
2005
2006         /* Load up the kernel context */
2007 5:
2008 #ifdef DO_SOFT_DISABLE
2009 BEGIN_FW_FTR_SECTION
2010         li      r5,0
2011         stb     r5,PACAPROCENABLED(r13) /* Soft Disabled */
2012         mfmsr   r5
2013         ori     r5,r5,MSR_EE            /* Hard Enabled */
2014         mtmsrd  r5
2015 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
2016 #endif
2017
2018         bl .start_kernel
2019
2020         /* Not reached */
2021         BUG_OPCODE
2022
2023 /*
2024  * We put a few things here that have to be page-aligned.
2025  * This stuff goes at the beginning of the bss, which is page-aligned.
2026  */
2027         .section ".bss"
2028
2029         .align  PAGE_SHIFT
2030
2031         .globl  empty_zero_page
2032 empty_zero_page:
2033         .space  PAGE_SIZE
2034
2035         .globl  swapper_pg_dir
2036 swapper_pg_dir:
2037         .space  PAGE_SIZE
2038
2039 /*
2040  * This space gets a copy of optional info passed to us by the bootstrap
2041  * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2042  */
2043         .globl  cmd_line
2044 cmd_line:
2045         .space  COMMAND_LINE_SIZE