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[PATCH] Remove occurences of PPC_MULTIPLATFORM in head_64.S
[deliverable/linux.git] / arch / powerpc / kernel / head_64.S
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23
24 #include <linux/threads.h>
25 #include <asm/reg.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/bug.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
37
38 #define DO_SOFT_DISABLE
39
40 /*
41 * We layout physical memory as follows:
42 * 0x0000 - 0x00ff : Secondary processor spin code
43 * 0x0100 - 0x2fff : pSeries Interrupt prologs
44 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
45 * 0x6000 - 0x6fff : Initial (CPU0) segment table
46 * 0x7000 - 0x7fff : FWNMI data area
47 * 0x8000 - : Early init and support code
48 */
49
50 /*
51 * SPRG Usage
52 *
53 * Register Definition
54 *
55 * SPRG0 reserved for hypervisor
56 * SPRG1 temp - used to save gpr
57 * SPRG2 temp - used to save gpr
58 * SPRG3 virt addr of paca
59 */
60
61 /*
62 * Entering into this code we make the following assumptions:
63 * For pSeries:
64 * 1. The MMU is off & open firmware is running in real mode.
65 * 2. The kernel is entered at __start
66 *
67 * For iSeries:
68 * 1. The MMU is on (as it always is for iSeries)
69 * 2. The kernel is entered at system_reset_iSeries
70 */
71
72 .text
73 .globl _stext
74 _stext:
75 _GLOBAL(__start)
76 /* NOP this out unconditionally */
77 BEGIN_FTR_SECTION
78 b .__start_initialization_multiplatform
79 END_FTR_SECTION(0, 1)
80
81 /* Catch branch to 0 in real mode */
82 trap
83
84 /* Secondary processors spin on this value until it goes to 1. */
85 .globl __secondary_hold_spinloop
86 __secondary_hold_spinloop:
87 .llong 0x0
88
89 /* Secondary processors write this value with their cpu # */
90 /* after they enter the spin loop immediately below. */
91 .globl __secondary_hold_acknowledge
92 __secondary_hold_acknowledge:
93 .llong 0x0
94
95 #ifdef CONFIG_PPC_ISERIES
96 /*
97 * At offset 0x20, there is a pointer to iSeries LPAR data.
98 * This is required by the hypervisor
99 */
100 . = 0x20
101 .llong hvReleaseData-KERNELBASE
102 #endif /* CONFIG_PPC_ISERIES */
103
104 . = 0x60
105 /*
106 * The following code is used on pSeries to hold secondary processors
107 * in a spin loop after they have been freed from OpenFirmware, but
108 * before the bulk of the kernel has been relocated. This code
109 * is relocated to physical address 0x60 before prom_init is run.
110 * All of it must fit below the first exception vector at 0x100.
111 */
112 _GLOBAL(__secondary_hold)
113 mfmsr r24
114 ori r24,r24,MSR_RI
115 mtmsrd r24 /* RI on */
116
117 /* Grab our physical cpu number */
118 mr r24,r3
119
120 /* Tell the master cpu we're here */
121 /* Relocation is off & we are located at an address less */
122 /* than 0x100, so only need to grab low order offset. */
123 std r24,__secondary_hold_acknowledge@l(0)
124 sync
125
126 /* All secondary cpus wait here until told to start. */
127 100: ld r4,__secondary_hold_spinloop@l(0)
128 cmpdi 0,r4,1
129 bne 100b
130
131 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
132 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
133 mtctr r4
134 mr r3,r24
135 bctr
136 #else
137 BUG_OPCODE
138 #endif
139
140 /* This value is used to mark exception frames on the stack. */
141 .section ".toc","aw"
142 exception_marker:
143 .tc ID_72656773_68657265[TC],0x7265677368657265
144 .text
145
146 /*
147 * The following macros define the code that appears as
148 * the prologue to each of the exception handlers. They
149 * are split into two parts to allow a single kernel binary
150 * to be used for pSeries and iSeries.
151 * LOL. One day... - paulus
152 */
153
154 /*
155 * We make as much of the exception code common between native
156 * exception handlers (including pSeries LPAR) and iSeries LPAR
157 * implementations as possible.
158 */
159
160 /*
161 * This is the start of the interrupt handlers for pSeries
162 * This code runs with relocation off.
163 */
164 #define EX_R9 0
165 #define EX_R10 8
166 #define EX_R11 16
167 #define EX_R12 24
168 #define EX_R13 32
169 #define EX_SRR0 40
170 #define EX_DAR 48
171 #define EX_DSISR 56
172 #define EX_CCR 60
173 #define EX_R3 64
174 #define EX_LR 72
175
176 /*
177 * We're short on space and time in the exception prolog, so we can't
178 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
179 * low halfword of the address, but for Kdump we need the whole low
180 * word.
181 */
182 #ifdef CONFIG_CRASH_DUMP
183 #define LOAD_HANDLER(reg, label) \
184 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
185 ori reg,reg,(label)@l; /* .. and the rest */
186 #else
187 #define LOAD_HANDLER(reg, label) \
188 ori reg,reg,(label)@l; /* virt addr of handler ... */
189 #endif
190
191 /*
192 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
193 * The firmware calls the registered system_reset_fwnmi and
194 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
195 * a 32bit application at the time of the event.
196 * This firmware bug is present on POWER4 and JS20.
197 */
198 #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
199 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
200 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
201 std r10,area+EX_R10(r13); \
202 std r11,area+EX_R11(r13); \
203 std r12,area+EX_R12(r13); \
204 mfspr r9,SPRN_SPRG1; \
205 std r9,area+EX_R13(r13); \
206 mfcr r9; \
207 clrrdi r12,r13,32; /* get high part of &label */ \
208 mfmsr r10; \
209 /* force 64bit mode */ \
210 li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \
211 rldimi r10,r11,61,0; /* insert into top 3 bits */ \
212 /* done 64bit mode */ \
213 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
214 LOAD_HANDLER(r12,label) \
215 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
216 mtspr SPRN_SRR0,r12; \
217 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
218 mtspr SPRN_SRR1,r10; \
219 rfid; \
220 b . /* prevent speculative execution */
221
222 #define EXCEPTION_PROLOG_PSERIES(area, label) \
223 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
224 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
225 std r10,area+EX_R10(r13); \
226 std r11,area+EX_R11(r13); \
227 std r12,area+EX_R12(r13); \
228 mfspr r9,SPRN_SPRG1; \
229 std r9,area+EX_R13(r13); \
230 mfcr r9; \
231 clrrdi r12,r13,32; /* get high part of &label */ \
232 mfmsr r10; \
233 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
234 LOAD_HANDLER(r12,label) \
235 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
236 mtspr SPRN_SRR0,r12; \
237 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
238 mtspr SPRN_SRR1,r10; \
239 rfid; \
240 b . /* prevent speculative execution */
241
242 /*
243 * This is the start of the interrupt handlers for iSeries
244 * This code runs with relocation on.
245 */
246 #define EXCEPTION_PROLOG_ISERIES_1(area) \
247 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
248 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
249 std r10,area+EX_R10(r13); \
250 std r11,area+EX_R11(r13); \
251 std r12,area+EX_R12(r13); \
252 mfspr r9,SPRN_SPRG1; \
253 std r9,area+EX_R13(r13); \
254 mfcr r9
255
256 #define EXCEPTION_PROLOG_ISERIES_2 \
257 mfmsr r10; \
258 ld r12,PACALPPACAPTR(r13); \
259 ld r11,LPPACASRR0(r12); \
260 ld r12,LPPACASRR1(r12); \
261 ori r10,r10,MSR_RI; \
262 mtmsrd r10,1
263
264 /*
265 * The common exception prolog is used for all except a few exceptions
266 * such as a segment miss on a kernel address. We have to be prepared
267 * to take another exception from the point where we first touch the
268 * kernel stack onwards.
269 *
270 * On entry r13 points to the paca, r9-r13 are saved in the paca,
271 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
272 * SRR1, and relocation is on.
273 */
274 #define EXCEPTION_PROLOG_COMMON(n, area) \
275 andi. r10,r12,MSR_PR; /* See if coming from user */ \
276 mr r10,r1; /* Save r1 */ \
277 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
278 beq- 1f; \
279 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
280 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
281 bge- cr1,bad_stack; /* abort if it is */ \
282 std r9,_CCR(r1); /* save CR in stackframe */ \
283 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
284 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
285 std r10,0(r1); /* make stack chain pointer */ \
286 std r0,GPR0(r1); /* save r0 in stackframe */ \
287 std r10,GPR1(r1); /* save r1 in stackframe */ \
288 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
289 std r2,GPR2(r1); /* save r2 in stackframe */ \
290 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
291 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
292 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
293 ld r10,area+EX_R10(r13); \
294 std r9,GPR9(r1); \
295 std r10,GPR10(r1); \
296 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
297 ld r10,area+EX_R12(r13); \
298 ld r11,area+EX_R13(r13); \
299 std r9,GPR11(r1); \
300 std r10,GPR12(r1); \
301 std r11,GPR13(r1); \
302 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
303 mflr r9; /* save LR in stackframe */ \
304 std r9,_LINK(r1); \
305 mfctr r10; /* save CTR in stackframe */ \
306 std r10,_CTR(r1); \
307 lbz r10,PACASOFTIRQEN(r13); \
308 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
309 std r10,SOFTE(r1); \
310 std r11,_XER(r1); \
311 li r9,(n)+1; \
312 std r9,_TRAP(r1); /* set trap number */ \
313 li r10,0; \
314 ld r11,exception_marker@toc(r2); \
315 std r10,RESULT(r1); /* clear regs->result */ \
316 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
317
318 /*
319 * Exception vectors.
320 */
321 #define STD_EXCEPTION_PSERIES(n, label) \
322 . = n; \
323 .globl label##_pSeries; \
324 label##_pSeries: \
325 HMT_MEDIUM; \
326 mtspr SPRN_SPRG1,r13; /* save r13 */ \
327 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
328
329 #define HSTD_EXCEPTION_PSERIES(n, label) \
330 . = n; \
331 .globl label##_pSeries; \
332 label##_pSeries: \
333 HMT_MEDIUM; \
334 mtspr SPRN_SPRG1,r20; /* save r20 */ \
335 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
336 mtspr SPRN_SRR0,r20; \
337 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
338 mtspr SPRN_SRR1,r20; \
339 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
340 mtspr SPRN_SPRG1,r13; /* save r13 */ \
341 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
342
343
344 #define MASKABLE_EXCEPTION_PSERIES(n, label) \
345 . = n; \
346 .globl label##_pSeries; \
347 label##_pSeries: \
348 HMT_MEDIUM; \
349 mtspr SPRN_SPRG1,r13; /* save r13 */ \
350 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
351 std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
352 std r10,PACA_EXGEN+EX_R10(r13); \
353 lbz r10,PACASOFTIRQEN(r13); \
354 mfcr r9; \
355 cmpwi r10,0; \
356 beq masked_interrupt; \
357 mfspr r10,SPRN_SPRG1; \
358 std r10,PACA_EXGEN+EX_R13(r13); \
359 std r11,PACA_EXGEN+EX_R11(r13); \
360 std r12,PACA_EXGEN+EX_R12(r13); \
361 clrrdi r12,r13,32; /* get high part of &label */ \
362 mfmsr r10; \
363 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
364 LOAD_HANDLER(r12,label##_common) \
365 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
366 mtspr SPRN_SRR0,r12; \
367 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
368 mtspr SPRN_SRR1,r10; \
369 rfid; \
370 b . /* prevent speculative execution */
371
372 #define STD_EXCEPTION_ISERIES(n, label, area) \
373 .globl label##_iSeries; \
374 label##_iSeries: \
375 HMT_MEDIUM; \
376 mtspr SPRN_SPRG1,r13; /* save r13 */ \
377 EXCEPTION_PROLOG_ISERIES_1(area); \
378 EXCEPTION_PROLOG_ISERIES_2; \
379 b label##_common
380
381 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
382 .globl label##_iSeries; \
383 label##_iSeries: \
384 HMT_MEDIUM; \
385 mtspr SPRN_SPRG1,r13; /* save r13 */ \
386 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
387 lbz r10,PACASOFTIRQEN(r13); \
388 cmpwi 0,r10,0; \
389 beq- label##_iSeries_masked; \
390 EXCEPTION_PROLOG_ISERIES_2; \
391 b label##_common; \
392
393 #ifdef CONFIG_PPC_ISERIES
394 #define DISABLE_INTS \
395 li r11,0; \
396 stb r11,PACASOFTIRQEN(r13); \
397 BEGIN_FW_FTR_SECTION; \
398 stb r11,PACAHARDIRQEN(r13); \
399 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
400 BEGIN_FW_FTR_SECTION; \
401 mfmsr r10; \
402 ori r10,r10,MSR_EE; \
403 mtmsrd r10,1; \
404 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
405
406 #else
407 #define DISABLE_INTS \
408 li r11,0; \
409 stb r11,PACASOFTIRQEN(r13); \
410 stb r11,PACAHARDIRQEN(r13)
411
412 #endif /* CONFIG_PPC_ISERIES */
413
414 #define ENABLE_INTS \
415 ld r12,_MSR(r1); \
416 mfmsr r11; \
417 rlwimi r11,r12,0,MSR_EE; \
418 mtmsrd r11,1
419
420 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
421 .align 7; \
422 .globl label##_common; \
423 label##_common: \
424 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
425 DISABLE_INTS; \
426 bl .save_nvgprs; \
427 addi r3,r1,STACK_FRAME_OVERHEAD; \
428 bl hdlr; \
429 b .ret_from_except
430
431 /*
432 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
433 * in the idle task and therefore need the special idle handling.
434 */
435 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
436 .align 7; \
437 .globl label##_common; \
438 label##_common: \
439 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
440 FINISH_NAP; \
441 DISABLE_INTS; \
442 bl .save_nvgprs; \
443 addi r3,r1,STACK_FRAME_OVERHEAD; \
444 bl hdlr; \
445 b .ret_from_except
446
447 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
448 .align 7; \
449 .globl label##_common; \
450 label##_common: \
451 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
452 FINISH_NAP; \
453 DISABLE_INTS; \
454 bl .ppc64_runlatch_on; \
455 addi r3,r1,STACK_FRAME_OVERHEAD; \
456 bl hdlr; \
457 b .ret_from_except_lite
458
459 /*
460 * When the idle code in power4_idle puts the CPU into NAP mode,
461 * it has to do so in a loop, and relies on the external interrupt
462 * and decrementer interrupt entry code to get it out of the loop.
463 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
464 * to signal that it is in the loop and needs help to get out.
465 */
466 #ifdef CONFIG_PPC_970_NAP
467 #define FINISH_NAP \
468 BEGIN_FTR_SECTION \
469 clrrdi r11,r1,THREAD_SHIFT; \
470 ld r9,TI_LOCAL_FLAGS(r11); \
471 andi. r10,r9,_TLF_NAPPING; \
472 bnel power4_fixup_nap; \
473 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
474 #else
475 #define FINISH_NAP
476 #endif
477
478 /*
479 * Start of pSeries system interrupt routines
480 */
481 . = 0x100
482 .globl __start_interrupts
483 __start_interrupts:
484
485 STD_EXCEPTION_PSERIES(0x100, system_reset)
486
487 . = 0x200
488 _machine_check_pSeries:
489 HMT_MEDIUM
490 mtspr SPRN_SPRG1,r13 /* save r13 */
491 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
492
493 . = 0x300
494 .globl data_access_pSeries
495 data_access_pSeries:
496 HMT_MEDIUM
497 mtspr SPRN_SPRG1,r13
498 BEGIN_FTR_SECTION
499 mtspr SPRN_SPRG2,r12
500 mfspr r13,SPRN_DAR
501 mfspr r12,SPRN_DSISR
502 srdi r13,r13,60
503 rlwimi r13,r12,16,0x20
504 mfcr r12
505 cmpwi r13,0x2c
506 beq .do_stab_bolted_pSeries
507 mtcrf 0x80,r12
508 mfspr r12,SPRN_SPRG2
509 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
510 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
511
512 . = 0x380
513 .globl data_access_slb_pSeries
514 data_access_slb_pSeries:
515 HMT_MEDIUM
516 mtspr SPRN_SPRG1,r13
517 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
518 std r3,PACA_EXSLB+EX_R3(r13)
519 mfspr r3,SPRN_DAR
520 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
521 mfcr r9
522 #ifdef __DISABLED__
523 /* Keep that around for when we re-implement dynamic VSIDs */
524 cmpdi r3,0
525 bge slb_miss_user_pseries
526 #endif /* __DISABLED__ */
527 std r10,PACA_EXSLB+EX_R10(r13)
528 std r11,PACA_EXSLB+EX_R11(r13)
529 std r12,PACA_EXSLB+EX_R12(r13)
530 mfspr r10,SPRN_SPRG1
531 std r10,PACA_EXSLB+EX_R13(r13)
532 mfspr r12,SPRN_SRR1 /* and SRR1 */
533 b .slb_miss_realmode /* Rel. branch works in real mode */
534
535 STD_EXCEPTION_PSERIES(0x400, instruction_access)
536
537 . = 0x480
538 .globl instruction_access_slb_pSeries
539 instruction_access_slb_pSeries:
540 HMT_MEDIUM
541 mtspr SPRN_SPRG1,r13
542 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
543 std r3,PACA_EXSLB+EX_R3(r13)
544 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
545 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
546 mfcr r9
547 #ifdef __DISABLED__
548 /* Keep that around for when we re-implement dynamic VSIDs */
549 cmpdi r3,0
550 bge slb_miss_user_pseries
551 #endif /* __DISABLED__ */
552 std r10,PACA_EXSLB+EX_R10(r13)
553 std r11,PACA_EXSLB+EX_R11(r13)
554 std r12,PACA_EXSLB+EX_R12(r13)
555 mfspr r10,SPRN_SPRG1
556 std r10,PACA_EXSLB+EX_R13(r13)
557 mfspr r12,SPRN_SRR1 /* and SRR1 */
558 b .slb_miss_realmode /* Rel. branch works in real mode */
559
560 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
561 STD_EXCEPTION_PSERIES(0x600, alignment)
562 STD_EXCEPTION_PSERIES(0x700, program_check)
563 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
564 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
565 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
566 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
567
568 . = 0xc00
569 .globl system_call_pSeries
570 system_call_pSeries:
571 HMT_MEDIUM
572 mr r9,r13
573 mfmsr r10
574 mfspr r13,SPRN_SPRG3
575 mfspr r11,SPRN_SRR0
576 clrrdi r12,r13,32
577 oris r12,r12,system_call_common@h
578 ori r12,r12,system_call_common@l
579 mtspr SPRN_SRR0,r12
580 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
581 mfspr r12,SPRN_SRR1
582 mtspr SPRN_SRR1,r10
583 rfid
584 b . /* prevent speculative execution */
585
586 STD_EXCEPTION_PSERIES(0xd00, single_step)
587 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
588
589 /* We need to deal with the Altivec unavailable exception
590 * here which is at 0xf20, thus in the middle of the
591 * prolog code of the PerformanceMonitor one. A little
592 * trickery is thus necessary
593 */
594 . = 0xf00
595 b performance_monitor_pSeries
596
597 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
598
599 #ifdef CONFIG_CBE_RAS
600 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
601 #endif /* CONFIG_CBE_RAS */
602 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
603 #ifdef CONFIG_CBE_RAS
604 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
605 #endif /* CONFIG_CBE_RAS */
606 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
607 #ifdef CONFIG_CBE_RAS
608 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
609 #endif /* CONFIG_CBE_RAS */
610
611 . = 0x3000
612
613 /*** pSeries interrupt support ***/
614
615 /* moved from 0xf00 */
616 MASKABLE_EXCEPTION_PSERIES(., performance_monitor)
617
618 /*
619 * An interrupt came in while soft-disabled; clear EE in SRR1,
620 * clear paca->hard_enabled and return.
621 */
622 masked_interrupt:
623 stb r10,PACAHARDIRQEN(r13)
624 mtcrf 0x80,r9
625 ld r9,PACA_EXGEN+EX_R9(r13)
626 mfspr r10,SPRN_SRR1
627 rldicl r10,r10,48,1 /* clear MSR_EE */
628 rotldi r10,r10,16
629 mtspr SPRN_SRR1,r10
630 ld r10,PACA_EXGEN+EX_R10(r13)
631 mfspr r13,SPRN_SPRG1
632 rfid
633 b .
634
635 .align 7
636 _GLOBAL(do_stab_bolted_pSeries)
637 mtcrf 0x80,r12
638 mfspr r12,SPRN_SPRG2
639 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
640
641 /*
642 * We have some room here we use that to put
643 * the peries slb miss user trampoline code so it's reasonably
644 * away from slb_miss_user_common to avoid problems with rfid
645 *
646 * This is used for when the SLB miss handler has to go virtual,
647 * which doesn't happen for now anymore but will once we re-implement
648 * dynamic VSIDs for shared page tables
649 */
650 #ifdef __DISABLED__
651 slb_miss_user_pseries:
652 std r10,PACA_EXGEN+EX_R10(r13)
653 std r11,PACA_EXGEN+EX_R11(r13)
654 std r12,PACA_EXGEN+EX_R12(r13)
655 mfspr r10,SPRG1
656 ld r11,PACA_EXSLB+EX_R9(r13)
657 ld r12,PACA_EXSLB+EX_R3(r13)
658 std r10,PACA_EXGEN+EX_R13(r13)
659 std r11,PACA_EXGEN+EX_R9(r13)
660 std r12,PACA_EXGEN+EX_R3(r13)
661 clrrdi r12,r13,32
662 mfmsr r10
663 mfspr r11,SRR0 /* save SRR0 */
664 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
665 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
666 mtspr SRR0,r12
667 mfspr r12,SRR1 /* and SRR1 */
668 mtspr SRR1,r10
669 rfid
670 b . /* prevent spec. execution */
671 #endif /* __DISABLED__ */
672
673 /*
674 * Vectors for the FWNMI option. Share common code.
675 */
676 .globl system_reset_fwnmi
677 .align 7
678 system_reset_fwnmi:
679 HMT_MEDIUM
680 mtspr SPRN_SPRG1,r13 /* save r13 */
681 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
682
683 .globl machine_check_fwnmi
684 .align 7
685 machine_check_fwnmi:
686 HMT_MEDIUM
687 mtspr SPRN_SPRG1,r13 /* save r13 */
688 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
689
690 #ifdef CONFIG_PPC_ISERIES
691 /*** ISeries-LPAR interrupt handlers ***/
692
693 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
694
695 .globl data_access_iSeries
696 data_access_iSeries:
697 mtspr SPRN_SPRG1,r13
698 BEGIN_FTR_SECTION
699 mtspr SPRN_SPRG2,r12
700 mfspr r13,SPRN_DAR
701 mfspr r12,SPRN_DSISR
702 srdi r13,r13,60
703 rlwimi r13,r12,16,0x20
704 mfcr r12
705 cmpwi r13,0x2c
706 beq .do_stab_bolted_iSeries
707 mtcrf 0x80,r12
708 mfspr r12,SPRN_SPRG2
709 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
710 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
711 EXCEPTION_PROLOG_ISERIES_2
712 b data_access_common
713
714 .do_stab_bolted_iSeries:
715 mtcrf 0x80,r12
716 mfspr r12,SPRN_SPRG2
717 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
718 EXCEPTION_PROLOG_ISERIES_2
719 b .do_stab_bolted
720
721 .globl data_access_slb_iSeries
722 data_access_slb_iSeries:
723 mtspr SPRN_SPRG1,r13 /* save r13 */
724 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
725 std r3,PACA_EXSLB+EX_R3(r13)
726 mfspr r3,SPRN_DAR
727 std r9,PACA_EXSLB+EX_R9(r13)
728 mfcr r9
729 #ifdef __DISABLED__
730 cmpdi r3,0
731 bge slb_miss_user_iseries
732 #endif
733 std r10,PACA_EXSLB+EX_R10(r13)
734 std r11,PACA_EXSLB+EX_R11(r13)
735 std r12,PACA_EXSLB+EX_R12(r13)
736 mfspr r10,SPRN_SPRG1
737 std r10,PACA_EXSLB+EX_R13(r13)
738 ld r12,PACALPPACAPTR(r13)
739 ld r12,LPPACASRR1(r12)
740 b .slb_miss_realmode
741
742 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
743
744 .globl instruction_access_slb_iSeries
745 instruction_access_slb_iSeries:
746 mtspr SPRN_SPRG1,r13 /* save r13 */
747 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
748 std r3,PACA_EXSLB+EX_R3(r13)
749 ld r3,PACALPPACAPTR(r13)
750 ld r3,LPPACASRR0(r3) /* get SRR0 value */
751 std r9,PACA_EXSLB+EX_R9(r13)
752 mfcr r9
753 #ifdef __DISABLED__
754 cmpdi r3,0
755 bge .slb_miss_user_iseries
756 #endif
757 std r10,PACA_EXSLB+EX_R10(r13)
758 std r11,PACA_EXSLB+EX_R11(r13)
759 std r12,PACA_EXSLB+EX_R12(r13)
760 mfspr r10,SPRN_SPRG1
761 std r10,PACA_EXSLB+EX_R13(r13)
762 ld r12,PACALPPACAPTR(r13)
763 ld r12,LPPACASRR1(r12)
764 b .slb_miss_realmode
765
766 #ifdef __DISABLED__
767 slb_miss_user_iseries:
768 std r10,PACA_EXGEN+EX_R10(r13)
769 std r11,PACA_EXGEN+EX_R11(r13)
770 std r12,PACA_EXGEN+EX_R12(r13)
771 mfspr r10,SPRG1
772 ld r11,PACA_EXSLB+EX_R9(r13)
773 ld r12,PACA_EXSLB+EX_R3(r13)
774 std r10,PACA_EXGEN+EX_R13(r13)
775 std r11,PACA_EXGEN+EX_R9(r13)
776 std r12,PACA_EXGEN+EX_R3(r13)
777 EXCEPTION_PROLOG_ISERIES_2
778 b slb_miss_user_common
779 #endif
780
781 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
782 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
783 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
784 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
785 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
786 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
787 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
788
789 .globl system_call_iSeries
790 system_call_iSeries:
791 mr r9,r13
792 mfspr r13,SPRN_SPRG3
793 EXCEPTION_PROLOG_ISERIES_2
794 b system_call_common
795
796 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
797 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
798 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
799
800 .globl system_reset_iSeries
801 system_reset_iSeries:
802 mfspr r13,SPRN_SPRG3 /* Get paca address */
803 mfmsr r24
804 ori r24,r24,MSR_RI
805 mtmsrd r24 /* RI on */
806 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
807 cmpwi 0,r24,0 /* Are we processor 0? */
808 beq .__start_initialization_iSeries /* Start up the first processor */
809 mfspr r4,SPRN_CTRLF
810 li r5,CTRL_RUNLATCH /* Turn off the run light */
811 andc r4,r4,r5
812 mtspr SPRN_CTRLT,r4
813
814 1:
815 HMT_LOW
816 #ifdef CONFIG_SMP
817 lbz r23,PACAPROCSTART(r13) /* Test if this processor
818 * should start */
819 sync
820 LOAD_REG_IMMEDIATE(r3,current_set)
821 sldi r28,r24,3 /* get current_set[cpu#] */
822 ldx r3,r3,r28
823 addi r1,r3,THREAD_SIZE
824 subi r1,r1,STACK_FRAME_OVERHEAD
825
826 cmpwi 0,r23,0
827 beq iSeries_secondary_smp_loop /* Loop until told to go */
828 bne .__secondary_start /* Loop until told to go */
829 iSeries_secondary_smp_loop:
830 /* Let the Hypervisor know we are alive */
831 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
832 lis r3,0x8002
833 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
834 #else /* CONFIG_SMP */
835 /* Yield the processor. This is required for non-SMP kernels
836 which are running on multi-threaded machines. */
837 lis r3,0x8000
838 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
839 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
840 li r4,0 /* "yield timed" */
841 li r5,-1 /* "yield forever" */
842 #endif /* CONFIG_SMP */
843 li r0,-1 /* r0=-1 indicates a Hypervisor call */
844 sc /* Invoke the hypervisor via a system call */
845 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
846 b 1b /* If SMP not configured, secondaries
847 * loop forever */
848
849 .globl decrementer_iSeries_masked
850 decrementer_iSeries_masked:
851 /* We may not have a valid TOC pointer in here. */
852 li r11,1
853 ld r12,PACALPPACAPTR(r13)
854 stb r11,LPPACADECRINT(r12)
855 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
856 lwz r12,0(r12)
857 mtspr SPRN_DEC,r12
858 /* fall through */
859
860 .globl hardware_interrupt_iSeries_masked
861 hardware_interrupt_iSeries_masked:
862 mtcrf 0x80,r9 /* Restore regs */
863 ld r12,PACALPPACAPTR(r13)
864 ld r11,LPPACASRR0(r12)
865 ld r12,LPPACASRR1(r12)
866 mtspr SPRN_SRR0,r11
867 mtspr SPRN_SRR1,r12
868 ld r9,PACA_EXGEN+EX_R9(r13)
869 ld r10,PACA_EXGEN+EX_R10(r13)
870 ld r11,PACA_EXGEN+EX_R11(r13)
871 ld r12,PACA_EXGEN+EX_R12(r13)
872 ld r13,PACA_EXGEN+EX_R13(r13)
873 rfid
874 b . /* prevent speculative execution */
875 #endif /* CONFIG_PPC_ISERIES */
876
877 /*** Common interrupt handlers ***/
878
879 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
880
881 /*
882 * Machine check is different because we use a different
883 * save area: PACA_EXMC instead of PACA_EXGEN.
884 */
885 .align 7
886 .globl machine_check_common
887 machine_check_common:
888 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
889 FINISH_NAP
890 DISABLE_INTS
891 bl .save_nvgprs
892 addi r3,r1,STACK_FRAME_OVERHEAD
893 bl .machine_check_exception
894 b .ret_from_except
895
896 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
897 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
898 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
899 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
900 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
901 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
902 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
903 #ifdef CONFIG_ALTIVEC
904 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
905 #else
906 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
907 #endif
908 #ifdef CONFIG_CBE_RAS
909 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
910 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
911 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
912 #endif /* CONFIG_CBE_RAS */
913
914 /*
915 * Here we have detected that the kernel stack pointer is bad.
916 * R9 contains the saved CR, r13 points to the paca,
917 * r10 contains the (bad) kernel stack pointer,
918 * r11 and r12 contain the saved SRR0 and SRR1.
919 * We switch to using an emergency stack, save the registers there,
920 * and call kernel_bad_stack(), which panics.
921 */
922 bad_stack:
923 ld r1,PACAEMERGSP(r13)
924 subi r1,r1,64+INT_FRAME_SIZE
925 std r9,_CCR(r1)
926 std r10,GPR1(r1)
927 std r11,_NIP(r1)
928 std r12,_MSR(r1)
929 mfspr r11,SPRN_DAR
930 mfspr r12,SPRN_DSISR
931 std r11,_DAR(r1)
932 std r12,_DSISR(r1)
933 mflr r10
934 mfctr r11
935 mfxer r12
936 std r10,_LINK(r1)
937 std r11,_CTR(r1)
938 std r12,_XER(r1)
939 SAVE_GPR(0,r1)
940 SAVE_GPR(2,r1)
941 SAVE_4GPRS(3,r1)
942 SAVE_2GPRS(7,r1)
943 SAVE_10GPRS(12,r1)
944 SAVE_10GPRS(22,r1)
945 addi r11,r1,INT_FRAME_SIZE
946 std r11,0(r1)
947 li r12,0
948 std r12,0(r11)
949 ld r2,PACATOC(r13)
950 1: addi r3,r1,STACK_FRAME_OVERHEAD
951 bl .kernel_bad_stack
952 b 1b
953
954 /*
955 * Return from an exception with minimal checks.
956 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
957 * If interrupts have been enabled, or anything has been
958 * done that might have changed the scheduling status of
959 * any task or sent any task a signal, you should use
960 * ret_from_except or ret_from_except_lite instead of this.
961 */
962 fast_exc_return_irq: /* restores irq state too */
963 ld r3,SOFTE(r1)
964 ld r12,_MSR(r1)
965 stb r3,PACASOFTIRQEN(r13) /* restore paca->soft_enabled */
966 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
967 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
968 b 1f
969
970 .globl fast_exception_return
971 fast_exception_return:
972 ld r12,_MSR(r1)
973 1: ld r11,_NIP(r1)
974 andi. r3,r12,MSR_RI /* check if RI is set */
975 beq- unrecov_fer
976
977 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
978 andi. r3,r12,MSR_PR
979 beq 2f
980 ACCOUNT_CPU_USER_EXIT(r3, r4)
981 2:
982 #endif
983
984 ld r3,_CCR(r1)
985 ld r4,_LINK(r1)
986 ld r5,_CTR(r1)
987 ld r6,_XER(r1)
988 mtcr r3
989 mtlr r4
990 mtctr r5
991 mtxer r6
992 REST_GPR(0, r1)
993 REST_8GPRS(2, r1)
994
995 mfmsr r10
996 rldicl r10,r10,48,1 /* clear EE */
997 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
998 mtmsrd r10,1
999
1000 mtspr SPRN_SRR1,r12
1001 mtspr SPRN_SRR0,r11
1002 REST_4GPRS(10, r1)
1003 ld r1,GPR1(r1)
1004 rfid
1005 b . /* prevent speculative execution */
1006
1007 unrecov_fer:
1008 bl .save_nvgprs
1009 1: addi r3,r1,STACK_FRAME_OVERHEAD
1010 bl .unrecoverable_exception
1011 b 1b
1012
1013 /*
1014 * Here r13 points to the paca, r9 contains the saved CR,
1015 * SRR0 and SRR1 are saved in r11 and r12,
1016 * r9 - r13 are saved in paca->exgen.
1017 */
1018 .align 7
1019 .globl data_access_common
1020 data_access_common:
1021 mfspr r10,SPRN_DAR
1022 std r10,PACA_EXGEN+EX_DAR(r13)
1023 mfspr r10,SPRN_DSISR
1024 stw r10,PACA_EXGEN+EX_DSISR(r13)
1025 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
1026 ld r3,PACA_EXGEN+EX_DAR(r13)
1027 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1028 li r5,0x300
1029 b .do_hash_page /* Try to handle as hpte fault */
1030
1031 .align 7
1032 .globl instruction_access_common
1033 instruction_access_common:
1034 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
1035 ld r3,_NIP(r1)
1036 andis. r4,r12,0x5820
1037 li r5,0x400
1038 b .do_hash_page /* Try to handle as hpte fault */
1039
1040 /*
1041 * Here is the common SLB miss user that is used when going to virtual
1042 * mode for SLB misses, that is currently not used
1043 */
1044 #ifdef __DISABLED__
1045 .align 7
1046 .globl slb_miss_user_common
1047 slb_miss_user_common:
1048 mflr r10
1049 std r3,PACA_EXGEN+EX_DAR(r13)
1050 stw r9,PACA_EXGEN+EX_CCR(r13)
1051 std r10,PACA_EXGEN+EX_LR(r13)
1052 std r11,PACA_EXGEN+EX_SRR0(r13)
1053 bl .slb_allocate_user
1054
1055 ld r10,PACA_EXGEN+EX_LR(r13)
1056 ld r3,PACA_EXGEN+EX_R3(r13)
1057 lwz r9,PACA_EXGEN+EX_CCR(r13)
1058 ld r11,PACA_EXGEN+EX_SRR0(r13)
1059 mtlr r10
1060 beq- slb_miss_fault
1061
1062 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1063 beq- unrecov_user_slb
1064 mfmsr r10
1065
1066 .machine push
1067 .machine "power4"
1068 mtcrf 0x80,r9
1069 .machine pop
1070
1071 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
1072 mtmsrd r10,1
1073
1074 mtspr SRR0,r11
1075 mtspr SRR1,r12
1076
1077 ld r9,PACA_EXGEN+EX_R9(r13)
1078 ld r10,PACA_EXGEN+EX_R10(r13)
1079 ld r11,PACA_EXGEN+EX_R11(r13)
1080 ld r12,PACA_EXGEN+EX_R12(r13)
1081 ld r13,PACA_EXGEN+EX_R13(r13)
1082 rfid
1083 b .
1084
1085 slb_miss_fault:
1086 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1087 ld r4,PACA_EXGEN+EX_DAR(r13)
1088 li r5,0
1089 std r4,_DAR(r1)
1090 std r5,_DSISR(r1)
1091 b .handle_page_fault
1092
1093 unrecov_user_slb:
1094 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1095 DISABLE_INTS
1096 bl .save_nvgprs
1097 1: addi r3,r1,STACK_FRAME_OVERHEAD
1098 bl .unrecoverable_exception
1099 b 1b
1100
1101 #endif /* __DISABLED__ */
1102
1103
1104 /*
1105 * r13 points to the PACA, r9 contains the saved CR,
1106 * r12 contain the saved SRR1, SRR0 is still ready for return
1107 * r3 has the faulting address
1108 * r9 - r13 are saved in paca->exslb.
1109 * r3 is saved in paca->slb_r3
1110 * We assume we aren't going to take any exceptions during this procedure.
1111 */
1112 _GLOBAL(slb_miss_realmode)
1113 mflr r10
1114
1115 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1116 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1117
1118 bl .slb_allocate_realmode
1119
1120 /* All done -- return from exception. */
1121
1122 ld r10,PACA_EXSLB+EX_LR(r13)
1123 ld r3,PACA_EXSLB+EX_R3(r13)
1124 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1125 #ifdef CONFIG_PPC_ISERIES
1126 BEGIN_FW_FTR_SECTION
1127 ld r11,PACALPPACAPTR(r13)
1128 ld r11,LPPACASRR0(r11) /* get SRR0 value */
1129 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1130 #endif /* CONFIG_PPC_ISERIES */
1131
1132 mtlr r10
1133
1134 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1135 beq- unrecov_slb
1136
1137 .machine push
1138 .machine "power4"
1139 mtcrf 0x80,r9
1140 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1141 .machine pop
1142
1143 #ifdef CONFIG_PPC_ISERIES
1144 BEGIN_FW_FTR_SECTION
1145 mtspr SPRN_SRR0,r11
1146 mtspr SPRN_SRR1,r12
1147 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1148 #endif /* CONFIG_PPC_ISERIES */
1149 ld r9,PACA_EXSLB+EX_R9(r13)
1150 ld r10,PACA_EXSLB+EX_R10(r13)
1151 ld r11,PACA_EXSLB+EX_R11(r13)
1152 ld r12,PACA_EXSLB+EX_R12(r13)
1153 ld r13,PACA_EXSLB+EX_R13(r13)
1154 rfid
1155 b . /* prevent speculative execution */
1156
1157 unrecov_slb:
1158 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1159 DISABLE_INTS
1160 bl .save_nvgprs
1161 1: addi r3,r1,STACK_FRAME_OVERHEAD
1162 bl .unrecoverable_exception
1163 b 1b
1164
1165 .align 7
1166 .globl hardware_interrupt_common
1167 .globl hardware_interrupt_entry
1168 hardware_interrupt_common:
1169 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1170 FINISH_NAP
1171 hardware_interrupt_entry:
1172 DISABLE_INTS
1173 bl .ppc64_runlatch_on
1174 addi r3,r1,STACK_FRAME_OVERHEAD
1175 bl .do_IRQ
1176 b .ret_from_except_lite
1177
1178 #ifdef CONFIG_PPC_970_NAP
1179 power4_fixup_nap:
1180 andc r9,r9,r10
1181 std r9,TI_LOCAL_FLAGS(r11)
1182 ld r10,_LINK(r1) /* make idle task do the */
1183 std r10,_NIP(r1) /* equivalent of a blr */
1184 blr
1185 #endif
1186
1187 .align 7
1188 .globl alignment_common
1189 alignment_common:
1190 mfspr r10,SPRN_DAR
1191 std r10,PACA_EXGEN+EX_DAR(r13)
1192 mfspr r10,SPRN_DSISR
1193 stw r10,PACA_EXGEN+EX_DSISR(r13)
1194 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1195 ld r3,PACA_EXGEN+EX_DAR(r13)
1196 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1197 std r3,_DAR(r1)
1198 std r4,_DSISR(r1)
1199 bl .save_nvgprs
1200 addi r3,r1,STACK_FRAME_OVERHEAD
1201 ENABLE_INTS
1202 bl .alignment_exception
1203 b .ret_from_except
1204
1205 .align 7
1206 .globl program_check_common
1207 program_check_common:
1208 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1209 bl .save_nvgprs
1210 addi r3,r1,STACK_FRAME_OVERHEAD
1211 ENABLE_INTS
1212 bl .program_check_exception
1213 b .ret_from_except
1214
1215 .align 7
1216 .globl fp_unavailable_common
1217 fp_unavailable_common:
1218 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1219 bne .load_up_fpu /* if from user, just load it up */
1220 bl .save_nvgprs
1221 addi r3,r1,STACK_FRAME_OVERHEAD
1222 ENABLE_INTS
1223 bl .kernel_fp_unavailable_exception
1224 BUG_OPCODE
1225
1226 .align 7
1227 .globl altivec_unavailable_common
1228 altivec_unavailable_common:
1229 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1230 #ifdef CONFIG_ALTIVEC
1231 BEGIN_FTR_SECTION
1232 bne .load_up_altivec /* if from user, just load it up */
1233 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1234 #endif
1235 bl .save_nvgprs
1236 addi r3,r1,STACK_FRAME_OVERHEAD
1237 ENABLE_INTS
1238 bl .altivec_unavailable_exception
1239 b .ret_from_except
1240
1241 #ifdef CONFIG_ALTIVEC
1242 /*
1243 * load_up_altivec(unused, unused, tsk)
1244 * Disable VMX for the task which had it previously,
1245 * and save its vector registers in its thread_struct.
1246 * Enables the VMX for use in the kernel on return.
1247 * On SMP we know the VMX is free, since we give it up every
1248 * switch (ie, no lazy save of the vector registers).
1249 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1250 */
1251 _STATIC(load_up_altivec)
1252 mfmsr r5 /* grab the current MSR */
1253 oris r5,r5,MSR_VEC@h
1254 mtmsrd r5 /* enable use of VMX now */
1255 isync
1256
1257 /*
1258 * For SMP, we don't do lazy VMX switching because it just gets too
1259 * horrendously complex, especially when a task switches from one CPU
1260 * to another. Instead we call giveup_altvec in switch_to.
1261 * VRSAVE isn't dealt with here, that is done in the normal context
1262 * switch code. Note that we could rely on vrsave value to eventually
1263 * avoid saving all of the VREGs here...
1264 */
1265 #ifndef CONFIG_SMP
1266 ld r3,last_task_used_altivec@got(r2)
1267 ld r4,0(r3)
1268 cmpdi 0,r4,0
1269 beq 1f
1270 /* Save VMX state to last_task_used_altivec's THREAD struct */
1271 addi r4,r4,THREAD
1272 SAVE_32VRS(0,r5,r4)
1273 mfvscr vr0
1274 li r10,THREAD_VSCR
1275 stvx vr0,r10,r4
1276 /* Disable VMX for last_task_used_altivec */
1277 ld r5,PT_REGS(r4)
1278 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1279 lis r6,MSR_VEC@h
1280 andc r4,r4,r6
1281 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1282 1:
1283 #endif /* CONFIG_SMP */
1284 /* Hack: if we get an altivec unavailable trap with VRSAVE
1285 * set to all zeros, we assume this is a broken application
1286 * that fails to set it properly, and thus we switch it to
1287 * all 1's
1288 */
1289 mfspr r4,SPRN_VRSAVE
1290 cmpdi 0,r4,0
1291 bne+ 1f
1292 li r4,-1
1293 mtspr SPRN_VRSAVE,r4
1294 1:
1295 /* enable use of VMX after return */
1296 ld r4,PACACURRENT(r13)
1297 addi r5,r4,THREAD /* Get THREAD */
1298 oris r12,r12,MSR_VEC@h
1299 std r12,_MSR(r1)
1300 li r4,1
1301 li r10,THREAD_VSCR
1302 stw r4,THREAD_USED_VR(r5)
1303 lvx vr0,r10,r5
1304 mtvscr vr0
1305 REST_32VRS(0,r4,r5)
1306 #ifndef CONFIG_SMP
1307 /* Update last_task_used_math to 'current' */
1308 subi r4,r5,THREAD /* Back to 'current' */
1309 std r4,0(r3)
1310 #endif /* CONFIG_SMP */
1311 /* restore registers and return */
1312 b fast_exception_return
1313 #endif /* CONFIG_ALTIVEC */
1314
1315 /*
1316 * Hash table stuff
1317 */
1318 .align 7
1319 _GLOBAL(do_hash_page)
1320 std r3,_DAR(r1)
1321 std r4,_DSISR(r1)
1322
1323 andis. r0,r4,0xa450 /* weird error? */
1324 bne- .handle_page_fault /* if not, try to insert a HPTE */
1325 BEGIN_FTR_SECTION
1326 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1327 bne- .do_ste_alloc /* If so handle it */
1328 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1329
1330 /*
1331 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1332 * accessing a userspace segment (even from the kernel). We assume
1333 * kernel addresses always have the high bit set.
1334 */
1335 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1336 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1337 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1338 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1339 ori r4,r4,1 /* add _PAGE_PRESENT */
1340 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1341
1342 /*
1343 * On iSeries, we soft-disable interrupts here, then
1344 * hard-enable interrupts so that the hash_page code can spin on
1345 * the hash_table_lock without problems on a shared processor.
1346 */
1347 DISABLE_INTS
1348
1349 /*
1350 * r3 contains the faulting address
1351 * r4 contains the required access permissions
1352 * r5 contains the trap number
1353 *
1354 * at return r3 = 0 for success
1355 */
1356 bl .hash_page /* build HPTE if possible */
1357 cmpdi r3,0 /* see if hash_page succeeded */
1358
1359 #ifdef DO_SOFT_DISABLE
1360 BEGIN_FW_FTR_SECTION
1361 /*
1362 * If we had interrupts soft-enabled at the point where the
1363 * DSI/ISI occurred, and an interrupt came in during hash_page,
1364 * handle it now.
1365 * We jump to ret_from_except_lite rather than fast_exception_return
1366 * because ret_from_except_lite will check for and handle pending
1367 * interrupts if necessary.
1368 */
1369 beq .ret_from_except_lite
1370 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1371 #endif
1372 BEGIN_FW_FTR_SECTION
1373 /*
1374 * Here we have interrupts hard-disabled, so it is sufficient
1375 * to restore paca->{soft,hard}_enable and get out.
1376 */
1377 beq fast_exc_return_irq /* Return from exception on success */
1378 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1379
1380 /* For a hash failure, we don't bother re-enabling interrupts */
1381 ble- 12f
1382
1383 /*
1384 * hash_page couldn't handle it, set soft interrupt enable back
1385 * to what it was before the trap. Note that .local_irq_restore
1386 * handles any interrupts pending at this point.
1387 */
1388 ld r3,SOFTE(r1)
1389 bl .local_irq_restore
1390 b 11f
1391
1392 /* Here we have a page fault that hash_page can't handle. */
1393 _GLOBAL(handle_page_fault)
1394 ENABLE_INTS
1395 11: ld r4,_DAR(r1)
1396 ld r5,_DSISR(r1)
1397 addi r3,r1,STACK_FRAME_OVERHEAD
1398 bl .do_page_fault
1399 cmpdi r3,0
1400 beq+ .ret_from_except_lite
1401 bl .save_nvgprs
1402 mr r5,r3
1403 addi r3,r1,STACK_FRAME_OVERHEAD
1404 lwz r4,_DAR(r1)
1405 bl .bad_page_fault
1406 b .ret_from_except
1407
1408 /* We have a page fault that hash_page could handle but HV refused
1409 * the PTE insertion
1410 */
1411 12: bl .save_nvgprs
1412 addi r3,r1,STACK_FRAME_OVERHEAD
1413 lwz r4,_DAR(r1)
1414 bl .low_hash_fault
1415 b .ret_from_except
1416
1417 /* here we have a segment miss */
1418 _GLOBAL(do_ste_alloc)
1419 bl .ste_allocate /* try to insert stab entry */
1420 cmpdi r3,0
1421 beq+ fast_exception_return
1422 b .handle_page_fault
1423
1424 /*
1425 * r13 points to the PACA, r9 contains the saved CR,
1426 * r11 and r12 contain the saved SRR0 and SRR1.
1427 * r9 - r13 are saved in paca->exslb.
1428 * We assume we aren't going to take any exceptions during this procedure.
1429 * We assume (DAR >> 60) == 0xc.
1430 */
1431 .align 7
1432 _GLOBAL(do_stab_bolted)
1433 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1434 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1435
1436 /* Hash to the primary group */
1437 ld r10,PACASTABVIRT(r13)
1438 mfspr r11,SPRN_DAR
1439 srdi r11,r11,28
1440 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1441
1442 /* Calculate VSID */
1443 /* This is a kernel address, so protovsid = ESID */
1444 ASM_VSID_SCRAMBLE(r11, r9)
1445 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1446
1447 /* Search the primary group for a free entry */
1448 1: ld r11,0(r10) /* Test valid bit of the current ste */
1449 andi. r11,r11,0x80
1450 beq 2f
1451 addi r10,r10,16
1452 andi. r11,r10,0x70
1453 bne 1b
1454
1455 /* Stick for only searching the primary group for now. */
1456 /* At least for now, we use a very simple random castout scheme */
1457 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1458 mftb r11
1459 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1460 ori r11,r11,0x10
1461
1462 /* r10 currently points to an ste one past the group of interest */
1463 /* make it point to the randomly selected entry */
1464 subi r10,r10,128
1465 or r10,r10,r11 /* r10 is the entry to invalidate */
1466
1467 isync /* mark the entry invalid */
1468 ld r11,0(r10)
1469 rldicl r11,r11,56,1 /* clear the valid bit */
1470 rotldi r11,r11,8
1471 std r11,0(r10)
1472 sync
1473
1474 clrrdi r11,r11,28 /* Get the esid part of the ste */
1475 slbie r11
1476
1477 2: std r9,8(r10) /* Store the vsid part of the ste */
1478 eieio
1479
1480 mfspr r11,SPRN_DAR /* Get the new esid */
1481 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1482 ori r11,r11,0x90 /* Turn on valid and kp */
1483 std r11,0(r10) /* Put new entry back into the stab */
1484
1485 sync
1486
1487 /* All done -- return from exception. */
1488 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1489 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1490
1491 andi. r10,r12,MSR_RI
1492 beq- unrecov_slb
1493
1494 mtcrf 0x80,r9 /* restore CR */
1495
1496 mfmsr r10
1497 clrrdi r10,r10,2
1498 mtmsrd r10,1
1499
1500 mtspr SPRN_SRR0,r11
1501 mtspr SPRN_SRR1,r12
1502 ld r9,PACA_EXSLB+EX_R9(r13)
1503 ld r10,PACA_EXSLB+EX_R10(r13)
1504 ld r11,PACA_EXSLB+EX_R11(r13)
1505 ld r12,PACA_EXSLB+EX_R12(r13)
1506 ld r13,PACA_EXSLB+EX_R13(r13)
1507 rfid
1508 b . /* prevent speculative execution */
1509
1510 /*
1511 * Space for CPU0's segment table.
1512 *
1513 * On iSeries, the hypervisor must fill in at least one entry before
1514 * we get control (with relocate on). The address is give to the hv
1515 * as a page number (see xLparMap in lpardata.c), so this must be at a
1516 * fixed address (the linker can't compute (u64)&initial_stab >>
1517 * PAGE_SHIFT).
1518 */
1519 . = STAB0_OFFSET /* 0x6000 */
1520 .globl initial_stab
1521 initial_stab:
1522 .space 4096
1523
1524 /*
1525 * Data area reserved for FWNMI option.
1526 * This address (0x7000) is fixed by the RPA.
1527 */
1528 .= 0x7000
1529 .globl fwnmi_data_area
1530 fwnmi_data_area:
1531
1532 /* iSeries does not use the FWNMI stuff, so it is safe to put
1533 * this here, even if we later allow kernels that will boot on
1534 * both pSeries and iSeries */
1535 #ifdef CONFIG_PPC_ISERIES
1536 . = LPARMAP_PHYS
1537 #include "lparmap.s"
1538 /*
1539 * This ".text" is here for old compilers that generate a trailing
1540 * .note section when compiling .c files to .s
1541 */
1542 .text
1543 #endif /* CONFIG_PPC_ISERIES */
1544
1545 . = 0x8000
1546
1547 /*
1548 * On pSeries and most other platforms, secondary processors spin
1549 * in the following code.
1550 * At entry, r3 = this processor's number (physical cpu id)
1551 */
1552 _GLOBAL(generic_secondary_smp_init)
1553 mr r24,r3
1554
1555 /* turn on 64-bit mode */
1556 bl .enable_64b_mode
1557 isync
1558
1559 /* Set up a paca value for this processor. Since we have the
1560 * physical cpu id in r24, we need to search the pacas to find
1561 * which logical id maps to our physical one.
1562 */
1563 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1564 li r5,0 /* logical cpu id */
1565 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1566 cmpw r6,r24 /* Compare to our id */
1567 beq 2f
1568 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1569 addi r5,r5,1
1570 cmpwi r5,NR_CPUS
1571 blt 1b
1572
1573 mr r3,r24 /* not found, copy phys to r3 */
1574 b .kexec_wait /* next kernel might do better */
1575
1576 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1577 /* From now on, r24 is expected to be logical cpuid */
1578 mr r24,r5
1579 3: HMT_LOW
1580 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1581 /* start. */
1582 sync
1583
1584 #ifndef CONFIG_SMP
1585 b 3b /* Never go on non-SMP */
1586 #else
1587 cmpwi 0,r23,0
1588 beq 3b /* Loop until told to go */
1589
1590 /* See if we need to call a cpu state restore handler */
1591 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1592 ld r23,0(r23)
1593 ld r23,CPU_SPEC_RESTORE(r23)
1594 cmpdi 0,r23,0
1595 beq 4f
1596 ld r23,0(r23)
1597 mtctr r23
1598 bctrl
1599
1600 4: /* Create a temp kernel stack for use before relocation is on. */
1601 ld r1,PACAEMERGSP(r13)
1602 subi r1,r1,STACK_FRAME_OVERHEAD
1603
1604 b .__secondary_start
1605 #endif
1606
1607 #ifdef CONFIG_PPC_ISERIES
1608 _STATIC(__start_initialization_iSeries)
1609 /* Clear out the BSS */
1610 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1611 LOAD_REG_IMMEDIATE(r8,__bss_start)
1612 sub r11,r11,r8 /* bss size */
1613 addi r11,r11,7 /* round up to an even double word */
1614 rldicl. r11,r11,61,3 /* shift right by 3 */
1615 beq 4f
1616 addi r8,r8,-8
1617 li r0,0
1618 mtctr r11 /* zero this many doublewords */
1619 3: stdu r0,8(r8)
1620 bdnz 3b
1621 4:
1622 LOAD_REG_IMMEDIATE(r1,init_thread_union)
1623 addi r1,r1,THREAD_SIZE
1624 li r0,0
1625 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1626
1627 LOAD_REG_IMMEDIATE(r3,cpu_specs)
1628 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1629 li r5,0
1630 bl .identify_cpu
1631
1632 LOAD_REG_IMMEDIATE(r2,__toc_start)
1633 addi r2,r2,0x4000
1634 addi r2,r2,0x4000
1635
1636 bl .iSeries_early_setup
1637 bl .early_setup
1638
1639 /* relocation is on at this point */
1640
1641 b .start_here_common
1642 #endif /* CONFIG_PPC_ISERIES */
1643
1644
1645 _STATIC(__mmu_off)
1646 mfmsr r3
1647 andi. r0,r3,MSR_IR|MSR_DR
1648 beqlr
1649 andc r3,r3,r0
1650 mtspr SPRN_SRR0,r4
1651 mtspr SPRN_SRR1,r3
1652 sync
1653 rfid
1654 b . /* prevent speculative execution */
1655
1656
1657 /*
1658 * Here is our main kernel entry point. We support currently 2 kind of entries
1659 * depending on the value of r5.
1660 *
1661 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1662 * in r3...r7
1663 *
1664 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1665 * DT block, r4 is a physical pointer to the kernel itself
1666 *
1667 */
1668 _GLOBAL(__start_initialization_multiplatform)
1669 /*
1670 * Are we booted from a PROM Of-type client-interface ?
1671 */
1672 cmpldi cr0,r5,0
1673 bne .__boot_from_prom /* yes -> prom */
1674
1675 /* Save parameters */
1676 mr r31,r3
1677 mr r30,r4
1678
1679 /* Make sure we are running in 64 bits mode */
1680 bl .enable_64b_mode
1681
1682 /* Setup some critical 970 SPRs before switching MMU off */
1683 mfspr r0,SPRN_PVR
1684 srwi r0,r0,16
1685 cmpwi r0,0x39 /* 970 */
1686 beq 1f
1687 cmpwi r0,0x3c /* 970FX */
1688 beq 1f
1689 cmpwi r0,0x44 /* 970MP */
1690 bne 2f
1691 1: bl .__cpu_preinit_ppc970
1692 2:
1693
1694 /* Switch off MMU if not already */
1695 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1696 add r4,r4,r30
1697 bl .__mmu_off
1698 b .__after_prom_start
1699
1700 _STATIC(__boot_from_prom)
1701 /* Save parameters */
1702 mr r31,r3
1703 mr r30,r4
1704 mr r29,r5
1705 mr r28,r6
1706 mr r27,r7
1707
1708 /*
1709 * Align the stack to 16-byte boundary
1710 * Depending on the size and layout of the ELF sections in the initial
1711 * boot binary, the stack pointer will be unalignet on PowerMac
1712 */
1713 rldicr r1,r1,0,59
1714
1715 /* Make sure we are running in 64 bits mode */
1716 bl .enable_64b_mode
1717
1718 /* put a relocation offset into r3 */
1719 bl .reloc_offset
1720
1721 LOAD_REG_IMMEDIATE(r2,__toc_start)
1722 addi r2,r2,0x4000
1723 addi r2,r2,0x4000
1724
1725 /* Relocate the TOC from a virt addr to a real addr */
1726 add r2,r2,r3
1727
1728 /* Restore parameters */
1729 mr r3,r31
1730 mr r4,r30
1731 mr r5,r29
1732 mr r6,r28
1733 mr r7,r27
1734
1735 /* Do all of the interaction with OF client interface */
1736 bl .prom_init
1737 /* We never return */
1738 trap
1739
1740 /*
1741 * At this point, r3 contains the physical address we are running at,
1742 * returned by prom_init()
1743 */
1744 _STATIC(__after_prom_start)
1745
1746 /*
1747 * We need to run with __start at physical address PHYSICAL_START.
1748 * This will leave some code in the first 256B of
1749 * real memory, which are reserved for software use.
1750 * The remainder of the first page is loaded with the fixed
1751 * interrupt vectors. The next two pages are filled with
1752 * unknown exception placeholders.
1753 *
1754 * Note: This process overwrites the OF exception vectors.
1755 * r26 == relocation offset
1756 * r27 == KERNELBASE
1757 */
1758 bl .reloc_offset
1759 mr r26,r3
1760 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1761
1762 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1763
1764 // XXX FIXME: Use phys returned by OF (r30)
1765 add r4,r27,r26 /* source addr */
1766 /* current address of _start */
1767 /* i.e. where we are running */
1768 /* the source addr */
1769
1770 cmpdi r4,0 /* In some cases the loader may */
1771 beq .start_here_multiplatform /* have already put us at zero */
1772 /* so we can skip the copy. */
1773 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1774 sub r5,r5,r27
1775
1776 li r6,0x100 /* Start offset, the first 0x100 */
1777 /* bytes were copied earlier. */
1778
1779 bl .copy_and_flush /* copy the first n bytes */
1780 /* this includes the code being */
1781 /* executed here. */
1782
1783 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1784 mtctr r0 /* that we just made/relocated */
1785 bctr
1786
1787 4: LOAD_REG_IMMEDIATE(r5,klimit)
1788 add r5,r5,r26
1789 ld r5,0(r5) /* get the value of klimit */
1790 sub r5,r5,r27
1791 bl .copy_and_flush /* copy the rest */
1792 b .start_here_multiplatform
1793
1794 /*
1795 * Copy routine used to copy the kernel to start at physical address 0
1796 * and flush and invalidate the caches as needed.
1797 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1798 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1799 *
1800 * Note: this routine *only* clobbers r0, r6 and lr
1801 */
1802 _GLOBAL(copy_and_flush)
1803 addi r5,r5,-8
1804 addi r6,r6,-8
1805 4: li r0,8 /* Use the smallest common */
1806 /* denominator cache line */
1807 /* size. This results in */
1808 /* extra cache line flushes */
1809 /* but operation is correct. */
1810 /* Can't get cache line size */
1811 /* from NACA as it is being */
1812 /* moved too. */
1813
1814 mtctr r0 /* put # words/line in ctr */
1815 3: addi r6,r6,8 /* copy a cache line */
1816 ldx r0,r6,r4
1817 stdx r0,r6,r3
1818 bdnz 3b
1819 dcbst r6,r3 /* write it to memory */
1820 sync
1821 icbi r6,r3 /* flush the icache line */
1822 cmpld 0,r6,r5
1823 blt 4b
1824 sync
1825 addi r5,r5,8
1826 addi r6,r6,8
1827 blr
1828
1829 .align 8
1830 copy_to_here:
1831
1832 #ifdef CONFIG_SMP
1833 #ifdef CONFIG_PPC_PMAC
1834 /*
1835 * On PowerMac, secondary processors starts from the reset vector, which
1836 * is temporarily turned into a call to one of the functions below.
1837 */
1838 .section ".text";
1839 .align 2 ;
1840
1841 .globl __secondary_start_pmac_0
1842 __secondary_start_pmac_0:
1843 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1844 li r24,0
1845 b 1f
1846 li r24,1
1847 b 1f
1848 li r24,2
1849 b 1f
1850 li r24,3
1851 1:
1852
1853 _GLOBAL(pmac_secondary_start)
1854 /* turn on 64-bit mode */
1855 bl .enable_64b_mode
1856 isync
1857
1858 /* Copy some CPU settings from CPU 0 */
1859 bl .__restore_cpu_ppc970
1860
1861 /* pSeries do that early though I don't think we really need it */
1862 mfmsr r3
1863 ori r3,r3,MSR_RI
1864 mtmsrd r3 /* RI on */
1865
1866 /* Set up a paca value for this processor. */
1867 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1868 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1869 add r13,r13,r4 /* for this processor. */
1870 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1871
1872 /* Create a temp kernel stack for use before relocation is on. */
1873 ld r1,PACAEMERGSP(r13)
1874 subi r1,r1,STACK_FRAME_OVERHEAD
1875
1876 b .__secondary_start
1877
1878 #endif /* CONFIG_PPC_PMAC */
1879
1880 /*
1881 * This function is called after the master CPU has released the
1882 * secondary processors. The execution environment is relocation off.
1883 * The paca for this processor has the following fields initialized at
1884 * this point:
1885 * 1. Processor number
1886 * 2. Segment table pointer (virtual address)
1887 * On entry the following are set:
1888 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1889 * r24 = cpu# (in Linux terms)
1890 * r13 = paca virtual address
1891 * SPRG3 = paca virtual address
1892 */
1893 _GLOBAL(__secondary_start)
1894 /* Set thread priority to MEDIUM */
1895 HMT_MEDIUM
1896
1897 /* Load TOC */
1898 ld r2,PACATOC(r13)
1899
1900 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1901 bl .early_setup_secondary
1902
1903 /* Initialize the kernel stack. Just a repeat for iSeries. */
1904 LOAD_REG_ADDR(r3, current_set)
1905 sldi r28,r24,3 /* get current_set[cpu#] */
1906 ldx r1,r3,r28
1907 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1908 std r1,PACAKSAVE(r13)
1909
1910 /* Clear backchain so we get nice backtraces */
1911 li r7,0
1912 mtlr r7
1913
1914 /* enable MMU and jump to start_secondary */
1915 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1916 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1917 #ifdef CONFIG_PPC_ISERIES
1918 BEGIN_FW_FTR_SECTION
1919 ori r4,r4,MSR_EE
1920 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1921 #endif
1922 BEGIN_FW_FTR_SECTION
1923 stb r7,PACASOFTIRQEN(r13)
1924 stb r7,PACAHARDIRQEN(r13)
1925 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1926
1927 mtspr SPRN_SRR0,r3
1928 mtspr SPRN_SRR1,r4
1929 rfid
1930 b . /* prevent speculative execution */
1931
1932 /*
1933 * Running with relocation on at this point. All we want to do is
1934 * zero the stack back-chain pointer before going into C code.
1935 */
1936 _GLOBAL(start_secondary_prolog)
1937 li r3,0
1938 std r3,0(r1) /* Zero the stack frame pointer */
1939 bl .start_secondary
1940 b .
1941 #endif
1942
1943 /*
1944 * This subroutine clobbers r11 and r12
1945 */
1946 _GLOBAL(enable_64b_mode)
1947 mfmsr r11 /* grab the current MSR */
1948 li r12,1
1949 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1950 or r11,r11,r12
1951 li r12,1
1952 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1953 or r11,r11,r12
1954 mtmsrd r11
1955 isync
1956 blr
1957
1958 /*
1959 * This is where the main kernel code starts.
1960 */
1961 _STATIC(start_here_multiplatform)
1962 /* get a new offset, now that the kernel has moved. */
1963 bl .reloc_offset
1964 mr r26,r3
1965
1966 /* Clear out the BSS. It may have been done in prom_init,
1967 * already but that's irrelevant since prom_init will soon
1968 * be detached from the kernel completely. Besides, we need
1969 * to clear it now for kexec-style entry.
1970 */
1971 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1972 LOAD_REG_IMMEDIATE(r8,__bss_start)
1973 sub r11,r11,r8 /* bss size */
1974 addi r11,r11,7 /* round up to an even double word */
1975 rldicl. r11,r11,61,3 /* shift right by 3 */
1976 beq 4f
1977 addi r8,r8,-8
1978 li r0,0
1979 mtctr r11 /* zero this many doublewords */
1980 3: stdu r0,8(r8)
1981 bdnz 3b
1982 4:
1983
1984 mfmsr r6
1985 ori r6,r6,MSR_RI
1986 mtmsrd r6 /* RI on */
1987
1988 /* The following gets the stack and TOC set up with the regs */
1989 /* pointing to the real addr of the kernel stack. This is */
1990 /* all done to support the C function call below which sets */
1991 /* up the htab. This is done because we have relocated the */
1992 /* kernel but are still running in real mode. */
1993
1994 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1995 add r3,r3,r26
1996
1997 /* set up a stack pointer (physical address) */
1998 addi r1,r3,THREAD_SIZE
1999 li r0,0
2000 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2001
2002 /* set up the TOC (physical address) */
2003 LOAD_REG_IMMEDIATE(r2,__toc_start)
2004 addi r2,r2,0x4000
2005 addi r2,r2,0x4000
2006 add r2,r2,r26
2007
2008 LOAD_REG_IMMEDIATE(r3, cpu_specs)
2009 add r3,r3,r26
2010 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
2011 add r4,r4,r26
2012 mr r5,r26
2013 bl .identify_cpu
2014
2015 /* Do very early kernel initializations, including initial hash table,
2016 * stab and slb setup before we turn on relocation. */
2017
2018 /* Restore parameters passed from prom_init/kexec */
2019 mr r3,r31
2020 bl .early_setup
2021
2022 LOAD_REG_IMMEDIATE(r3, .start_here_common)
2023 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
2024 mtspr SPRN_SRR0,r3
2025 mtspr SPRN_SRR1,r4
2026 rfid
2027 b . /* prevent speculative execution */
2028
2029 /* This is where all platforms converge execution */
2030 _STATIC(start_here_common)
2031 /* relocation is on at this point */
2032
2033 /* The following code sets up the SP and TOC now that we are */
2034 /* running with translation enabled. */
2035
2036 LOAD_REG_IMMEDIATE(r3,init_thread_union)
2037
2038 /* set up the stack */
2039 addi r1,r3,THREAD_SIZE
2040 li r0,0
2041 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2042
2043 /* Apply the CPUs-specific fixups (nop out sections not relevant
2044 * to this CPU
2045 */
2046 li r3,0
2047 bl .do_cpu_ftr_fixups
2048 bl .do_fw_ftr_fixups
2049
2050 /* ptr to current */
2051 LOAD_REG_IMMEDIATE(r4, init_task)
2052 std r4,PACACURRENT(r13)
2053
2054 /* Load the TOC */
2055 ld r2,PACATOC(r13)
2056 std r1,PACAKSAVE(r13)
2057
2058 bl .setup_system
2059
2060 /* Load up the kernel context */
2061 5:
2062 li r5,0
2063 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
2064 #ifdef CONFIG_PPC_ISERIES
2065 BEGIN_FW_FTR_SECTION
2066 mfmsr r5
2067 ori r5,r5,MSR_EE /* Hard Enabled */
2068 mtmsrd r5
2069 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
2070 #endif
2071 BEGIN_FW_FTR_SECTION
2072 stb r5,PACAHARDIRQEN(r13)
2073 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
2074
2075 bl .start_kernel
2076
2077 /* Not reached */
2078 BUG_OPCODE
2079
2080 /*
2081 * We put a few things here that have to be page-aligned.
2082 * This stuff goes at the beginning of the bss, which is page-aligned.
2083 */
2084 .section ".bss"
2085
2086 .align PAGE_SHIFT
2087
2088 .globl empty_zero_page
2089 empty_zero_page:
2090 .space PAGE_SIZE
2091
2092 .globl swapper_pg_dir
2093 swapper_pg_dir:
2094 .space PAGE_SIZE
2095
2096 /*
2097 * This space gets a copy of optional info passed to us by the bootstrap
2098 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2099 */
2100 .globl cmd_line
2101 cmd_line:
2102 .space COMMAND_LINE_SIZE
Linux kernel - Deliverables
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