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Merge ../scsi-misc-2.6
[deliverable/linux.git] / arch / powerpc / kernel / head_64.S
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23
24 #include <linux/threads.h>
25 #include <asm/reg.h>
26 #include <asm/page.h>
27 #include <asm/mmu.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/bug.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36
37 #ifdef CONFIG_PPC_ISERIES
38 #define DO_SOFT_DISABLE
39 #endif
40
41 /*
42 * We layout physical memory as follows:
43 * 0x0000 - 0x00ff : Secondary processor spin code
44 * 0x0100 - 0x2fff : pSeries Interrupt prologs
45 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
46 * 0x6000 - 0x6fff : Initial (CPU0) segment table
47 * 0x7000 - 0x7fff : FWNMI data area
48 * 0x8000 - : Early init and support code
49 */
50
51 /*
52 * SPRG Usage
53 *
54 * Register Definition
55 *
56 * SPRG0 reserved for hypervisor
57 * SPRG1 temp - used to save gpr
58 * SPRG2 temp - used to save gpr
59 * SPRG3 virt addr of paca
60 */
61
62 /*
63 * Entering into this code we make the following assumptions:
64 * For pSeries:
65 * 1. The MMU is off & open firmware is running in real mode.
66 * 2. The kernel is entered at __start
67 *
68 * For iSeries:
69 * 1. The MMU is on (as it always is for iSeries)
70 * 2. The kernel is entered at system_reset_iSeries
71 */
72
73 .text
74 .globl _stext
75 _stext:
76 #ifdef CONFIG_PPC_MULTIPLATFORM
77 _GLOBAL(__start)
78 /* NOP this out unconditionally */
79 BEGIN_FTR_SECTION
80 b .__start_initialization_multiplatform
81 END_FTR_SECTION(0, 1)
82 #endif /* CONFIG_PPC_MULTIPLATFORM */
83
84 /* Catch branch to 0 in real mode */
85 trap
86
87 /* Secondary processors spin on this value until it goes to 1. */
88 .globl __secondary_hold_spinloop
89 __secondary_hold_spinloop:
90 .llong 0x0
91
92 /* Secondary processors write this value with their cpu # */
93 /* after they enter the spin loop immediately below. */
94 .globl __secondary_hold_acknowledge
95 __secondary_hold_acknowledge:
96 .llong 0x0
97
98 #ifdef CONFIG_PPC_ISERIES
99 /*
100 * At offset 0x20, there is a pointer to iSeries LPAR data.
101 * This is required by the hypervisor
102 */
103 . = 0x20
104 .llong hvReleaseData-KERNELBASE
105 #endif /* CONFIG_PPC_ISERIES */
106
107 . = 0x60
108 /*
109 * The following code is used on pSeries to hold secondary processors
110 * in a spin loop after they have been freed from OpenFirmware, but
111 * before the bulk of the kernel has been relocated. This code
112 * is relocated to physical address 0x60 before prom_init is run.
113 * All of it must fit below the first exception vector at 0x100.
114 */
115 _GLOBAL(__secondary_hold)
116 mfmsr r24
117 ori r24,r24,MSR_RI
118 mtmsrd r24 /* RI on */
119
120 /* Grab our physical cpu number */
121 mr r24,r3
122
123 /* Tell the master cpu we're here */
124 /* Relocation is off & we are located at an address less */
125 /* than 0x100, so only need to grab low order offset. */
126 std r24,__secondary_hold_acknowledge@l(0)
127 sync
128
129 /* All secondary cpus wait here until told to start. */
130 100: ld r4,__secondary_hold_spinloop@l(0)
131 cmpdi 0,r4,1
132 bne 100b
133
134 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
135 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
136 mtctr r4
137 mr r3,r24
138 bctr
139 #else
140 BUG_OPCODE
141 #endif
142
143 /* This value is used to mark exception frames on the stack. */
144 .section ".toc","aw"
145 exception_marker:
146 .tc ID_72656773_68657265[TC],0x7265677368657265
147 .text
148
149 /*
150 * The following macros define the code that appears as
151 * the prologue to each of the exception handlers. They
152 * are split into two parts to allow a single kernel binary
153 * to be used for pSeries and iSeries.
154 * LOL. One day... - paulus
155 */
156
157 /*
158 * We make as much of the exception code common between native
159 * exception handlers (including pSeries LPAR) and iSeries LPAR
160 * implementations as possible.
161 */
162
163 /*
164 * This is the start of the interrupt handlers for pSeries
165 * This code runs with relocation off.
166 */
167 #define EX_R9 0
168 #define EX_R10 8
169 #define EX_R11 16
170 #define EX_R12 24
171 #define EX_R13 32
172 #define EX_SRR0 40
173 #define EX_DAR 48
174 #define EX_DSISR 56
175 #define EX_CCR 60
176 #define EX_R3 64
177 #define EX_LR 72
178
179 /*
180 * We're short on space and time in the exception prolog, so we can't
181 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
182 * low halfword of the address, but for Kdump we need the whole low
183 * word.
184 */
185 #ifdef CONFIG_CRASH_DUMP
186 #define LOAD_HANDLER(reg, label) \
187 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
188 ori reg,reg,(label)@l; /* .. and the rest */
189 #else
190 #define LOAD_HANDLER(reg, label) \
191 ori reg,reg,(label)@l; /* virt addr of handler ... */
192 #endif
193
194 #define EXCEPTION_PROLOG_PSERIES(area, label) \
195 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
196 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
197 std r10,area+EX_R10(r13); \
198 std r11,area+EX_R11(r13); \
199 std r12,area+EX_R12(r13); \
200 mfspr r9,SPRN_SPRG1; \
201 std r9,area+EX_R13(r13); \
202 mfcr r9; \
203 clrrdi r12,r13,32; /* get high part of &label */ \
204 mfmsr r10; \
205 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
206 LOAD_HANDLER(r12,label) \
207 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
208 mtspr SPRN_SRR0,r12; \
209 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
210 mtspr SPRN_SRR1,r10; \
211 rfid; \
212 b . /* prevent speculative execution */
213
214 /*
215 * This is the start of the interrupt handlers for iSeries
216 * This code runs with relocation on.
217 */
218 #define EXCEPTION_PROLOG_ISERIES_1(area) \
219 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
220 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
221 std r10,area+EX_R10(r13); \
222 std r11,area+EX_R11(r13); \
223 std r12,area+EX_R12(r13); \
224 mfspr r9,SPRN_SPRG1; \
225 std r9,area+EX_R13(r13); \
226 mfcr r9
227
228 #define EXCEPTION_PROLOG_ISERIES_2 \
229 mfmsr r10; \
230 ld r12,PACALPPACAPTR(r13); \
231 ld r11,LPPACASRR0(r12); \
232 ld r12,LPPACASRR1(r12); \
233 ori r10,r10,MSR_RI; \
234 mtmsrd r10,1
235
236 /*
237 * The common exception prolog is used for all except a few exceptions
238 * such as a segment miss on a kernel address. We have to be prepared
239 * to take another exception from the point where we first touch the
240 * kernel stack onwards.
241 *
242 * On entry r13 points to the paca, r9-r13 are saved in the paca,
243 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
244 * SRR1, and relocation is on.
245 */
246 #define EXCEPTION_PROLOG_COMMON(n, area) \
247 andi. r10,r12,MSR_PR; /* See if coming from user */ \
248 mr r10,r1; /* Save r1 */ \
249 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
250 beq- 1f; \
251 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
252 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
253 bge- cr1,bad_stack; /* abort if it is */ \
254 std r9,_CCR(r1); /* save CR in stackframe */ \
255 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
256 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
257 std r10,0(r1); /* make stack chain pointer */ \
258 std r0,GPR0(r1); /* save r0 in stackframe */ \
259 std r10,GPR1(r1); /* save r1 in stackframe */ \
260 ACCOUNT_CPU_USER_ENTRY(r9, r10); \
261 std r2,GPR2(r1); /* save r2 in stackframe */ \
262 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
263 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
264 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
265 ld r10,area+EX_R10(r13); \
266 std r9,GPR9(r1); \
267 std r10,GPR10(r1); \
268 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
269 ld r10,area+EX_R12(r13); \
270 ld r11,area+EX_R13(r13); \
271 std r9,GPR11(r1); \
272 std r10,GPR12(r1); \
273 std r11,GPR13(r1); \
274 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
275 mflr r9; /* save LR in stackframe */ \
276 std r9,_LINK(r1); \
277 mfctr r10; /* save CTR in stackframe */ \
278 std r10,_CTR(r1); \
279 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
280 std r11,_XER(r1); \
281 li r9,(n)+1; \
282 std r9,_TRAP(r1); /* set trap number */ \
283 li r10,0; \
284 ld r11,exception_marker@toc(r2); \
285 std r10,RESULT(r1); /* clear regs->result */ \
286 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
287
288 /*
289 * Exception vectors.
290 */
291 #define STD_EXCEPTION_PSERIES(n, label) \
292 . = n; \
293 .globl label##_pSeries; \
294 label##_pSeries: \
295 HMT_MEDIUM; \
296 mtspr SPRN_SPRG1,r13; /* save r13 */ \
297 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
298
299 #define HSTD_EXCEPTION_PSERIES(n, label) \
300 . = n; \
301 .globl label##_pSeries; \
302 label##_pSeries: \
303 HMT_MEDIUM; \
304 mtspr SPRN_SPRG1,r20; /* save r20 */ \
305 mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
306 mtspr SPRN_SRR0,r20; \
307 mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
308 mtspr SPRN_SRR1,r20; \
309 mfspr r20,SPRN_SPRG1; /* restore r20 */ \
310 mtspr SPRN_SPRG1,r13; /* save r13 */ \
311 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
312
313
314 #define STD_EXCEPTION_ISERIES(n, label, area) \
315 .globl label##_iSeries; \
316 label##_iSeries: \
317 HMT_MEDIUM; \
318 mtspr SPRN_SPRG1,r13; /* save r13 */ \
319 EXCEPTION_PROLOG_ISERIES_1(area); \
320 EXCEPTION_PROLOG_ISERIES_2; \
321 b label##_common
322
323 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
324 .globl label##_iSeries; \
325 label##_iSeries: \
326 HMT_MEDIUM; \
327 mtspr SPRN_SPRG1,r13; /* save r13 */ \
328 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
329 lbz r10,PACAPROCENABLED(r13); \
330 cmpwi 0,r10,0; \
331 beq- label##_iSeries_masked; \
332 EXCEPTION_PROLOG_ISERIES_2; \
333 b label##_common; \
334
335 #ifdef DO_SOFT_DISABLE
336 #define DISABLE_INTS \
337 lbz r10,PACAPROCENABLED(r13); \
338 li r11,0; \
339 std r10,SOFTE(r1); \
340 mfmsr r10; \
341 stb r11,PACAPROCENABLED(r13); \
342 ori r10,r10,MSR_EE; \
343 mtmsrd r10,1
344
345 #define ENABLE_INTS \
346 lbz r10,PACAPROCENABLED(r13); \
347 mfmsr r11; \
348 std r10,SOFTE(r1); \
349 ori r11,r11,MSR_EE; \
350 mtmsrd r11,1
351
352 #else /* hard enable/disable interrupts */
353 #define DISABLE_INTS
354
355 #define ENABLE_INTS \
356 ld r12,_MSR(r1); \
357 mfmsr r11; \
358 rlwimi r11,r12,0,MSR_EE; \
359 mtmsrd r11,1
360
361 #endif
362
363 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
364 .align 7; \
365 .globl label##_common; \
366 label##_common: \
367 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
368 DISABLE_INTS; \
369 bl .save_nvgprs; \
370 addi r3,r1,STACK_FRAME_OVERHEAD; \
371 bl hdlr; \
372 b .ret_from_except
373
374 /*
375 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
376 * in the idle task and therefore need the special idle handling.
377 */
378 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
379 .align 7; \
380 .globl label##_common; \
381 label##_common: \
382 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
383 FINISH_NAP; \
384 DISABLE_INTS; \
385 bl .save_nvgprs; \
386 addi r3,r1,STACK_FRAME_OVERHEAD; \
387 bl hdlr; \
388 b .ret_from_except
389
390 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
391 .align 7; \
392 .globl label##_common; \
393 label##_common: \
394 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
395 FINISH_NAP; \
396 DISABLE_INTS; \
397 bl .ppc64_runlatch_on; \
398 addi r3,r1,STACK_FRAME_OVERHEAD; \
399 bl hdlr; \
400 b .ret_from_except_lite
401
402 /*
403 * When the idle code in power4_idle puts the CPU into NAP mode,
404 * it has to do so in a loop, and relies on the external interrupt
405 * and decrementer interrupt entry code to get it out of the loop.
406 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
407 * to signal that it is in the loop and needs help to get out.
408 */
409 #ifdef CONFIG_PPC_970_NAP
410 #define FINISH_NAP \
411 BEGIN_FTR_SECTION \
412 clrrdi r11,r1,THREAD_SHIFT; \
413 ld r9,TI_LOCAL_FLAGS(r11); \
414 andi. r10,r9,_TLF_NAPPING; \
415 bnel power4_fixup_nap; \
416 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
417 #else
418 #define FINISH_NAP
419 #endif
420
421 /*
422 * Start of pSeries system interrupt routines
423 */
424 . = 0x100
425 .globl __start_interrupts
426 __start_interrupts:
427
428 STD_EXCEPTION_PSERIES(0x100, system_reset)
429
430 . = 0x200
431 _machine_check_pSeries:
432 HMT_MEDIUM
433 mtspr SPRN_SPRG1,r13 /* save r13 */
434 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
435
436 . = 0x300
437 .globl data_access_pSeries
438 data_access_pSeries:
439 HMT_MEDIUM
440 mtspr SPRN_SPRG1,r13
441 BEGIN_FTR_SECTION
442 mtspr SPRN_SPRG2,r12
443 mfspr r13,SPRN_DAR
444 mfspr r12,SPRN_DSISR
445 srdi r13,r13,60
446 rlwimi r13,r12,16,0x20
447 mfcr r12
448 cmpwi r13,0x2c
449 beq .do_stab_bolted_pSeries
450 mtcrf 0x80,r12
451 mfspr r12,SPRN_SPRG2
452 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
453 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
454
455 . = 0x380
456 .globl data_access_slb_pSeries
457 data_access_slb_pSeries:
458 HMT_MEDIUM
459 mtspr SPRN_SPRG1,r13
460 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
461 std r3,PACA_EXSLB+EX_R3(r13)
462 mfspr r3,SPRN_DAR
463 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
464 mfcr r9
465 #ifdef __DISABLED__
466 /* Keep that around for when we re-implement dynamic VSIDs */
467 cmpdi r3,0
468 bge slb_miss_user_pseries
469 #endif /* __DISABLED__ */
470 std r10,PACA_EXSLB+EX_R10(r13)
471 std r11,PACA_EXSLB+EX_R11(r13)
472 std r12,PACA_EXSLB+EX_R12(r13)
473 mfspr r10,SPRN_SPRG1
474 std r10,PACA_EXSLB+EX_R13(r13)
475 mfspr r12,SPRN_SRR1 /* and SRR1 */
476 b .slb_miss_realmode /* Rel. branch works in real mode */
477
478 STD_EXCEPTION_PSERIES(0x400, instruction_access)
479
480 . = 0x480
481 .globl instruction_access_slb_pSeries
482 instruction_access_slb_pSeries:
483 HMT_MEDIUM
484 mtspr SPRN_SPRG1,r13
485 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
486 std r3,PACA_EXSLB+EX_R3(r13)
487 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
488 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
489 mfcr r9
490 #ifdef __DISABLED__
491 /* Keep that around for when we re-implement dynamic VSIDs */
492 cmpdi r3,0
493 bge slb_miss_user_pseries
494 #endif /* __DISABLED__ */
495 std r10,PACA_EXSLB+EX_R10(r13)
496 std r11,PACA_EXSLB+EX_R11(r13)
497 std r12,PACA_EXSLB+EX_R12(r13)
498 mfspr r10,SPRN_SPRG1
499 std r10,PACA_EXSLB+EX_R13(r13)
500 mfspr r12,SPRN_SRR1 /* and SRR1 */
501 b .slb_miss_realmode /* Rel. branch works in real mode */
502
503 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
504 STD_EXCEPTION_PSERIES(0x600, alignment)
505 STD_EXCEPTION_PSERIES(0x700, program_check)
506 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
507 STD_EXCEPTION_PSERIES(0x900, decrementer)
508 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
509 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
510
511 . = 0xc00
512 .globl system_call_pSeries
513 system_call_pSeries:
514 HMT_MEDIUM
515 mr r9,r13
516 mfmsr r10
517 mfspr r13,SPRN_SPRG3
518 mfspr r11,SPRN_SRR0
519 clrrdi r12,r13,32
520 oris r12,r12,system_call_common@h
521 ori r12,r12,system_call_common@l
522 mtspr SPRN_SRR0,r12
523 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
524 mfspr r12,SPRN_SRR1
525 mtspr SPRN_SRR1,r10
526 rfid
527 b . /* prevent speculative execution */
528
529 STD_EXCEPTION_PSERIES(0xd00, single_step)
530 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
531
532 /* We need to deal with the Altivec unavailable exception
533 * here which is at 0xf20, thus in the middle of the
534 * prolog code of the PerformanceMonitor one. A little
535 * trickery is thus necessary
536 */
537 . = 0xf00
538 b performance_monitor_pSeries
539
540 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
541
542 #ifdef CONFIG_CBE_RAS
543 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
544 #endif /* CONFIG_CBE_RAS */
545 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
546 #ifdef CONFIG_CBE_RAS
547 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
548 #endif /* CONFIG_CBE_RAS */
549 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
550 #ifdef CONFIG_CBE_RAS
551 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
552 #endif /* CONFIG_CBE_RAS */
553
554 . = 0x3000
555
556 /*** pSeries interrupt support ***/
557
558 /* moved from 0xf00 */
559 STD_EXCEPTION_PSERIES(., performance_monitor)
560
561 .align 7
562 _GLOBAL(do_stab_bolted_pSeries)
563 mtcrf 0x80,r12
564 mfspr r12,SPRN_SPRG2
565 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
566
567 /*
568 * We have some room here we use that to put
569 * the peries slb miss user trampoline code so it's reasonably
570 * away from slb_miss_user_common to avoid problems with rfid
571 *
572 * This is used for when the SLB miss handler has to go virtual,
573 * which doesn't happen for now anymore but will once we re-implement
574 * dynamic VSIDs for shared page tables
575 */
576 #ifdef __DISABLED__
577 slb_miss_user_pseries:
578 std r10,PACA_EXGEN+EX_R10(r13)
579 std r11,PACA_EXGEN+EX_R11(r13)
580 std r12,PACA_EXGEN+EX_R12(r13)
581 mfspr r10,SPRG1
582 ld r11,PACA_EXSLB+EX_R9(r13)
583 ld r12,PACA_EXSLB+EX_R3(r13)
584 std r10,PACA_EXGEN+EX_R13(r13)
585 std r11,PACA_EXGEN+EX_R9(r13)
586 std r12,PACA_EXGEN+EX_R3(r13)
587 clrrdi r12,r13,32
588 mfmsr r10
589 mfspr r11,SRR0 /* save SRR0 */
590 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
591 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
592 mtspr SRR0,r12
593 mfspr r12,SRR1 /* and SRR1 */
594 mtspr SRR1,r10
595 rfid
596 b . /* prevent spec. execution */
597 #endif /* __DISABLED__ */
598
599 /*
600 * Vectors for the FWNMI option. Share common code.
601 */
602 .globl system_reset_fwnmi
603 .align 7
604 system_reset_fwnmi:
605 HMT_MEDIUM
606 mtspr SPRN_SPRG1,r13 /* save r13 */
607 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
608
609 .globl machine_check_fwnmi
610 .align 7
611 machine_check_fwnmi:
612 HMT_MEDIUM
613 mtspr SPRN_SPRG1,r13 /* save r13 */
614 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
615
616 #ifdef CONFIG_PPC_ISERIES
617 /*** ISeries-LPAR interrupt handlers ***/
618
619 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
620
621 .globl data_access_iSeries
622 data_access_iSeries:
623 mtspr SPRN_SPRG1,r13
624 BEGIN_FTR_SECTION
625 mtspr SPRN_SPRG2,r12
626 mfspr r13,SPRN_DAR
627 mfspr r12,SPRN_DSISR
628 srdi r13,r13,60
629 rlwimi r13,r12,16,0x20
630 mfcr r12
631 cmpwi r13,0x2c
632 beq .do_stab_bolted_iSeries
633 mtcrf 0x80,r12
634 mfspr r12,SPRN_SPRG2
635 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
636 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
637 EXCEPTION_PROLOG_ISERIES_2
638 b data_access_common
639
640 .do_stab_bolted_iSeries:
641 mtcrf 0x80,r12
642 mfspr r12,SPRN_SPRG2
643 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
644 EXCEPTION_PROLOG_ISERIES_2
645 b .do_stab_bolted
646
647 .globl data_access_slb_iSeries
648 data_access_slb_iSeries:
649 mtspr SPRN_SPRG1,r13 /* save r13 */
650 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
651 std r3,PACA_EXSLB+EX_R3(r13)
652 mfspr r3,SPRN_DAR
653 std r9,PACA_EXSLB+EX_R9(r13)
654 mfcr r9
655 #ifdef __DISABLED__
656 cmpdi r3,0
657 bge slb_miss_user_iseries
658 #endif
659 std r10,PACA_EXSLB+EX_R10(r13)
660 std r11,PACA_EXSLB+EX_R11(r13)
661 std r12,PACA_EXSLB+EX_R12(r13)
662 mfspr r10,SPRN_SPRG1
663 std r10,PACA_EXSLB+EX_R13(r13)
664 ld r12,PACALPPACAPTR(r13)
665 ld r12,LPPACASRR1(r12)
666 b .slb_miss_realmode
667
668 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
669
670 .globl instruction_access_slb_iSeries
671 instruction_access_slb_iSeries:
672 mtspr SPRN_SPRG1,r13 /* save r13 */
673 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
674 std r3,PACA_EXSLB+EX_R3(r13)
675 ld r3,PACALPPACAPTR(r13)
676 ld r3,LPPACASRR0(r3) /* get SRR0 value */
677 std r9,PACA_EXSLB+EX_R9(r13)
678 mfcr r9
679 #ifdef __DISABLED__
680 cmpdi r3,0
681 bge .slb_miss_user_iseries
682 #endif
683 std r10,PACA_EXSLB+EX_R10(r13)
684 std r11,PACA_EXSLB+EX_R11(r13)
685 std r12,PACA_EXSLB+EX_R12(r13)
686 mfspr r10,SPRN_SPRG1
687 std r10,PACA_EXSLB+EX_R13(r13)
688 ld r12,PACALPPACAPTR(r13)
689 ld r12,LPPACASRR1(r12)
690 b .slb_miss_realmode
691
692 #ifdef __DISABLED__
693 slb_miss_user_iseries:
694 std r10,PACA_EXGEN+EX_R10(r13)
695 std r11,PACA_EXGEN+EX_R11(r13)
696 std r12,PACA_EXGEN+EX_R12(r13)
697 mfspr r10,SPRG1
698 ld r11,PACA_EXSLB+EX_R9(r13)
699 ld r12,PACA_EXSLB+EX_R3(r13)
700 std r10,PACA_EXGEN+EX_R13(r13)
701 std r11,PACA_EXGEN+EX_R9(r13)
702 std r12,PACA_EXGEN+EX_R3(r13)
703 EXCEPTION_PROLOG_ISERIES_2
704 b slb_miss_user_common
705 #endif
706
707 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
708 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
709 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
710 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
711 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
712 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
713 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
714
715 .globl system_call_iSeries
716 system_call_iSeries:
717 mr r9,r13
718 mfspr r13,SPRN_SPRG3
719 EXCEPTION_PROLOG_ISERIES_2
720 b system_call_common
721
722 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
723 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
724 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
725
726 .globl system_reset_iSeries
727 system_reset_iSeries:
728 mfspr r13,SPRN_SPRG3 /* Get paca address */
729 mfmsr r24
730 ori r24,r24,MSR_RI
731 mtmsrd r24 /* RI on */
732 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
733 cmpwi 0,r24,0 /* Are we processor 0? */
734 beq .__start_initialization_iSeries /* Start up the first processor */
735 mfspr r4,SPRN_CTRLF
736 li r5,CTRL_RUNLATCH /* Turn off the run light */
737 andc r4,r4,r5
738 mtspr SPRN_CTRLT,r4
739
740 1:
741 HMT_LOW
742 #ifdef CONFIG_SMP
743 lbz r23,PACAPROCSTART(r13) /* Test if this processor
744 * should start */
745 sync
746 LOAD_REG_IMMEDIATE(r3,current_set)
747 sldi r28,r24,3 /* get current_set[cpu#] */
748 ldx r3,r3,r28
749 addi r1,r3,THREAD_SIZE
750 subi r1,r1,STACK_FRAME_OVERHEAD
751
752 cmpwi 0,r23,0
753 beq iSeries_secondary_smp_loop /* Loop until told to go */
754 bne .__secondary_start /* Loop until told to go */
755 iSeries_secondary_smp_loop:
756 /* Let the Hypervisor know we are alive */
757 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
758 lis r3,0x8002
759 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
760 #else /* CONFIG_SMP */
761 /* Yield the processor. This is required for non-SMP kernels
762 which are running on multi-threaded machines. */
763 lis r3,0x8000
764 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
765 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
766 li r4,0 /* "yield timed" */
767 li r5,-1 /* "yield forever" */
768 #endif /* CONFIG_SMP */
769 li r0,-1 /* r0=-1 indicates a Hypervisor call */
770 sc /* Invoke the hypervisor via a system call */
771 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
772 b 1b /* If SMP not configured, secondaries
773 * loop forever */
774
775 .globl decrementer_iSeries_masked
776 decrementer_iSeries_masked:
777 /* We may not have a valid TOC pointer in here. */
778 li r11,1
779 ld r12,PACALPPACAPTR(r13)
780 stb r11,LPPACADECRINT(r12)
781 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
782 lwz r12,0(r12)
783 mtspr SPRN_DEC,r12
784 /* fall through */
785
786 .globl hardware_interrupt_iSeries_masked
787 hardware_interrupt_iSeries_masked:
788 mtcrf 0x80,r9 /* Restore regs */
789 ld r12,PACALPPACAPTR(r13)
790 ld r11,LPPACASRR0(r12)
791 ld r12,LPPACASRR1(r12)
792 mtspr SPRN_SRR0,r11
793 mtspr SPRN_SRR1,r12
794 ld r9,PACA_EXGEN+EX_R9(r13)
795 ld r10,PACA_EXGEN+EX_R10(r13)
796 ld r11,PACA_EXGEN+EX_R11(r13)
797 ld r12,PACA_EXGEN+EX_R12(r13)
798 ld r13,PACA_EXGEN+EX_R13(r13)
799 rfid
800 b . /* prevent speculative execution */
801 #endif /* CONFIG_PPC_ISERIES */
802
803 /*** Common interrupt handlers ***/
804
805 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
806
807 /*
808 * Machine check is different because we use a different
809 * save area: PACA_EXMC instead of PACA_EXGEN.
810 */
811 .align 7
812 .globl machine_check_common
813 machine_check_common:
814 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
815 FINISH_NAP
816 DISABLE_INTS
817 bl .save_nvgprs
818 addi r3,r1,STACK_FRAME_OVERHEAD
819 bl .machine_check_exception
820 b .ret_from_except
821
822 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
823 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
824 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
825 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
826 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
827 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
828 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
829 #ifdef CONFIG_ALTIVEC
830 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
831 #else
832 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
833 #endif
834 #ifdef CONFIG_CBE_RAS
835 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
836 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
837 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
838 #endif /* CONFIG_CBE_RAS */
839
840 /*
841 * Here we have detected that the kernel stack pointer is bad.
842 * R9 contains the saved CR, r13 points to the paca,
843 * r10 contains the (bad) kernel stack pointer,
844 * r11 and r12 contain the saved SRR0 and SRR1.
845 * We switch to using an emergency stack, save the registers there,
846 * and call kernel_bad_stack(), which panics.
847 */
848 bad_stack:
849 ld r1,PACAEMERGSP(r13)
850 subi r1,r1,64+INT_FRAME_SIZE
851 std r9,_CCR(r1)
852 std r10,GPR1(r1)
853 std r11,_NIP(r1)
854 std r12,_MSR(r1)
855 mfspr r11,SPRN_DAR
856 mfspr r12,SPRN_DSISR
857 std r11,_DAR(r1)
858 std r12,_DSISR(r1)
859 mflr r10
860 mfctr r11
861 mfxer r12
862 std r10,_LINK(r1)
863 std r11,_CTR(r1)
864 std r12,_XER(r1)
865 SAVE_GPR(0,r1)
866 SAVE_GPR(2,r1)
867 SAVE_4GPRS(3,r1)
868 SAVE_2GPRS(7,r1)
869 SAVE_10GPRS(12,r1)
870 SAVE_10GPRS(22,r1)
871 addi r11,r1,INT_FRAME_SIZE
872 std r11,0(r1)
873 li r12,0
874 std r12,0(r11)
875 ld r2,PACATOC(r13)
876 1: addi r3,r1,STACK_FRAME_OVERHEAD
877 bl .kernel_bad_stack
878 b 1b
879
880 /*
881 * Return from an exception with minimal checks.
882 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
883 * If interrupts have been enabled, or anything has been
884 * done that might have changed the scheduling status of
885 * any task or sent any task a signal, you should use
886 * ret_from_except or ret_from_except_lite instead of this.
887 */
888 .globl fast_exception_return
889 fast_exception_return:
890 ld r12,_MSR(r1)
891 ld r11,_NIP(r1)
892 andi. r3,r12,MSR_RI /* check if RI is set */
893 beq- unrecov_fer
894
895 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
896 andi. r3,r12,MSR_PR
897 beq 2f
898 ACCOUNT_CPU_USER_EXIT(r3, r4)
899 2:
900 #endif
901
902 ld r3,_CCR(r1)
903 ld r4,_LINK(r1)
904 ld r5,_CTR(r1)
905 ld r6,_XER(r1)
906 mtcr r3
907 mtlr r4
908 mtctr r5
909 mtxer r6
910 REST_GPR(0, r1)
911 REST_8GPRS(2, r1)
912
913 mfmsr r10
914 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
915 mtmsrd r10,1
916
917 mtspr SPRN_SRR1,r12
918 mtspr SPRN_SRR0,r11
919 REST_4GPRS(10, r1)
920 ld r1,GPR1(r1)
921 rfid
922 b . /* prevent speculative execution */
923
924 unrecov_fer:
925 bl .save_nvgprs
926 1: addi r3,r1,STACK_FRAME_OVERHEAD
927 bl .unrecoverable_exception
928 b 1b
929
930 /*
931 * Here r13 points to the paca, r9 contains the saved CR,
932 * SRR0 and SRR1 are saved in r11 and r12,
933 * r9 - r13 are saved in paca->exgen.
934 */
935 .align 7
936 .globl data_access_common
937 data_access_common:
938 mfspr r10,SPRN_DAR
939 std r10,PACA_EXGEN+EX_DAR(r13)
940 mfspr r10,SPRN_DSISR
941 stw r10,PACA_EXGEN+EX_DSISR(r13)
942 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
943 ld r3,PACA_EXGEN+EX_DAR(r13)
944 lwz r4,PACA_EXGEN+EX_DSISR(r13)
945 li r5,0x300
946 b .do_hash_page /* Try to handle as hpte fault */
947
948 .align 7
949 .globl instruction_access_common
950 instruction_access_common:
951 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
952 ld r3,_NIP(r1)
953 andis. r4,r12,0x5820
954 li r5,0x400
955 b .do_hash_page /* Try to handle as hpte fault */
956
957 /*
958 * Here is the common SLB miss user that is used when going to virtual
959 * mode for SLB misses, that is currently not used
960 */
961 #ifdef __DISABLED__
962 .align 7
963 .globl slb_miss_user_common
964 slb_miss_user_common:
965 mflr r10
966 std r3,PACA_EXGEN+EX_DAR(r13)
967 stw r9,PACA_EXGEN+EX_CCR(r13)
968 std r10,PACA_EXGEN+EX_LR(r13)
969 std r11,PACA_EXGEN+EX_SRR0(r13)
970 bl .slb_allocate_user
971
972 ld r10,PACA_EXGEN+EX_LR(r13)
973 ld r3,PACA_EXGEN+EX_R3(r13)
974 lwz r9,PACA_EXGEN+EX_CCR(r13)
975 ld r11,PACA_EXGEN+EX_SRR0(r13)
976 mtlr r10
977 beq- slb_miss_fault
978
979 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
980 beq- unrecov_user_slb
981 mfmsr r10
982
983 .machine push
984 .machine "power4"
985 mtcrf 0x80,r9
986 .machine pop
987
988 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
989 mtmsrd r10,1
990
991 mtspr SRR0,r11
992 mtspr SRR1,r12
993
994 ld r9,PACA_EXGEN+EX_R9(r13)
995 ld r10,PACA_EXGEN+EX_R10(r13)
996 ld r11,PACA_EXGEN+EX_R11(r13)
997 ld r12,PACA_EXGEN+EX_R12(r13)
998 ld r13,PACA_EXGEN+EX_R13(r13)
999 rfid
1000 b .
1001
1002 slb_miss_fault:
1003 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1004 ld r4,PACA_EXGEN+EX_DAR(r13)
1005 li r5,0
1006 std r4,_DAR(r1)
1007 std r5,_DSISR(r1)
1008 b .handle_page_fault
1009
1010 unrecov_user_slb:
1011 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1012 DISABLE_INTS
1013 bl .save_nvgprs
1014 1: addi r3,r1,STACK_FRAME_OVERHEAD
1015 bl .unrecoverable_exception
1016 b 1b
1017
1018 #endif /* __DISABLED__ */
1019
1020
1021 /*
1022 * r13 points to the PACA, r9 contains the saved CR,
1023 * r12 contain the saved SRR1, SRR0 is still ready for return
1024 * r3 has the faulting address
1025 * r9 - r13 are saved in paca->exslb.
1026 * r3 is saved in paca->slb_r3
1027 * We assume we aren't going to take any exceptions during this procedure.
1028 */
1029 _GLOBAL(slb_miss_realmode)
1030 mflr r10
1031
1032 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1033 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1034
1035 bl .slb_allocate_realmode
1036
1037 /* All done -- return from exception. */
1038
1039 ld r10,PACA_EXSLB+EX_LR(r13)
1040 ld r3,PACA_EXSLB+EX_R3(r13)
1041 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1042 #ifdef CONFIG_PPC_ISERIES
1043 ld r11,PACALPPACAPTR(r13)
1044 ld r11,LPPACASRR0(r11) /* get SRR0 value */
1045 #endif /* CONFIG_PPC_ISERIES */
1046
1047 mtlr r10
1048
1049 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1050 beq- unrecov_slb
1051
1052 .machine push
1053 .machine "power4"
1054 mtcrf 0x80,r9
1055 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1056 .machine pop
1057
1058 #ifdef CONFIG_PPC_ISERIES
1059 mtspr SPRN_SRR0,r11
1060 mtspr SPRN_SRR1,r12
1061 #endif /* CONFIG_PPC_ISERIES */
1062 ld r9,PACA_EXSLB+EX_R9(r13)
1063 ld r10,PACA_EXSLB+EX_R10(r13)
1064 ld r11,PACA_EXSLB+EX_R11(r13)
1065 ld r12,PACA_EXSLB+EX_R12(r13)
1066 ld r13,PACA_EXSLB+EX_R13(r13)
1067 rfid
1068 b . /* prevent speculative execution */
1069
1070 unrecov_slb:
1071 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1072 DISABLE_INTS
1073 bl .save_nvgprs
1074 1: addi r3,r1,STACK_FRAME_OVERHEAD
1075 bl .unrecoverable_exception
1076 b 1b
1077
1078 .align 7
1079 .globl hardware_interrupt_common
1080 .globl hardware_interrupt_entry
1081 hardware_interrupt_common:
1082 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1083 FINISH_NAP
1084 hardware_interrupt_entry:
1085 DISABLE_INTS
1086 bl .ppc64_runlatch_on
1087 addi r3,r1,STACK_FRAME_OVERHEAD
1088 bl .do_IRQ
1089 b .ret_from_except_lite
1090
1091 #ifdef CONFIG_PPC_970_NAP
1092 power4_fixup_nap:
1093 andc r9,r9,r10
1094 std r9,TI_LOCAL_FLAGS(r11)
1095 ld r10,_LINK(r1) /* make idle task do the */
1096 std r10,_NIP(r1) /* equivalent of a blr */
1097 blr
1098 #endif
1099
1100 .align 7
1101 .globl alignment_common
1102 alignment_common:
1103 mfspr r10,SPRN_DAR
1104 std r10,PACA_EXGEN+EX_DAR(r13)
1105 mfspr r10,SPRN_DSISR
1106 stw r10,PACA_EXGEN+EX_DSISR(r13)
1107 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1108 ld r3,PACA_EXGEN+EX_DAR(r13)
1109 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1110 std r3,_DAR(r1)
1111 std r4,_DSISR(r1)
1112 bl .save_nvgprs
1113 addi r3,r1,STACK_FRAME_OVERHEAD
1114 ENABLE_INTS
1115 bl .alignment_exception
1116 b .ret_from_except
1117
1118 .align 7
1119 .globl program_check_common
1120 program_check_common:
1121 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1122 bl .save_nvgprs
1123 addi r3,r1,STACK_FRAME_OVERHEAD
1124 ENABLE_INTS
1125 bl .program_check_exception
1126 b .ret_from_except
1127
1128 .align 7
1129 .globl fp_unavailable_common
1130 fp_unavailable_common:
1131 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1132 bne .load_up_fpu /* if from user, just load it up */
1133 bl .save_nvgprs
1134 addi r3,r1,STACK_FRAME_OVERHEAD
1135 ENABLE_INTS
1136 bl .kernel_fp_unavailable_exception
1137 BUG_OPCODE
1138
1139 .align 7
1140 .globl altivec_unavailable_common
1141 altivec_unavailable_common:
1142 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1143 #ifdef CONFIG_ALTIVEC
1144 BEGIN_FTR_SECTION
1145 bne .load_up_altivec /* if from user, just load it up */
1146 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1147 #endif
1148 bl .save_nvgprs
1149 addi r3,r1,STACK_FRAME_OVERHEAD
1150 ENABLE_INTS
1151 bl .altivec_unavailable_exception
1152 b .ret_from_except
1153
1154 #ifdef CONFIG_ALTIVEC
1155 /*
1156 * load_up_altivec(unused, unused, tsk)
1157 * Disable VMX for the task which had it previously,
1158 * and save its vector registers in its thread_struct.
1159 * Enables the VMX for use in the kernel on return.
1160 * On SMP we know the VMX is free, since we give it up every
1161 * switch (ie, no lazy save of the vector registers).
1162 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1163 */
1164 _STATIC(load_up_altivec)
1165 mfmsr r5 /* grab the current MSR */
1166 oris r5,r5,MSR_VEC@h
1167 mtmsrd r5 /* enable use of VMX now */
1168 isync
1169
1170 /*
1171 * For SMP, we don't do lazy VMX switching because it just gets too
1172 * horrendously complex, especially when a task switches from one CPU
1173 * to another. Instead we call giveup_altvec in switch_to.
1174 * VRSAVE isn't dealt with here, that is done in the normal context
1175 * switch code. Note that we could rely on vrsave value to eventually
1176 * avoid saving all of the VREGs here...
1177 */
1178 #ifndef CONFIG_SMP
1179 ld r3,last_task_used_altivec@got(r2)
1180 ld r4,0(r3)
1181 cmpdi 0,r4,0
1182 beq 1f
1183 /* Save VMX state to last_task_used_altivec's THREAD struct */
1184 addi r4,r4,THREAD
1185 SAVE_32VRS(0,r5,r4)
1186 mfvscr vr0
1187 li r10,THREAD_VSCR
1188 stvx vr0,r10,r4
1189 /* Disable VMX for last_task_used_altivec */
1190 ld r5,PT_REGS(r4)
1191 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1192 lis r6,MSR_VEC@h
1193 andc r4,r4,r6
1194 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1195 1:
1196 #endif /* CONFIG_SMP */
1197 /* Hack: if we get an altivec unavailable trap with VRSAVE
1198 * set to all zeros, we assume this is a broken application
1199 * that fails to set it properly, and thus we switch it to
1200 * all 1's
1201 */
1202 mfspr r4,SPRN_VRSAVE
1203 cmpdi 0,r4,0
1204 bne+ 1f
1205 li r4,-1
1206 mtspr SPRN_VRSAVE,r4
1207 1:
1208 /* enable use of VMX after return */
1209 ld r4,PACACURRENT(r13)
1210 addi r5,r4,THREAD /* Get THREAD */
1211 oris r12,r12,MSR_VEC@h
1212 std r12,_MSR(r1)
1213 li r4,1
1214 li r10,THREAD_VSCR
1215 stw r4,THREAD_USED_VR(r5)
1216 lvx vr0,r10,r5
1217 mtvscr vr0
1218 REST_32VRS(0,r4,r5)
1219 #ifndef CONFIG_SMP
1220 /* Update last_task_used_math to 'current' */
1221 subi r4,r5,THREAD /* Back to 'current' */
1222 std r4,0(r3)
1223 #endif /* CONFIG_SMP */
1224 /* restore registers and return */
1225 b fast_exception_return
1226 #endif /* CONFIG_ALTIVEC */
1227
1228 /*
1229 * Hash table stuff
1230 */
1231 .align 7
1232 _GLOBAL(do_hash_page)
1233 std r3,_DAR(r1)
1234 std r4,_DSISR(r1)
1235
1236 andis. r0,r4,0xa450 /* weird error? */
1237 bne- .handle_page_fault /* if not, try to insert a HPTE */
1238 BEGIN_FTR_SECTION
1239 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1240 bne- .do_ste_alloc /* If so handle it */
1241 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1242
1243 /*
1244 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1245 * accessing a userspace segment (even from the kernel). We assume
1246 * kernel addresses always have the high bit set.
1247 */
1248 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1249 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1250 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1251 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1252 ori r4,r4,1 /* add _PAGE_PRESENT */
1253 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1254
1255 /*
1256 * On iSeries, we soft-disable interrupts here, then
1257 * hard-enable interrupts so that the hash_page code can spin on
1258 * the hash_table_lock without problems on a shared processor.
1259 */
1260 DISABLE_INTS
1261
1262 /*
1263 * r3 contains the faulting address
1264 * r4 contains the required access permissions
1265 * r5 contains the trap number
1266 *
1267 * at return r3 = 0 for success
1268 */
1269 bl .hash_page /* build HPTE if possible */
1270 cmpdi r3,0 /* see if hash_page succeeded */
1271
1272 #ifdef DO_SOFT_DISABLE
1273 /*
1274 * If we had interrupts soft-enabled at the point where the
1275 * DSI/ISI occurred, and an interrupt came in during hash_page,
1276 * handle it now.
1277 * We jump to ret_from_except_lite rather than fast_exception_return
1278 * because ret_from_except_lite will check for and handle pending
1279 * interrupts if necessary.
1280 */
1281 beq .ret_from_except_lite
1282 /* For a hash failure, we don't bother re-enabling interrupts */
1283 ble- 12f
1284
1285 /*
1286 * hash_page couldn't handle it, set soft interrupt enable back
1287 * to what it was before the trap. Note that .local_irq_restore
1288 * handles any interrupts pending at this point.
1289 */
1290 ld r3,SOFTE(r1)
1291 bl .local_irq_restore
1292 b 11f
1293 #else
1294 beq fast_exception_return /* Return from exception on success */
1295 ble- 12f /* Failure return from hash_page */
1296
1297 /* fall through */
1298 #endif
1299
1300 /* Here we have a page fault that hash_page can't handle. */
1301 _GLOBAL(handle_page_fault)
1302 ENABLE_INTS
1303 11: ld r4,_DAR(r1)
1304 ld r5,_DSISR(r1)
1305 addi r3,r1,STACK_FRAME_OVERHEAD
1306 bl .do_page_fault
1307 cmpdi r3,0
1308 beq+ .ret_from_except_lite
1309 bl .save_nvgprs
1310 mr r5,r3
1311 addi r3,r1,STACK_FRAME_OVERHEAD
1312 lwz r4,_DAR(r1)
1313 bl .bad_page_fault
1314 b .ret_from_except
1315
1316 /* We have a page fault that hash_page could handle but HV refused
1317 * the PTE insertion
1318 */
1319 12: bl .save_nvgprs
1320 addi r3,r1,STACK_FRAME_OVERHEAD
1321 lwz r4,_DAR(r1)
1322 bl .low_hash_fault
1323 b .ret_from_except
1324
1325 /* here we have a segment miss */
1326 _GLOBAL(do_ste_alloc)
1327 bl .ste_allocate /* try to insert stab entry */
1328 cmpdi r3,0
1329 beq+ fast_exception_return
1330 b .handle_page_fault
1331
1332 /*
1333 * r13 points to the PACA, r9 contains the saved CR,
1334 * r11 and r12 contain the saved SRR0 and SRR1.
1335 * r9 - r13 are saved in paca->exslb.
1336 * We assume we aren't going to take any exceptions during this procedure.
1337 * We assume (DAR >> 60) == 0xc.
1338 */
1339 .align 7
1340 _GLOBAL(do_stab_bolted)
1341 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1342 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1343
1344 /* Hash to the primary group */
1345 ld r10,PACASTABVIRT(r13)
1346 mfspr r11,SPRN_DAR
1347 srdi r11,r11,28
1348 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1349
1350 /* Calculate VSID */
1351 /* This is a kernel address, so protovsid = ESID */
1352 ASM_VSID_SCRAMBLE(r11, r9)
1353 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1354
1355 /* Search the primary group for a free entry */
1356 1: ld r11,0(r10) /* Test valid bit of the current ste */
1357 andi. r11,r11,0x80
1358 beq 2f
1359 addi r10,r10,16
1360 andi. r11,r10,0x70
1361 bne 1b
1362
1363 /* Stick for only searching the primary group for now. */
1364 /* At least for now, we use a very simple random castout scheme */
1365 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1366 mftb r11
1367 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1368 ori r11,r11,0x10
1369
1370 /* r10 currently points to an ste one past the group of interest */
1371 /* make it point to the randomly selected entry */
1372 subi r10,r10,128
1373 or r10,r10,r11 /* r10 is the entry to invalidate */
1374
1375 isync /* mark the entry invalid */
1376 ld r11,0(r10)
1377 rldicl r11,r11,56,1 /* clear the valid bit */
1378 rotldi r11,r11,8
1379 std r11,0(r10)
1380 sync
1381
1382 clrrdi r11,r11,28 /* Get the esid part of the ste */
1383 slbie r11
1384
1385 2: std r9,8(r10) /* Store the vsid part of the ste */
1386 eieio
1387
1388 mfspr r11,SPRN_DAR /* Get the new esid */
1389 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1390 ori r11,r11,0x90 /* Turn on valid and kp */
1391 std r11,0(r10) /* Put new entry back into the stab */
1392
1393 sync
1394
1395 /* All done -- return from exception. */
1396 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1397 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1398
1399 andi. r10,r12,MSR_RI
1400 beq- unrecov_slb
1401
1402 mtcrf 0x80,r9 /* restore CR */
1403
1404 mfmsr r10
1405 clrrdi r10,r10,2
1406 mtmsrd r10,1
1407
1408 mtspr SPRN_SRR0,r11
1409 mtspr SPRN_SRR1,r12
1410 ld r9,PACA_EXSLB+EX_R9(r13)
1411 ld r10,PACA_EXSLB+EX_R10(r13)
1412 ld r11,PACA_EXSLB+EX_R11(r13)
1413 ld r12,PACA_EXSLB+EX_R12(r13)
1414 ld r13,PACA_EXSLB+EX_R13(r13)
1415 rfid
1416 b . /* prevent speculative execution */
1417
1418 /*
1419 * Space for CPU0's segment table.
1420 *
1421 * On iSeries, the hypervisor must fill in at least one entry before
1422 * we get control (with relocate on). The address is give to the hv
1423 * as a page number (see xLparMap in lpardata.c), so this must be at a
1424 * fixed address (the linker can't compute (u64)&initial_stab >>
1425 * PAGE_SHIFT).
1426 */
1427 . = STAB0_OFFSET /* 0x6000 */
1428 .globl initial_stab
1429 initial_stab:
1430 .space 4096
1431
1432 /*
1433 * Data area reserved for FWNMI option.
1434 * This address (0x7000) is fixed by the RPA.
1435 */
1436 .= 0x7000
1437 .globl fwnmi_data_area
1438 fwnmi_data_area:
1439
1440 /* iSeries does not use the FWNMI stuff, so it is safe to put
1441 * this here, even if we later allow kernels that will boot on
1442 * both pSeries and iSeries */
1443 #ifdef CONFIG_PPC_ISERIES
1444 . = LPARMAP_PHYS
1445 #include "lparmap.s"
1446 /*
1447 * This ".text" is here for old compilers that generate a trailing
1448 * .note section when compiling .c files to .s
1449 */
1450 .text
1451 #endif /* CONFIG_PPC_ISERIES */
1452
1453 . = 0x8000
1454
1455 /*
1456 * On pSeries, secondary processors spin in the following code.
1457 * At entry, r3 = this processor's number (physical cpu id)
1458 */
1459 _GLOBAL(pSeries_secondary_smp_init)
1460 mr r24,r3
1461
1462 /* turn on 64-bit mode */
1463 bl .enable_64b_mode
1464 isync
1465
1466 /* Copy some CPU settings from CPU 0 */
1467 bl .__restore_cpu_setup
1468
1469 /* Set up a paca value for this processor. Since we have the
1470 * physical cpu id in r24, we need to search the pacas to find
1471 * which logical id maps to our physical one.
1472 */
1473 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1474 li r5,0 /* logical cpu id */
1475 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1476 cmpw r6,r24 /* Compare to our id */
1477 beq 2f
1478 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1479 addi r5,r5,1
1480 cmpwi r5,NR_CPUS
1481 blt 1b
1482
1483 mr r3,r24 /* not found, copy phys to r3 */
1484 b .kexec_wait /* next kernel might do better */
1485
1486 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1487 /* From now on, r24 is expected to be logical cpuid */
1488 mr r24,r5
1489 3: HMT_LOW
1490 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1491 /* start. */
1492 sync
1493
1494 /* Create a temp kernel stack for use before relocation is on. */
1495 ld r1,PACAEMERGSP(r13)
1496 subi r1,r1,STACK_FRAME_OVERHEAD
1497
1498 cmpwi 0,r23,0
1499 #ifdef CONFIG_SMP
1500 bne .__secondary_start
1501 #endif
1502 b 3b /* Loop until told to go */
1503
1504 #ifdef CONFIG_PPC_ISERIES
1505 _STATIC(__start_initialization_iSeries)
1506 /* Clear out the BSS */
1507 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1508 LOAD_REG_IMMEDIATE(r8,__bss_start)
1509 sub r11,r11,r8 /* bss size */
1510 addi r11,r11,7 /* round up to an even double word */
1511 rldicl. r11,r11,61,3 /* shift right by 3 */
1512 beq 4f
1513 addi r8,r8,-8
1514 li r0,0
1515 mtctr r11 /* zero this many doublewords */
1516 3: stdu r0,8(r8)
1517 bdnz 3b
1518 4:
1519 LOAD_REG_IMMEDIATE(r1,init_thread_union)
1520 addi r1,r1,THREAD_SIZE
1521 li r0,0
1522 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1523
1524 LOAD_REG_IMMEDIATE(r3,cpu_specs)
1525 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1526 li r5,0
1527 bl .identify_cpu
1528
1529 LOAD_REG_IMMEDIATE(r2,__toc_start)
1530 addi r2,r2,0x4000
1531 addi r2,r2,0x4000
1532
1533 bl .iSeries_early_setup
1534 bl .early_setup
1535
1536 /* relocation is on at this point */
1537
1538 b .start_here_common
1539 #endif /* CONFIG_PPC_ISERIES */
1540
1541 #ifdef CONFIG_PPC_MULTIPLATFORM
1542
1543 _STATIC(__mmu_off)
1544 mfmsr r3
1545 andi. r0,r3,MSR_IR|MSR_DR
1546 beqlr
1547 andc r3,r3,r0
1548 mtspr SPRN_SRR0,r4
1549 mtspr SPRN_SRR1,r3
1550 sync
1551 rfid
1552 b . /* prevent speculative execution */
1553
1554
1555 /*
1556 * Here is our main kernel entry point. We support currently 2 kind of entries
1557 * depending on the value of r5.
1558 *
1559 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1560 * in r3...r7
1561 *
1562 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1563 * DT block, r4 is a physical pointer to the kernel itself
1564 *
1565 */
1566 _GLOBAL(__start_initialization_multiplatform)
1567 #ifdef CONFIG_PPC_MULTIPLATFORM
1568 /*
1569 * Are we booted from a PROM Of-type client-interface ?
1570 */
1571 cmpldi cr0,r5,0
1572 bne .__boot_from_prom /* yes -> prom */
1573 #endif
1574
1575 /* Save parameters */
1576 mr r31,r3
1577 mr r30,r4
1578
1579 /* Make sure we are running in 64 bits mode */
1580 bl .enable_64b_mode
1581
1582 /* Setup some critical 970 SPRs before switching MMU off */
1583 bl .__970_cpu_preinit
1584
1585 /* Switch off MMU if not already */
1586 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1587 add r4,r4,r30
1588 bl .__mmu_off
1589 b .__after_prom_start
1590
1591 #ifdef CONFIG_PPC_MULTIPLATFORM
1592 _STATIC(__boot_from_prom)
1593 /* Save parameters */
1594 mr r31,r3
1595 mr r30,r4
1596 mr r29,r5
1597 mr r28,r6
1598 mr r27,r7
1599
1600 /*
1601 * Align the stack to 16-byte boundary
1602 * Depending on the size and layout of the ELF sections in the initial
1603 * boot binary, the stack pointer will be unalignet on PowerMac
1604 */
1605 rldicr r1,r1,0,59
1606
1607 /* Make sure we are running in 64 bits mode */
1608 bl .enable_64b_mode
1609
1610 /* put a relocation offset into r3 */
1611 bl .reloc_offset
1612
1613 LOAD_REG_IMMEDIATE(r2,__toc_start)
1614 addi r2,r2,0x4000
1615 addi r2,r2,0x4000
1616
1617 /* Relocate the TOC from a virt addr to a real addr */
1618 add r2,r2,r3
1619
1620 /* Restore parameters */
1621 mr r3,r31
1622 mr r4,r30
1623 mr r5,r29
1624 mr r6,r28
1625 mr r7,r27
1626
1627 /* Do all of the interaction with OF client interface */
1628 bl .prom_init
1629 /* We never return */
1630 trap
1631 #endif
1632
1633 /*
1634 * At this point, r3 contains the physical address we are running at,
1635 * returned by prom_init()
1636 */
1637 _STATIC(__after_prom_start)
1638
1639 /*
1640 * We need to run with __start at physical address PHYSICAL_START.
1641 * This will leave some code in the first 256B of
1642 * real memory, which are reserved for software use.
1643 * The remainder of the first page is loaded with the fixed
1644 * interrupt vectors. The next two pages are filled with
1645 * unknown exception placeholders.
1646 *
1647 * Note: This process overwrites the OF exception vectors.
1648 * r26 == relocation offset
1649 * r27 == KERNELBASE
1650 */
1651 bl .reloc_offset
1652 mr r26,r3
1653 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1654
1655 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1656
1657 // XXX FIXME: Use phys returned by OF (r30)
1658 add r4,r27,r26 /* source addr */
1659 /* current address of _start */
1660 /* i.e. where we are running */
1661 /* the source addr */
1662
1663 cmpdi r4,0 /* In some cases the loader may */
1664 beq .start_here_multiplatform /* have already put us at zero */
1665 /* so we can skip the copy. */
1666 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1667 sub r5,r5,r27
1668
1669 li r6,0x100 /* Start offset, the first 0x100 */
1670 /* bytes were copied earlier. */
1671
1672 bl .copy_and_flush /* copy the first n bytes */
1673 /* this includes the code being */
1674 /* executed here. */
1675
1676 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1677 mtctr r0 /* that we just made/relocated */
1678 bctr
1679
1680 4: LOAD_REG_IMMEDIATE(r5,klimit)
1681 add r5,r5,r26
1682 ld r5,0(r5) /* get the value of klimit */
1683 sub r5,r5,r27
1684 bl .copy_and_flush /* copy the rest */
1685 b .start_here_multiplatform
1686
1687 #endif /* CONFIG_PPC_MULTIPLATFORM */
1688
1689 /*
1690 * Copy routine used to copy the kernel to start at physical address 0
1691 * and flush and invalidate the caches as needed.
1692 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1693 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1694 *
1695 * Note: this routine *only* clobbers r0, r6 and lr
1696 */
1697 _GLOBAL(copy_and_flush)
1698 addi r5,r5,-8
1699 addi r6,r6,-8
1700 4: li r0,16 /* Use the least common */
1701 /* denominator cache line */
1702 /* size. This results in */
1703 /* extra cache line flushes */
1704 /* but operation is correct. */
1705 /* Can't get cache line size */
1706 /* from NACA as it is being */
1707 /* moved too. */
1708
1709 mtctr r0 /* put # words/line in ctr */
1710 3: addi r6,r6,8 /* copy a cache line */
1711 ldx r0,r6,r4
1712 stdx r0,r6,r3
1713 bdnz 3b
1714 dcbst r6,r3 /* write it to memory */
1715 sync
1716 icbi r6,r3 /* flush the icache line */
1717 cmpld 0,r6,r5
1718 blt 4b
1719 sync
1720 addi r5,r5,8
1721 addi r6,r6,8
1722 blr
1723
1724 .align 8
1725 copy_to_here:
1726
1727 #ifdef CONFIG_SMP
1728 #ifdef CONFIG_PPC_PMAC
1729 /*
1730 * On PowerMac, secondary processors starts from the reset vector, which
1731 * is temporarily turned into a call to one of the functions below.
1732 */
1733 .section ".text";
1734 .align 2 ;
1735
1736 .globl __secondary_start_pmac_0
1737 __secondary_start_pmac_0:
1738 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1739 li r24,0
1740 b 1f
1741 li r24,1
1742 b 1f
1743 li r24,2
1744 b 1f
1745 li r24,3
1746 1:
1747
1748 _GLOBAL(pmac_secondary_start)
1749 /* turn on 64-bit mode */
1750 bl .enable_64b_mode
1751 isync
1752
1753 /* Copy some CPU settings from CPU 0 */
1754 bl .__restore_cpu_setup
1755
1756 /* pSeries do that early though I don't think we really need it */
1757 mfmsr r3
1758 ori r3,r3,MSR_RI
1759 mtmsrd r3 /* RI on */
1760
1761 /* Set up a paca value for this processor. */
1762 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1763 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1764 add r13,r13,r4 /* for this processor. */
1765 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1766
1767 /* Create a temp kernel stack for use before relocation is on. */
1768 ld r1,PACAEMERGSP(r13)
1769 subi r1,r1,STACK_FRAME_OVERHEAD
1770
1771 b .__secondary_start
1772
1773 #endif /* CONFIG_PPC_PMAC */
1774
1775 /*
1776 * This function is called after the master CPU has released the
1777 * secondary processors. The execution environment is relocation off.
1778 * The paca for this processor has the following fields initialized at
1779 * this point:
1780 * 1. Processor number
1781 * 2. Segment table pointer (virtual address)
1782 * On entry the following are set:
1783 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1784 * r24 = cpu# (in Linux terms)
1785 * r13 = paca virtual address
1786 * SPRG3 = paca virtual address
1787 */
1788 _GLOBAL(__secondary_start)
1789 /* Set thread priority to MEDIUM */
1790 HMT_MEDIUM
1791
1792 /* Load TOC */
1793 ld r2,PACATOC(r13)
1794
1795 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1796 bl .early_setup_secondary
1797
1798 /* Initialize the kernel stack. Just a repeat for iSeries. */
1799 LOAD_REG_ADDR(r3, current_set)
1800 sldi r28,r24,3 /* get current_set[cpu#] */
1801 ldx r1,r3,r28
1802 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1803 std r1,PACAKSAVE(r13)
1804
1805 /* Clear backchain so we get nice backtraces */
1806 li r7,0
1807 mtlr r7
1808
1809 /* enable MMU and jump to start_secondary */
1810 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1811 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1812 #ifdef DO_SOFT_DISABLE
1813 ori r4,r4,MSR_EE
1814 #endif
1815 mtspr SPRN_SRR0,r3
1816 mtspr SPRN_SRR1,r4
1817 rfid
1818 b . /* prevent speculative execution */
1819
1820 /*
1821 * Running with relocation on at this point. All we want to do is
1822 * zero the stack back-chain pointer before going into C code.
1823 */
1824 _GLOBAL(start_secondary_prolog)
1825 li r3,0
1826 std r3,0(r1) /* Zero the stack frame pointer */
1827 bl .start_secondary
1828 b .
1829 #endif
1830
1831 /*
1832 * This subroutine clobbers r11 and r12
1833 */
1834 _GLOBAL(enable_64b_mode)
1835 mfmsr r11 /* grab the current MSR */
1836 li r12,1
1837 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1838 or r11,r11,r12
1839 li r12,1
1840 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1841 or r11,r11,r12
1842 mtmsrd r11
1843 isync
1844 blr
1845
1846 #ifdef CONFIG_PPC_MULTIPLATFORM
1847 /*
1848 * This is where the main kernel code starts.
1849 */
1850 _STATIC(start_here_multiplatform)
1851 /* get a new offset, now that the kernel has moved. */
1852 bl .reloc_offset
1853 mr r26,r3
1854
1855 /* Clear out the BSS. It may have been done in prom_init,
1856 * already but that's irrelevant since prom_init will soon
1857 * be detached from the kernel completely. Besides, we need
1858 * to clear it now for kexec-style entry.
1859 */
1860 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1861 LOAD_REG_IMMEDIATE(r8,__bss_start)
1862 sub r11,r11,r8 /* bss size */
1863 addi r11,r11,7 /* round up to an even double word */
1864 rldicl. r11,r11,61,3 /* shift right by 3 */
1865 beq 4f
1866 addi r8,r8,-8
1867 li r0,0
1868 mtctr r11 /* zero this many doublewords */
1869 3: stdu r0,8(r8)
1870 bdnz 3b
1871 4:
1872
1873 mfmsr r6
1874 ori r6,r6,MSR_RI
1875 mtmsrd r6 /* RI on */
1876
1877 /* The following gets the stack and TOC set up with the regs */
1878 /* pointing to the real addr of the kernel stack. This is */
1879 /* all done to support the C function call below which sets */
1880 /* up the htab. This is done because we have relocated the */
1881 /* kernel but are still running in real mode. */
1882
1883 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1884 add r3,r3,r26
1885
1886 /* set up a stack pointer (physical address) */
1887 addi r1,r3,THREAD_SIZE
1888 li r0,0
1889 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1890
1891 /* set up the TOC (physical address) */
1892 LOAD_REG_IMMEDIATE(r2,__toc_start)
1893 addi r2,r2,0x4000
1894 addi r2,r2,0x4000
1895 add r2,r2,r26
1896
1897 LOAD_REG_IMMEDIATE(r3, cpu_specs)
1898 add r3,r3,r26
1899 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1900 add r4,r4,r26
1901 mr r5,r26
1902 bl .identify_cpu
1903
1904 /* Save some low level config HIDs of CPU0 to be copied to
1905 * other CPUs later on, or used for suspend/resume
1906 */
1907 bl .__save_cpu_setup
1908 sync
1909
1910 /* Do very early kernel initializations, including initial hash table,
1911 * stab and slb setup before we turn on relocation. */
1912
1913 /* Restore parameters passed from prom_init/kexec */
1914 mr r3,r31
1915 bl .early_setup
1916
1917 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1918 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1919 mtspr SPRN_SRR0,r3
1920 mtspr SPRN_SRR1,r4
1921 rfid
1922 b . /* prevent speculative execution */
1923 #endif /* CONFIG_PPC_MULTIPLATFORM */
1924
1925 /* This is where all platforms converge execution */
1926 _STATIC(start_here_common)
1927 /* relocation is on at this point */
1928
1929 /* The following code sets up the SP and TOC now that we are */
1930 /* running with translation enabled. */
1931
1932 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1933
1934 /* set up the stack */
1935 addi r1,r3,THREAD_SIZE
1936 li r0,0
1937 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1938
1939 /* Apply the CPUs-specific fixups (nop out sections not relevant
1940 * to this CPU
1941 */
1942 li r3,0
1943 bl .do_cpu_ftr_fixups
1944
1945 /* ptr to current */
1946 LOAD_REG_IMMEDIATE(r4, init_task)
1947 std r4,PACACURRENT(r13)
1948
1949 /* Load the TOC */
1950 ld r2,PACATOC(r13)
1951 std r1,PACAKSAVE(r13)
1952
1953 bl .setup_system
1954
1955 /* Load up the kernel context */
1956 5:
1957 #ifdef DO_SOFT_DISABLE
1958 li r5,0
1959 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1960 mfmsr r5
1961 ori r5,r5,MSR_EE /* Hard Enabled */
1962 mtmsrd r5
1963 #endif
1964
1965 bl .start_kernel
1966
1967 /* Not reached */
1968 BUG_OPCODE
1969
1970 /*
1971 * We put a few things here that have to be page-aligned.
1972 * This stuff goes at the beginning of the bss, which is page-aligned.
1973 */
1974 .section ".bss"
1975
1976 .align PAGE_SHIFT
1977
1978 .globl empty_zero_page
1979 empty_zero_page:
1980 .space PAGE_SIZE
1981
1982 .globl swapper_pg_dir
1983 swapper_pg_dir:
1984 .space PAGE_SIZE
1985
1986 /*
1987 * This space gets a copy of optional info passed to us by the bootstrap
1988 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1989 */
1990 .globl cmd_line
1991 cmd_line:
1992 .space COMMAND_LINE_SIZE
Linux kernel - Deliverables
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