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[deliverable/linux.git] / arch / powerpc / kernel / head_fsl_booke.S
1 /*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 */
32
33 #include <linux/threads.h>
34 #include <asm/processor.h>
35 #include <asm/page.h>
36 #include <asm/mmu.h>
37 #include <asm/pgtable.h>
38 #include <asm/cputable.h>
39 #include <asm/thread_info.h>
40 #include <asm/ppc_asm.h>
41 #include <asm/asm-offsets.h>
42 #include <asm/cache.h>
43 #include "head_booke.h"
44
45 /* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
48 *
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=128")
53 * r7 - End of kernel command line string
54 *
55 */
56 .section .text.head, "ax"
57 _ENTRY(_stext);
58 _ENTRY(_start);
59 /*
60 * Reserve a word at a fixed location to store the address
61 * of abatron_pteptrs
62 */
63 nop
64 /*
65 * Save parameters we are passed
66 */
67 mr r31,r3
68 mr r30,r4
69 mr r29,r5
70 mr r28,r6
71 mr r27,r7
72 li r25,0 /* phys kernel start (low) */
73 li r24,0 /* CPU number */
74 li r23,0 /* phys kernel start (high) */
75
76 /* We try to not make any assumptions about how the boot loader
77 * setup or used the TLBs. We invalidate all mappings from the
78 * boot loader and load a single entry in TLB1[0] to map the
79 * first 64M of kernel memory. Any boot info passed from the
80 * bootloader needs to live in this first 64M.
81 *
82 * Requirement on bootloader:
83 * - The page we're executing in needs to reside in TLB1 and
84 * have IPROT=1. If not an invalidate broadcast could
85 * evict the entry we're currently executing in.
86 *
87 * r3 = Index of TLB1 were executing in
88 * r4 = Current MSR[IS]
89 * r5 = Index of TLB1 temp mapping
90 *
91 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
92 * if needed
93 */
94
95 /* 1. Find the index of the entry we're executing in */
96 bl invstr /* Find our address */
97 invstr: mflr r6 /* Make it accessible */
98 mfmsr r7
99 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
100 mfspr r7, SPRN_PID0
101 slwi r7,r7,16
102 or r7,r7,r4
103 mtspr SPRN_MAS6,r7
104 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
105 #ifndef CONFIG_E200
106 mfspr r7,SPRN_MAS1
107 andis. r7,r7,MAS1_VALID@h
108 bne match_TLB
109 mfspr r7,SPRN_PID1
110 slwi r7,r7,16
111 or r7,r7,r4
112 mtspr SPRN_MAS6,r7
113 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
114 mfspr r7,SPRN_MAS1
115 andis. r7,r7,MAS1_VALID@h
116 bne match_TLB
117 mfspr r7, SPRN_PID2
118 slwi r7,r7,16
119 or r7,r7,r4
120 mtspr SPRN_MAS6,r7
121 tlbsx 0,r6 /* Fall through, we had to match */
122 #endif
123 match_TLB:
124 mfspr r7,SPRN_MAS0
125 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
126
127 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
128 oris r7,r7,MAS1_IPROT@h
129 mtspr SPRN_MAS1,r7
130 tlbwe
131
132 /* 2. Invalidate all entries except the entry we're executing in */
133 mfspr r9,SPRN_TLB1CFG
134 andi. r9,r9,0xfff
135 li r6,0 /* Set Entry counter to 0 */
136 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
137 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
138 mtspr SPRN_MAS0,r7
139 tlbre
140 mfspr r7,SPRN_MAS1
141 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
142 cmpw r3,r6
143 beq skpinv /* Dont update the current execution TLB */
144 mtspr SPRN_MAS1,r7
145 tlbwe
146 isync
147 skpinv: addi r6,r6,1 /* Increment */
148 cmpw r6,r9 /* Are we done? */
149 bne 1b /* If not, repeat */
150
151 /* Invalidate TLB0 */
152 li r6,0x04
153 tlbivax 0,r6
154 TLBSYNC
155 /* Invalidate TLB1 */
156 li r6,0x0c
157 tlbivax 0,r6
158 TLBSYNC
159
160 /* 3. Setup a temp mapping and jump to it */
161 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
162 addi r5, r5, 0x1
163 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
164 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
165 mtspr SPRN_MAS0,r7
166 tlbre
167
168 /* grab and fixup the RPN */
169 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
170 rlwinm r6,r6,25,27,30
171 li r8,-1
172 addi r6,r6,10
173 slw r6,r8,r6 /* convert to mask */
174
175 bl 1f /* Find our address */
176 1: mflr r7
177
178 mfspr r8,SPRN_MAS3
179 #ifdef CONFIG_PHYS_64BIT
180 mfspr r23,SPRN_MAS7
181 #endif
182 and r8,r6,r8
183 subfic r9,r6,-4096
184 and r9,r9,r7
185
186 or r25,r8,r9
187 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
188
189 /* Just modify the entry ID and EPN for the temp mapping */
190 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
191 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
192 mtspr SPRN_MAS0,r7
193 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
194 slwi r6,r6,12
195 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
196 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
197 mtspr SPRN_MAS1,r6
198 mfspr r6,SPRN_MAS2
199 li r7,0 /* temp EPN = 0 */
200 rlwimi r7,r6,0,20,31
201 mtspr SPRN_MAS2,r7
202 mtspr SPRN_MAS3,r8
203 tlbwe
204
205 xori r6,r4,1
206 slwi r6,r6,5 /* setup new context with other address space */
207 bl 1f /* Find our address */
208 1: mflr r9
209 rlwimi r7,r9,0,20,31
210 addi r7,r7,24
211 mtspr SPRN_SRR0,r7
212 mtspr SPRN_SRR1,r6
213 rfi
214
215 /* 4. Clear out PIDs & Search info */
216 li r6,0
217 mtspr SPRN_PID0,r6
218 #ifndef CONFIG_E200
219 mtspr SPRN_PID1,r6
220 mtspr SPRN_PID2,r6
221 #endif
222 mtspr SPRN_MAS6,r6
223
224 /* 5. Invalidate mapping we started in */
225 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
226 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
227 mtspr SPRN_MAS0,r7
228 tlbre
229 mfspr r6,SPRN_MAS1
230 rlwinm r6,r6,0,2,0 /* clear IPROT */
231 mtspr SPRN_MAS1,r6
232 tlbwe
233 /* Invalidate TLB1 */
234 li r9,0x0c
235 tlbivax 0,r9
236 TLBSYNC
237
238 /* 6. Setup KERNELBASE mapping in TLB1[0] */
239 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
240 mtspr SPRN_MAS0,r6
241 lis r6,(MAS1_VALID|MAS1_IPROT)@h
242 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
243 mtspr SPRN_MAS1,r6
244 li r7,0
245 lis r6,PAGE_OFFSET@h
246 ori r6,r6,PAGE_OFFSET@l
247 rlwimi r6,r7,0,20,31
248 mtspr SPRN_MAS2,r6
249 mtspr SPRN_MAS3,r8
250 tlbwe
251
252 /* 7. Jump to KERNELBASE mapping */
253 lis r6,KERNELBASE@h
254 ori r6,r6,KERNELBASE@l
255 rlwimi r6,r7,0,20,31
256 lis r7,MSR_KERNEL@h
257 ori r7,r7,MSR_KERNEL@l
258 bl 1f /* Find our address */
259 1: mflr r9
260 rlwimi r6,r9,0,20,31
261 addi r6,r6,24
262 mtspr SPRN_SRR0,r6
263 mtspr SPRN_SRR1,r7
264 rfi /* start execution out of TLB1[0] entry */
265
266 /* 8. Clear out the temp mapping */
267 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
268 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
269 mtspr SPRN_MAS0,r7
270 tlbre
271 mfspr r8,SPRN_MAS1
272 rlwinm r8,r8,0,2,0 /* clear IPROT */
273 mtspr SPRN_MAS1,r8
274 tlbwe
275 /* Invalidate TLB1 */
276 li r9,0x0c
277 tlbivax 0,r9
278 TLBSYNC
279
280 /* Establish the interrupt vector offsets */
281 SET_IVOR(0, CriticalInput);
282 SET_IVOR(1, MachineCheck);
283 SET_IVOR(2, DataStorage);
284 SET_IVOR(3, InstructionStorage);
285 SET_IVOR(4, ExternalInput);
286 SET_IVOR(5, Alignment);
287 SET_IVOR(6, Program);
288 SET_IVOR(7, FloatingPointUnavailable);
289 SET_IVOR(8, SystemCall);
290 SET_IVOR(9, AuxillaryProcessorUnavailable);
291 SET_IVOR(10, Decrementer);
292 SET_IVOR(11, FixedIntervalTimer);
293 SET_IVOR(12, WatchdogTimer);
294 SET_IVOR(13, DataTLBError);
295 SET_IVOR(14, InstructionTLBError);
296 SET_IVOR(15, DebugDebug);
297 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
298 SET_IVOR(15, DebugCrit);
299 #endif
300 SET_IVOR(32, SPEUnavailable);
301 SET_IVOR(33, SPEFloatingPointData);
302 SET_IVOR(34, SPEFloatingPointRound);
303 #ifndef CONFIG_E200
304 SET_IVOR(35, PerformanceMonitor);
305 #endif
306 #ifdef CONFIG_PPC_E500MC
307 SET_IVOR(36, Doorbell);
308 #endif
309
310 /* Establish the interrupt vector base */
311 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
312 mtspr SPRN_IVPR,r4
313
314 /* Setup the defaults for TLB entries */
315 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
316 #ifdef CONFIG_E200
317 oris r2,r2,MAS4_TLBSELD(1)@h
318 #endif
319 mtspr SPRN_MAS4, r2
320
321 #if 0
322 /* Enable DOZE */
323 mfspr r2,SPRN_HID0
324 oris r2,r2,HID0_DOZE@h
325 mtspr SPRN_HID0, r2
326 #endif
327 #ifdef CONFIG_E200
328 /* enable dedicated debug exception handling resources (Debug APU) */
329 mfspr r2,SPRN_HID0
330 ori r2,r2,HID0_DAPUEN@l
331 mtspr SPRN_HID0,r2
332 #endif
333
334 #if !defined(CONFIG_BDI_SWITCH)
335 /*
336 * The Abatron BDI JTAG debugger does not tolerate others
337 * mucking with the debug registers.
338 */
339 lis r2,DBCR0_IDM@h
340 mtspr SPRN_DBCR0,r2
341 isync
342 /* clear any residual debug events */
343 li r2,-1
344 mtspr SPRN_DBSR,r2
345 #endif
346
347 /*
348 * This is where the main kernel code starts.
349 */
350
351 /* ptr to current */
352 lis r2,init_task@h
353 ori r2,r2,init_task@l
354
355 /* ptr to current thread */
356 addi r4,r2,THREAD /* init task's THREAD */
357 mtspr SPRN_SPRG3,r4
358
359 /* stack */
360 lis r1,init_thread_union@h
361 ori r1,r1,init_thread_union@l
362 li r0,0
363 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
364
365 bl early_init
366
367 #ifdef CONFIG_RELOCATABLE
368 lis r3,kernstart_addr@ha
369 la r3,kernstart_addr@l(r3)
370 #ifdef CONFIG_PHYS_64BIT
371 stw r23,0(r3)
372 stw r25,4(r3)
373 #else
374 stw r25,0(r3)
375 #endif
376 #endif
377
378 mfspr r3,SPRN_TLB1CFG
379 andi. r3,r3,0xfff
380 lis r4,num_tlbcam_entries@ha
381 stw r3,num_tlbcam_entries@l(r4)
382 /*
383 * Decide what sort of machine this is and initialize the MMU.
384 */
385 mr r3,r31
386 mr r4,r30
387 mr r5,r29
388 mr r6,r28
389 mr r7,r27
390 bl machine_init
391 bl MMU_init
392
393 /* Setup PTE pointers for the Abatron bdiGDB */
394 lis r6, swapper_pg_dir@h
395 ori r6, r6, swapper_pg_dir@l
396 lis r5, abatron_pteptrs@h
397 ori r5, r5, abatron_pteptrs@l
398 lis r4, KERNELBASE@h
399 ori r4, r4, KERNELBASE@l
400 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
401 stw r6, 0(r5)
402
403 /* Let's move on */
404 lis r4,start_kernel@h
405 ori r4,r4,start_kernel@l
406 lis r3,MSR_KERNEL@h
407 ori r3,r3,MSR_KERNEL@l
408 mtspr SPRN_SRR0,r4
409 mtspr SPRN_SRR1,r3
410 rfi /* change context and jump to start_kernel */
411
412 /* Macros to hide the PTE size differences
413 *
414 * FIND_PTE -- walks the page tables given EA & pgdir pointer
415 * r10 -- EA of fault
416 * r11 -- PGDIR pointer
417 * r12 -- free
418 * label 2: is the bailout case
419 *
420 * if we find the pte (fall through):
421 * r11 is low pte word
422 * r12 is pointer to the pte
423 */
424 #ifdef CONFIG_PTE_64BIT
425 #define FIND_PTE \
426 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
427 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
428 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
429 beq 2f; /* Bail if no table */ \
430 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
431 lwz r11, 4(r12); /* Get pte entry */
432 #else
433 #define FIND_PTE \
434 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
435 lwz r11, 0(r11); /* Get L1 entry */ \
436 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
437 beq 2f; /* Bail if no table */ \
438 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
439 lwz r11, 0(r12); /* Get Linux PTE */
440 #endif
441
442 /*
443 * Interrupt vector entry code
444 *
445 * The Book E MMUs are always on so we don't need to handle
446 * interrupts in real mode as with previous PPC processors. In
447 * this case we handle interrupts in the kernel virtual address
448 * space.
449 *
450 * Interrupt vectors are dynamically placed relative to the
451 * interrupt prefix as determined by the address of interrupt_base.
452 * The interrupt vectors offsets are programmed using the labels
453 * for each interrupt vector entry.
454 *
455 * Interrupt vectors must be aligned on a 16 byte boundary.
456 * We align on a 32 byte cache line boundary for good measure.
457 */
458
459 interrupt_base:
460 /* Critical Input Interrupt */
461 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
462
463 /* Machine Check Interrupt */
464 #ifdef CONFIG_E200
465 /* no RFMCI, MCSRRs on E200 */
466 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
467 #else
468 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
469 #endif
470
471 /* Data Storage Interrupt */
472 START_EXCEPTION(DataStorage)
473 NORMAL_EXCEPTION_PROLOG
474 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
475 stw r5,_ESR(r11)
476 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
477 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
478 bne 1f
479 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
480 1:
481 addi r3,r1,STACK_FRAME_OVERHEAD
482 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
483
484 /* Instruction Storage Interrupt */
485 INSTRUCTION_STORAGE_EXCEPTION
486
487 /* External Input Interrupt */
488 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
489
490 /* Alignment Interrupt */
491 ALIGNMENT_EXCEPTION
492
493 /* Program Interrupt */
494 PROGRAM_EXCEPTION
495
496 /* Floating Point Unavailable Interrupt */
497 #ifdef CONFIG_PPC_FPU
498 FP_UNAVAILABLE_EXCEPTION
499 #else
500 #ifdef CONFIG_E200
501 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
502 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
503 #else
504 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
505 #endif
506 #endif
507
508 /* System Call Interrupt */
509 START_EXCEPTION(SystemCall)
510 NORMAL_EXCEPTION_PROLOG
511 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
512
513 /* Auxillary Processor Unavailable Interrupt */
514 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
515
516 /* Decrementer Interrupt */
517 DECREMENTER_EXCEPTION
518
519 /* Fixed Internal Timer Interrupt */
520 /* TODO: Add FIT support */
521 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
522
523 /* Watchdog Timer Interrupt */
524 #ifdef CONFIG_BOOKE_WDT
525 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
526 #else
527 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
528 #endif
529
530 /* Data TLB Error Interrupt */
531 START_EXCEPTION(DataTLBError)
532 mtspr SPRN_SPRG0, r10 /* Save some working registers */
533 mtspr SPRN_SPRG1, r11
534 mtspr SPRN_SPRG4W, r12
535 mtspr SPRN_SPRG5W, r13
536 mfcr r11
537 mtspr SPRN_SPRG7W, r11
538 mfspr r10, SPRN_DEAR /* Get faulting address */
539
540 /* If we are faulting a kernel address, we have to use the
541 * kernel page tables.
542 */
543 lis r11, PAGE_OFFSET@h
544 cmplw 5, r10, r11
545 blt 5, 3f
546 lis r11, swapper_pg_dir@h
547 ori r11, r11, swapper_pg_dir@l
548
549 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
550 rlwinm r12,r12,0,16,1
551 mtspr SPRN_MAS1,r12
552
553 b 4f
554
555 /* Get the PGD for the current thread */
556 3:
557 mfspr r11,SPRN_SPRG3
558 lwz r11,PGDIR(r11)
559
560 4:
561 /* Mask of required permission bits. Note that while we
562 * do copy ESR:ST to _PAGE_RW position as trying to write
563 * to an RO page is pretty common, we don't do it with
564 * _PAGE_DIRTY. We could do it, but it's a fairly rare
565 * event so I'd rather take the overhead when it happens
566 * rather than adding an instruction here. We should measure
567 * whether the whole thing is worth it in the first place
568 * as we could avoid loading SPRN_ESR completely in the first
569 * place...
570 *
571 * TODO: Is it worth doing that mfspr & rlwimi in the first
572 * place or can we save a couple of instructions here ?
573 */
574 mfspr r12,SPRN_ESR
575 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
576 rlwimi r13,r12,11,29,29
577
578 FIND_PTE
579 andc. r13,r13,r11 /* Check permission */
580
581 #ifdef CONFIG_PTE_64BIT
582 #ifdef CONFIG_SMP
583 subf r10,r11,r12 /* create false data dep */
584 lwzx r13,r11,r10 /* Get upper pte bits */
585 #else
586 lwz r13,0(r12) /* Get upper pte bits */
587 #endif
588 #endif
589
590 bne 2f /* Bail if permission/valid mismach */
591
592 /* Jump to common tlb load */
593 b finish_tlb_load
594 2:
595 /* The bailout. Restore registers to pre-exception conditions
596 * and call the heavyweights to help us out.
597 */
598 mfspr r11, SPRN_SPRG7R
599 mtcr r11
600 mfspr r13, SPRN_SPRG5R
601 mfspr r12, SPRN_SPRG4R
602 mfspr r11, SPRN_SPRG1
603 mfspr r10, SPRN_SPRG0
604 b DataStorage
605
606 /* Instruction TLB Error Interrupt */
607 /*
608 * Nearly the same as above, except we get our
609 * information from different registers and bailout
610 * to a different point.
611 */
612 START_EXCEPTION(InstructionTLBError)
613 mtspr SPRN_SPRG0, r10 /* Save some working registers */
614 mtspr SPRN_SPRG1, r11
615 mtspr SPRN_SPRG4W, r12
616 mtspr SPRN_SPRG5W, r13
617 mfcr r11
618 mtspr SPRN_SPRG7W, r11
619 mfspr r10, SPRN_SRR0 /* Get faulting address */
620
621 /* If we are faulting a kernel address, we have to use the
622 * kernel page tables.
623 */
624 lis r11, PAGE_OFFSET@h
625 cmplw 5, r10, r11
626 blt 5, 3f
627 lis r11, swapper_pg_dir@h
628 ori r11, r11, swapper_pg_dir@l
629
630 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
631 rlwinm r12,r12,0,16,1
632 mtspr SPRN_MAS1,r12
633
634 b 4f
635
636 /* Get the PGD for the current thread */
637 3:
638 mfspr r11,SPRN_SPRG3
639 lwz r11,PGDIR(r11)
640
641 4:
642 /* Make up the required permissions */
643 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
644
645 FIND_PTE
646 andc. r13,r13,r11 /* Check permission */
647
648 #ifdef CONFIG_PTE_64BIT
649 #ifdef CONFIG_SMP
650 subf r10,r11,r12 /* create false data dep */
651 lwzx r13,r11,r10 /* Get upper pte bits */
652 #else
653 lwz r13,0(r12) /* Get upper pte bits */
654 #endif
655 #endif
656
657 bne 2f /* Bail if permission mismach */
658
659 #ifdef CONFIG_PTE_64BIT
660 lwz r13,0(r12)
661 #endif
662
663 /* Jump to common TLB load point */
664 b finish_tlb_load
665
666 2:
667 /* The bailout. Restore registers to pre-exception conditions
668 * and call the heavyweights to help us out.
669 */
670 mfspr r11, SPRN_SPRG7R
671 mtcr r11
672 mfspr r13, SPRN_SPRG5R
673 mfspr r12, SPRN_SPRG4R
674 mfspr r11, SPRN_SPRG1
675 mfspr r10, SPRN_SPRG0
676 b InstructionStorage
677
678 #ifdef CONFIG_SPE
679 /* SPE Unavailable */
680 START_EXCEPTION(SPEUnavailable)
681 NORMAL_EXCEPTION_PROLOG
682 bne load_up_spe
683 addi r3,r1,STACK_FRAME_OVERHEAD
684 EXC_XFER_EE_LITE(0x2010, KernelSPE)
685 #else
686 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
687 #endif /* CONFIG_SPE */
688
689 /* SPE Floating Point Data */
690 #ifdef CONFIG_SPE
691 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
692 #else
693 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
694 #endif /* CONFIG_SPE */
695
696 /* SPE Floating Point Round */
697 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
698
699 /* Performance Monitor */
700 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
701
702 #ifdef CONFIG_PPC_E500MC
703 EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE)
704 #endif
705
706 /* Debug Interrupt */
707 DEBUG_DEBUG_EXCEPTION
708 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
709 DEBUG_CRIT_EXCEPTION
710 #endif
711
712 /*
713 * Local functions
714 */
715
716 /*
717 * Both the instruction and data TLB miss get to this
718 * point to load the TLB.
719 * r10 - available to use
720 * r11 - TLB (info from Linux PTE)
721 * r12 - available to use
722 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
723 * CR5 - results of addr >= PAGE_OFFSET
724 * MAS0, MAS1 - loaded with proper value when we get here
725 * MAS2, MAS3 - will need additional info from Linux PTE
726 * Upon exit, we reload everything and RFI.
727 */
728 finish_tlb_load:
729 /*
730 * We set execute, because we don't have the granularity to
731 * properly set this at the page level (Linux problem).
732 * Many of these bits are software only. Bits we don't set
733 * here we (properly should) assume have the appropriate value.
734 */
735
736 mfspr r12, SPRN_MAS2
737 #ifdef CONFIG_PTE_64BIT
738 rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
739 #else
740 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
741 #endif
742 mtspr SPRN_MAS2, r12
743
744 li r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
745 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
746 and r12, r11, r10
747 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
748 slwi r10, r12, 1
749 or r10, r10, r12
750 iseleq r12, r12, r10
751
752 #ifdef CONFIG_PTE_64BIT
753 2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
754 rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */
755 mtspr SPRN_MAS3, r12
756 BEGIN_FTR_SECTION
757 srwi r10, r13, 8 /* grab RPN[8:31] */
758 mtspr SPRN_MAS7, r10
759 END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
760 #else
761 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
762 mtspr SPRN_MAS3, r11
763 #endif
764 #ifdef CONFIG_E200
765 /* Round robin TLB1 entries assignment */
766 mfspr r12, SPRN_MAS0
767
768 /* Extract TLB1CFG(NENTRY) */
769 mfspr r11, SPRN_TLB1CFG
770 andi. r11, r11, 0xfff
771
772 /* Extract MAS0(NV) */
773 andi. r13, r12, 0xfff
774 addi r13, r13, 1
775 cmpw 0, r13, r11
776 addi r12, r12, 1
777
778 /* check if we need to wrap */
779 blt 7f
780
781 /* wrap back to first free tlbcam entry */
782 lis r13, tlbcam_index@ha
783 lwz r13, tlbcam_index@l(r13)
784 rlwimi r12, r13, 0, 20, 31
785 7:
786 mtspr SPRN_MAS0,r12
787 #endif /* CONFIG_E200 */
788
789 tlbwe
790
791 /* Done...restore registers and get out of here. */
792 mfspr r11, SPRN_SPRG7R
793 mtcr r11
794 mfspr r13, SPRN_SPRG5R
795 mfspr r12, SPRN_SPRG4R
796 mfspr r11, SPRN_SPRG1
797 mfspr r10, SPRN_SPRG0
798 rfi /* Force context change */
799
800 #ifdef CONFIG_SPE
801 /* Note that the SPE support is closely modeled after the AltiVec
802 * support. Changes to one are likely to be applicable to the
803 * other! */
804 load_up_spe:
805 /*
806 * Disable SPE for the task which had SPE previously,
807 * and save its SPE registers in its thread_struct.
808 * Enables SPE for use in the kernel on return.
809 * On SMP we know the SPE units are free, since we give it up every
810 * switch. -- Kumar
811 */
812 mfmsr r5
813 oris r5,r5,MSR_SPE@h
814 mtmsr r5 /* enable use of SPE now */
815 isync
816 /*
817 * For SMP, we don't do lazy SPE switching because it just gets too
818 * horrendously complex, especially when a task switches from one CPU
819 * to another. Instead we call giveup_spe in switch_to.
820 */
821 #ifndef CONFIG_SMP
822 lis r3,last_task_used_spe@ha
823 lwz r4,last_task_used_spe@l(r3)
824 cmpi 0,r4,0
825 beq 1f
826 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
827 SAVE_32EVRS(0,r10,r4)
828 evxor evr10, evr10, evr10 /* clear out evr10 */
829 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
830 li r5,THREAD_ACC
831 evstddx evr10, r4, r5 /* save off accumulator */
832 lwz r5,PT_REGS(r4)
833 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
834 lis r10,MSR_SPE@h
835 andc r4,r4,r10 /* disable SPE for previous task */
836 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
837 1:
838 #endif /* !CONFIG_SMP */
839 /* enable use of SPE after return */
840 oris r9,r9,MSR_SPE@h
841 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
842 li r4,1
843 li r10,THREAD_ACC
844 stw r4,THREAD_USED_SPE(r5)
845 evlddx evr4,r10,r5
846 evmra evr4,evr4
847 REST_32EVRS(0,r10,r5)
848 #ifndef CONFIG_SMP
849 subi r4,r5,THREAD
850 stw r4,last_task_used_spe@l(r3)
851 #endif /* !CONFIG_SMP */
852 /* restore registers and return */
853 2: REST_4GPRS(3, r11)
854 lwz r10,_CCR(r11)
855 REST_GPR(1, r11)
856 mtcr r10
857 lwz r10,_LINK(r11)
858 mtlr r10
859 REST_GPR(10, r11)
860 mtspr SPRN_SRR1,r9
861 mtspr SPRN_SRR0,r12
862 REST_GPR(9, r11)
863 REST_GPR(12, r11)
864 lwz r11,GPR11(r11)
865 rfi
866
867 /*
868 * SPE unavailable trap from kernel - print a message, but let
869 * the task use SPE in the kernel until it returns to user mode.
870 */
871 KernelSPE:
872 lwz r3,_MSR(r1)
873 oris r3,r3,MSR_SPE@h
874 stw r3,_MSR(r1) /* enable use of SPE after return */
875 lis r3,87f@h
876 ori r3,r3,87f@l
877 mr r4,r2 /* current */
878 lwz r5,_NIP(r1)
879 bl printk
880 b ret_from_except
881 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
882 .align 4,0
883
884 #endif /* CONFIG_SPE */
885
886 /*
887 * Global functions
888 */
889
890 /*
891 * extern void loadcam_entry(unsigned int index)
892 *
893 * Load TLBCAM[index] entry in to the L2 CAM MMU
894 */
895 _GLOBAL(loadcam_entry)
896 lis r4,TLBCAM@ha
897 addi r4,r4,TLBCAM@l
898 mulli r5,r3,20
899 add r3,r5,r4
900 lwz r4,0(r3)
901 mtspr SPRN_MAS0,r4
902 lwz r4,4(r3)
903 mtspr SPRN_MAS1,r4
904 lwz r4,8(r3)
905 mtspr SPRN_MAS2,r4
906 lwz r4,12(r3)
907 mtspr SPRN_MAS3,r4
908 tlbwe
909 isync
910 blr
911
912 /*
913 * extern void giveup_altivec(struct task_struct *prev)
914 *
915 * The e500 core does not have an AltiVec unit.
916 */
917 _GLOBAL(giveup_altivec)
918 blr
919
920 #ifdef CONFIG_SPE
921 /*
922 * extern void giveup_spe(struct task_struct *prev)
923 *
924 */
925 _GLOBAL(giveup_spe)
926 mfmsr r5
927 oris r5,r5,MSR_SPE@h
928 mtmsr r5 /* enable use of SPE now */
929 isync
930 cmpi 0,r3,0
931 beqlr- /* if no previous owner, done */
932 addi r3,r3,THREAD /* want THREAD of task */
933 lwz r5,PT_REGS(r3)
934 cmpi 0,r5,0
935 SAVE_32EVRS(0, r4, r3)
936 evxor evr6, evr6, evr6 /* clear out evr6 */
937 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
938 li r4,THREAD_ACC
939 evstddx evr6, r4, r3 /* save off accumulator */
940 mfspr r6,SPRN_SPEFSCR
941 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
942 beq 1f
943 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
944 lis r3,MSR_SPE@h
945 andc r4,r4,r3 /* disable SPE for previous task */
946 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
947 1:
948 #ifndef CONFIG_SMP
949 li r5,0
950 lis r4,last_task_used_spe@ha
951 stw r5,last_task_used_spe@l(r4)
952 #endif /* !CONFIG_SMP */
953 blr
954 #endif /* CONFIG_SPE */
955
956 /*
957 * extern void giveup_fpu(struct task_struct *prev)
958 *
959 * Not all FSL Book-E cores have an FPU
960 */
961 #ifndef CONFIG_PPC_FPU
962 _GLOBAL(giveup_fpu)
963 blr
964 #endif
965
966 /*
967 * extern void abort(void)
968 *
969 * At present, this routine just applies a system reset.
970 */
971 _GLOBAL(abort)
972 li r13,0
973 mtspr SPRN_DBCR0,r13 /* disable all debug events */
974 isync
975 mfmsr r13
976 ori r13,r13,MSR_DE@l /* Enable Debug Events */
977 mtmsr r13
978 isync
979 mfspr r13,SPRN_DBCR0
980 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
981 mtspr SPRN_DBCR0,r13
982 isync
983
984 _GLOBAL(set_context)
985
986 #ifdef CONFIG_BDI_SWITCH
987 /* Context switch the PTE pointer for the Abatron BDI2000.
988 * The PGDIR is the second parameter.
989 */
990 lis r5, abatron_pteptrs@h
991 ori r5, r5, abatron_pteptrs@l
992 stw r4, 0x4(r5)
993 #endif
994 mtspr SPRN_PID,r3
995 isync /* Force context change */
996 blr
997
998 _GLOBAL(flush_dcache_L1)
999 mfspr r3,SPRN_L1CFG0
1000
1001 rlwinm r5,r3,9,3 /* Extract cache block size */
1002 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1003 * are currently defined.
1004 */
1005 li r4,32
1006 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1007 * log2(number of ways)
1008 */
1009 slw r5,r4,r5 /* r5 = cache block size */
1010
1011 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1012 mulli r7,r7,13 /* An 8-way cache will require 13
1013 * loads per set.
1014 */
1015 slw r7,r7,r6
1016
1017 /* save off HID0 and set DCFA */
1018 mfspr r8,SPRN_HID0
1019 ori r9,r8,HID0_DCFA@l
1020 mtspr SPRN_HID0,r9
1021 isync
1022
1023 lis r4,KERNELBASE@h
1024 mtctr r7
1025
1026 1: lwz r3,0(r4) /* Load... */
1027 add r4,r4,r5
1028 bdnz 1b
1029
1030 msync
1031 lis r4,KERNELBASE@h
1032 mtctr r7
1033
1034 1: dcbf 0,r4 /* ...and flush. */
1035 add r4,r4,r5
1036 bdnz 1b
1037
1038 /* restore HID0 */
1039 mtspr SPRN_HID0,r8
1040 isync
1041
1042 blr
1043
1044 /*
1045 * We put a few things here that have to be page-aligned. This stuff
1046 * goes at the beginning of the data segment, which is page-aligned.
1047 */
1048 .data
1049 .align 12
1050 .globl sdata
1051 sdata:
1052 .globl empty_zero_page
1053 empty_zero_page:
1054 .space 4096
1055 .globl swapper_pg_dir
1056 swapper_pg_dir:
1057 .space PGD_TABLE_SIZE
1058
1059 /*
1060 * Room for two PTE pointers, usually the kernel and current user pointers
1061 * to their respective root page table.
1062 */
1063 abatron_pteptrs:
1064 .space 8
Linux kernel - Deliverables
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