arch/powerpc/kernel/head_fsl_booke.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2004 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *    Copyright 2004 Freescale Semiconductor, Inc
  25  *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  */
  32
  33 #include <linux/threads.h>
  34 #include <asm/processor.h>
  35 #include <asm/page.h>
  36 #include <asm/mmu.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/cputable.h>
  39 #include <asm/thread_info.h>
  40 #include <asm/ppc_asm.h>
  41 #include <asm/asm-offsets.h>
  42 #include <asm/cache.h>
  43 #include "head_booke.h"
  44
  45 /* As with the other PowerPC ports, it is expected that when code
  46  * execution begins here, the following registers contain valid, yet
  47  * optional, information:
  48  *
  49  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  50  *   r4 - Starting address of the init RAM disk
  51  *   r5 - Ending address of the init RAM disk
  52  *   r6 - Start of kernel command line string (e.g. "mem=128")
  53  *   r7 - End of kernel command line string
  54  *
  55  */
  56         .section        .text.head, "ax"
  57 _ENTRY(_stext);
  58 _ENTRY(_start);
  59         /*
  60          * Reserve a word at a fixed location to store the address
  61          * of abatron_pteptrs
  62          */
  63         nop
  64 /*
  65  * Save parameters we are passed
  66  */
  67         mr      r31,r3
  68         mr      r30,r4
  69         mr      r29,r5
  70         mr      r28,r6
  71         mr      r27,r7
  72         li      r25,0           /* phys kernel start (low) */
  73         li      r24,0           /* CPU number */
  74         li      r23,0           /* phys kernel start (high) */
  75
  76 /* We try to not make any assumptions about how the boot loader
  77  * setup or used the TLBs.  We invalidate all mappings from the
  78  * boot loader and load a single entry in TLB1[0] to map the
  79  * first 64M of kernel memory.  Any boot info passed from the
  80  * bootloader needs to live in this first 64M.
  81  *
  82  * Requirement on bootloader:
  83  *  - The page we're executing in needs to reside in TLB1 and
  84  *    have IPROT=1.  If not an invalidate broadcast could
  85  *    evict the entry we're currently executing in.
  86  *
  87  *  r3 = Index of TLB1 were executing in
  88  *  r4 = Current MSR[IS]
  89  *  r5 = Index of TLB1 temp mapping
  90  *
  91  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
  92  * if needed
  93  */
  94
  95 _ENTRY(__early_start)
  96 /* 1. Find the index of the entry we're executing in */
  97         bl      invstr                          /* Find our address */
  98 invstr: mflr    r6                              /* Make it accessible */
  99         mfmsr   r7
 100         rlwinm  r4,r7,27,31,31                  /* extract MSR[IS] */
 101         mfspr   r7, SPRN_PID0
 102         slwi    r7,r7,16
 103         or      r7,r7,r4
 104         mtspr   SPRN_MAS6,r7
 105         tlbsx   0,r6                            /* search MSR[IS], SPID=PID0 */
 106         mfspr   r7,SPRN_MAS1
 107         andis.  r7,r7,MAS1_VALID@h
 108         bne     match_TLB
 109
 110         mfspr   r7,SPRN_MMUCFG
 111         rlwinm  r7,r7,21,28,31                  /* extract MMUCFG[NPIDS] */
 112         cmpwi   r7,3
 113         bne     match_TLB                       /* skip if NPIDS != 3 */
 114
 115         mfspr   r7,SPRN_PID1
 116         slwi    r7,r7,16
 117         or      r7,r7,r4
 118         mtspr   SPRN_MAS6,r7
 119         tlbsx   0,r6                            /* search MSR[IS], SPID=PID1 */
 120         mfspr   r7,SPRN_MAS1
 121         andis.  r7,r7,MAS1_VALID@h
 122         bne     match_TLB
 123         mfspr   r7, SPRN_PID2
 124         slwi    r7,r7,16
 125         or      r7,r7,r4
 126         mtspr   SPRN_MAS6,r7
 127         tlbsx   0,r6                            /* Fall through, we had to match */
 128
 129 match_TLB:
 130         mfspr   r7,SPRN_MAS0
 131         rlwinm  r3,r7,16,20,31                  /* Extract MAS0(Entry) */
 132
 133         mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
 134         oris    r7,r7,MAS1_IPROT@h
 135         mtspr   SPRN_MAS1,r7
 136         tlbwe
 137
 138 /* 2. Invalidate all entries except the entry we're executing in */
 139         mfspr   r9,SPRN_TLB1CFG
 140         andi.   r9,r9,0xfff
 141         li      r6,0                            /* Set Entry counter to 0 */
 142 1:      lis     r7,0x1000                       /* Set MAS0(TLBSEL) = 1 */
 143         rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
 144         mtspr   SPRN_MAS0,r7
 145         tlbre
 146         mfspr   r7,SPRN_MAS1
 147         rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
 148         cmpw    r3,r6
 149         beq     skpinv                          /* Dont update the current execution TLB */
 150         mtspr   SPRN_MAS1,r7
 151         tlbwe
 152         isync
 153 skpinv: addi    r6,r6,1                         /* Increment */
 154         cmpw    r6,r9                           /* Are we done? */
 155         bne     1b                              /* If not, repeat */
 156
 157         /* Invalidate TLB0 */
 158         li      r6,0x04
 159         tlbivax 0,r6
 160         TLBSYNC
 161         /* Invalidate TLB1 */
 162         li      r6,0x0c
 163         tlbivax 0,r6
 164         TLBSYNC
 165
 166 /* 3. Setup a temp mapping and jump to it */
 167         andi.   r5, r3, 0x1     /* Find an entry not used and is non-zero */
 168         addi    r5, r5, 0x1
 169         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 170         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 171         mtspr   SPRN_MAS0,r7
 172         tlbre
 173
 174         /* grab and fixup the RPN */
 175         mfspr   r6,SPRN_MAS1    /* extract MAS1[SIZE] */
 176         rlwinm  r6,r6,25,27,30
 177         li      r8,-1
 178         addi    r6,r6,10
 179         slw     r6,r8,r6        /* convert to mask */
 180
 181         bl      1f              /* Find our address */
 182 1:      mflr    r7
 183
 184         mfspr   r8,SPRN_MAS3
 185 #ifdef CONFIG_PHYS_64BIT
 186         mfspr   r23,SPRN_MAS7
 187 #endif
 188         and     r8,r6,r8
 189         subfic  r9,r6,-4096
 190         and     r9,r9,r7
 191
 192         or      r25,r8,r9
 193         ori     r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
 194
 195         /* Just modify the entry ID and EPN for the temp mapping */
 196         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 197         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 198         mtspr   SPRN_MAS0,r7
 199         xori    r6,r4,1         /* Setup TMP mapping in the other Address space */
 200         slwi    r6,r6,12
 201         oris    r6,r6,(MAS1_VALID|MAS1_IPROT)@h
 202         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 203         mtspr   SPRN_MAS1,r6
 204         mfspr   r6,SPRN_MAS2
 205         li      r7,0            /* temp EPN = 0 */
 206         rlwimi  r7,r6,0,20,31
 207         mtspr   SPRN_MAS2,r7
 208         mtspr   SPRN_MAS3,r8
 209         tlbwe
 210
 211         xori    r6,r4,1
 212         slwi    r6,r6,5         /* setup new context with other address space */
 213         bl      1f              /* Find our address */
 214 1:      mflr    r9
 215         rlwimi  r7,r9,0,20,31
 216         addi    r7,r7,24
 217         mtspr   SPRN_SRR0,r7
 218         mtspr   SPRN_SRR1,r6
 219         rfi
 220
 221 /* 4. Clear out PIDs & Search info */
 222         li      r6,0
 223         mtspr   SPRN_MAS6,r6
 224         mtspr   SPRN_PID0,r6
 225
 226         mfspr   r7,SPRN_MMUCFG
 227         rlwinm  r7,r7,21,28,31                  /* extract MMUCFG[NPIDS] */
 228         cmpwi   r7,3
 229         bne     2f                              /* skip if NPIDS != 3 */
 230
 231         mtspr   SPRN_PID1,r6
 232         mtspr   SPRN_PID2,r6
 233
 234 /* 5. Invalidate mapping we started in */
 235 2:
 236         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 237         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 238         mtspr   SPRN_MAS0,r7
 239         tlbre
 240         mfspr   r6,SPRN_MAS1
 241         rlwinm  r6,r6,0,2,0     /* clear IPROT */
 242         mtspr   SPRN_MAS1,r6
 243         tlbwe
 244         /* Invalidate TLB1 */
 245         li      r9,0x0c
 246         tlbivax 0,r9
 247         TLBSYNC
 248
 249 /* The mapping only needs to be cache-coherent on SMP */
 250 #ifdef CONFIG_SMP
 251 #define M_IF_SMP        MAS2_M
 252 #else
 253 #define M_IF_SMP        0
 254 #endif
 255
 256 /* 6. Setup KERNELBASE mapping in TLB1[0] */
 257         lis     r6,0x1000               /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
 258         mtspr   SPRN_MAS0,r6
 259         lis     r6,(MAS1_VALID|MAS1_IPROT)@h
 260         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
 261         mtspr   SPRN_MAS1,r6
 262         lis     r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@h
 263         ori     r6,r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@l
 264         mtspr   SPRN_MAS2,r6
 265         mtspr   SPRN_MAS3,r8
 266         tlbwe
 267
 268 /* 7. Jump to KERNELBASE mapping */
 269         lis     r6,(KERNELBASE & ~0xfff)@h
 270         ori     r6,r6,(KERNELBASE & ~0xfff)@l
 271         lis     r7,MSR_KERNEL@h
 272         ori     r7,r7,MSR_KERNEL@l
 273         bl      1f                      /* Find our address */
 274 1:      mflr    r9
 275         rlwimi  r6,r9,0,20,31
 276         addi    r6,r6,(2f - 1b)
 277         mtspr   SPRN_SRR0,r6
 278         mtspr   SPRN_SRR1,r7
 279         rfi                             /* start execution out of TLB1[0] entry */
 280
 281 /* 8. Clear out the temp mapping */
 282 2:      lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 283         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 284         mtspr   SPRN_MAS0,r7
 285         tlbre
 286         mfspr   r8,SPRN_MAS1
 287         rlwinm  r8,r8,0,2,0     /* clear IPROT */
 288         mtspr   SPRN_MAS1,r8
 289         tlbwe
 290         /* Invalidate TLB1 */
 291         li      r9,0x0c
 292         tlbivax 0,r9
 293         TLBSYNC
 294
 295         /* Establish the interrupt vector offsets */
 296         SET_IVOR(0,  CriticalInput);
 297         SET_IVOR(1,  MachineCheck);
 298         SET_IVOR(2,  DataStorage);
 299         SET_IVOR(3,  InstructionStorage);
 300         SET_IVOR(4,  ExternalInput);
 301         SET_IVOR(5,  Alignment);
 302         SET_IVOR(6,  Program);
 303         SET_IVOR(7,  FloatingPointUnavailable);
 304         SET_IVOR(8,  SystemCall);
 305         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 306         SET_IVOR(10, Decrementer);
 307         SET_IVOR(11, FixedIntervalTimer);
 308         SET_IVOR(12, WatchdogTimer);
 309         SET_IVOR(13, DataTLBError);
 310         SET_IVOR(14, InstructionTLBError);
 311         SET_IVOR(15, DebugCrit);
 312
 313         /* Establish the interrupt vector base */
 314         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 315         mtspr   SPRN_IVPR,r4
 316
 317         /* Setup the defaults for TLB entries */
 318         li      r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
 319 #ifdef CONFIG_E200
 320         oris    r2,r2,MAS4_TLBSELD(1)@h
 321 #endif
 322         mtspr   SPRN_MAS4, r2
 323
 324 #if 0
 325         /* Enable DOZE */
 326         mfspr   r2,SPRN_HID0
 327         oris    r2,r2,HID0_DOZE@h
 328         mtspr   SPRN_HID0, r2
 329 #endif
 330
 331 #if !defined(CONFIG_BDI_SWITCH)
 332         /*
 333          * The Abatron BDI JTAG debugger does not tolerate others
 334          * mucking with the debug registers.
 335          */
 336         lis     r2,DBCR0_IDM@h
 337         mtspr   SPRN_DBCR0,r2
 338         isync
 339         /* clear any residual debug events */
 340         li      r2,-1
 341         mtspr   SPRN_DBSR,r2
 342 #endif
 343
 344 #ifdef CONFIG_SMP
 345         /* Check to see if we're the second processor, and jump
 346          * to the secondary_start code if so
 347          */
 348         mfspr   r24,SPRN_PIR
 349         cmpwi   r24,0
 350         bne     __secondary_start
 351 #endif
 352
 353         /*
 354          * This is where the main kernel code starts.
 355          */
 356
 357         /* ptr to current */
 358         lis     r2,init_task@h
 359         ori     r2,r2,init_task@l
 360
 361         /* ptr to current thread */
 362         addi    r4,r2,THREAD    /* init task's THREAD */
 363         mtspr   SPRN_SPRG3,r4
 364
 365         /* stack */
 366         lis     r1,init_thread_union@h
 367         ori     r1,r1,init_thread_union@l
 368         li      r0,0
 369         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 370
 371         bl      early_init
 372
 373 #ifdef CONFIG_RELOCATABLE
 374         lis     r3,kernstart_addr@ha
 375         la      r3,kernstart_addr@l(r3)
 376 #ifdef CONFIG_PHYS_64BIT
 377         stw     r23,0(r3)
 378         stw     r25,4(r3)
 379 #else
 380         stw     r25,0(r3)
 381 #endif
 382 #endif
 383
 384 /*
 385  * Decide what sort of machine this is and initialize the MMU.
 386  */
 387         mr      r3,r31
 388         mr      r4,r30
 389         mr      r5,r29
 390         mr      r6,r28
 391         mr      r7,r27
 392         bl      machine_init
 393         bl      MMU_init
 394
 395         /* Setup PTE pointers for the Abatron bdiGDB */
 396         lis     r6, swapper_pg_dir@h
 397         ori     r6, r6, swapper_pg_dir@l
 398         lis     r5, abatron_pteptrs@h
 399         ori     r5, r5, abatron_pteptrs@l
 400         lis     r4, KERNELBASE@h
 401         ori     r4, r4, KERNELBASE@l
 402         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 403         stw     r6, 0(r5)
 404
 405         /* Let's move on */
 406         lis     r4,start_kernel@h
 407         ori     r4,r4,start_kernel@l
 408         lis     r3,MSR_KERNEL@h
 409         ori     r3,r3,MSR_KERNEL@l
 410         mtspr   SPRN_SRR0,r4
 411         mtspr   SPRN_SRR1,r3
 412         rfi                     /* change context and jump to start_kernel */
 413
 414 /* Macros to hide the PTE size differences
 415  *
 416  * FIND_PTE -- walks the page tables given EA & pgdir pointer
 417  *   r10 -- EA of fault
 418  *   r11 -- PGDIR pointer
 419  *   r12 -- free
 420  *   label 2: is the bailout case
 421  *
 422  * if we find the pte (fall through):
 423  *   r11 is low pte word
 424  *   r12 is pointer to the pte
 425  */
 426 #ifdef CONFIG_PTE_64BIT
 427 #define FIND_PTE        \
 428         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 429         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 430         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 431         beq     2f;                     /* Bail if no table */          \
 432         rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 433         lwz     r11, 4(r12);            /* Get pte entry */
 434 #else
 435 #define FIND_PTE        \
 436         rlwimi  r11, r10, 12, 20, 29;   /* Create L1 (pgdir/pmd) address */     \
 437         lwz     r11, 0(r11);            /* Get L1 entry */                      \
 438         rlwinm. r12, r11, 0, 0, 19;     /* Extract L2 (pte) base address */     \
 439         beq     2f;                     /* Bail if no table */                  \
 440         rlwimi  r12, r10, 22, 20, 29;   /* Compute PTE address */               \
 441         lwz     r11, 0(r12);            /* Get Linux PTE */
 442 #endif
 443
 444 /*
 445  * Interrupt vector entry code
 446  *
 447  * The Book E MMUs are always on so we don't need to handle
 448  * interrupts in real mode as with previous PPC processors. In
 449  * this case we handle interrupts in the kernel virtual address
 450  * space.
 451  *
 452  * Interrupt vectors are dynamically placed relative to the
 453  * interrupt prefix as determined by the address of interrupt_base.
 454  * The interrupt vectors offsets are programmed using the labels
 455  * for each interrupt vector entry.
 456  *
 457  * Interrupt vectors must be aligned on a 16 byte boundary.
 458  * We align on a 32 byte cache line boundary for good measure.
 459  */
 460
 461 interrupt_base:
 462         /* Critical Input Interrupt */
 463         CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
 464
 465         /* Machine Check Interrupt */
 466 #ifdef CONFIG_E200
 467         /* no RFMCI, MCSRRs on E200 */
 468         CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 469 #else
 470         MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 471 #endif
 472
 473         /* Data Storage Interrupt */
 474         START_EXCEPTION(DataStorage)
 475         NORMAL_EXCEPTION_PROLOG
 476         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 477         stw     r5,_ESR(r11)
 478         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 479         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
 480         bne     1f
 481         EXC_XFER_EE_LITE(0x0300, handle_page_fault)
 482 1:
 483         addi    r3,r1,STACK_FRAME_OVERHEAD
 484         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
 485
 486         /* Instruction Storage Interrupt */
 487         INSTRUCTION_STORAGE_EXCEPTION
 488
 489         /* External Input Interrupt */
 490         EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
 491
 492         /* Alignment Interrupt */
 493         ALIGNMENT_EXCEPTION
 494
 495         /* Program Interrupt */
 496         PROGRAM_EXCEPTION
 497
 498         /* Floating Point Unavailable Interrupt */
 499 #ifdef CONFIG_PPC_FPU
 500         FP_UNAVAILABLE_EXCEPTION
 501 #else
 502 #ifdef CONFIG_E200
 503         /* E200 treats 'normal' floating point instructions as FP Unavail exception */
 504         EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
 505 #else
 506         EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
 507 #endif
 508 #endif
 509
 510         /* System Call Interrupt */
 511         START_EXCEPTION(SystemCall)
 512         NORMAL_EXCEPTION_PROLOG
 513         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 514
 515         /* Auxillary Processor Unavailable Interrupt */
 516         EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
 517
 518         /* Decrementer Interrupt */
 519         DECREMENTER_EXCEPTION
 520
 521         /* Fixed Internal Timer Interrupt */
 522         /* TODO: Add FIT support */
 523         EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
 524
 525         /* Watchdog Timer Interrupt */
 526 #ifdef CONFIG_BOOKE_WDT
 527         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
 528 #else
 529         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
 530 #endif
 531
 532         /* Data TLB Error Interrupt */
 533         START_EXCEPTION(DataTLBError)
 534         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 535         mtspr   SPRN_SPRG1, r11
 536         mtspr   SPRN_SPRG4W, r12
 537         mtspr   SPRN_SPRG5W, r13
 538         mfcr    r11
 539         mtspr   SPRN_SPRG7W, r11
 540         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 541
 542         /* If we are faulting a kernel address, we have to use the
 543          * kernel page tables.
 544          */
 545         lis     r11, PAGE_OFFSET@h
 546         cmplw   5, r10, r11
 547         blt     5, 3f
 548         lis     r11, swapper_pg_dir@h
 549         ori     r11, r11, swapper_pg_dir@l
 550
 551         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 552         rlwinm  r12,r12,0,16,1
 553         mtspr   SPRN_MAS1,r12
 554
 555         b       4f
 556
 557         /* Get the PGD for the current thread */
 558 3:
 559         mfspr   r11,SPRN_SPRG3
 560         lwz     r11,PGDIR(r11)
 561
 562 4:
 563         /* Mask of required permission bits. Note that while we
 564          * do copy ESR:ST to _PAGE_RW position as trying to write
 565          * to an RO page is pretty common, we don't do it with
 566          * _PAGE_DIRTY. We could do it, but it's a fairly rare
 567          * event so I'd rather take the overhead when it happens
 568          * rather than adding an instruction here. We should measure
 569          * whether the whole thing is worth it in the first place
 570          * as we could avoid loading SPRN_ESR completely in the first
 571          * place...
 572          *
 573          * TODO: Is it worth doing that mfspr & rlwimi in the first
 574          *       place or can we save a couple of instructions here ?
 575          */
 576         mfspr   r12,SPRN_ESR
 577         li      r13,_PAGE_PRESENT|_PAGE_ACCESSED
 578         rlwimi  r13,r12,11,29,29
 579
 580         FIND_PTE
 581         andc.   r13,r13,r11             /* Check permission */
 582
 583 #ifdef CONFIG_PTE_64BIT
 584 #ifdef CONFIG_SMP
 585         subf    r10,r11,r12             /* create false data dep */
 586         lwzx    r13,r11,r10             /* Get upper pte bits */
 587 #else
 588         lwz     r13,0(r12)              /* Get upper pte bits */
 589 #endif
 590 #endif
 591
 592         bne     2f                      /* Bail if permission/valid mismach */
 593
 594         /* Jump to common tlb load */
 595         b       finish_tlb_load
 596 2:
 597         /* The bailout.  Restore registers to pre-exception conditions
 598          * and call the heavyweights to help us out.
 599          */
 600         mfspr   r11, SPRN_SPRG7R
 601         mtcr    r11
 602         mfspr   r13, SPRN_SPRG5R
 603         mfspr   r12, SPRN_SPRG4R
 604         mfspr   r11, SPRN_SPRG1
 605         mfspr   r10, SPRN_SPRG0
 606         b       DataStorage
 607
 608         /* Instruction TLB Error Interrupt */
 609         /*
 610          * Nearly the same as above, except we get our
 611          * information from different registers and bailout
 612          * to a different point.
 613          */
 614         START_EXCEPTION(InstructionTLBError)
 615         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 616         mtspr   SPRN_SPRG1, r11
 617         mtspr   SPRN_SPRG4W, r12
 618         mtspr   SPRN_SPRG5W, r13
 619         mfcr    r11
 620         mtspr   SPRN_SPRG7W, r11
 621         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 622
 623         /* If we are faulting a kernel address, we have to use the
 624          * kernel page tables.
 625          */
 626         lis     r11, PAGE_OFFSET@h
 627         cmplw   5, r10, r11
 628         blt     5, 3f
 629         lis     r11, swapper_pg_dir@h
 630         ori     r11, r11, swapper_pg_dir@l
 631
 632         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 633         rlwinm  r12,r12,0,16,1
 634         mtspr   SPRN_MAS1,r12
 635
 636         b       4f
 637
 638         /* Get the PGD for the current thread */
 639 3:
 640         mfspr   r11,SPRN_SPRG3
 641         lwz     r11,PGDIR(r11)
 642
 643 4:
 644         /* Make up the required permissions */
 645         li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
 646
 647         FIND_PTE
 648         andc.   r13,r13,r11             /* Check permission */
 649
 650 #ifdef CONFIG_PTE_64BIT
 651 #ifdef CONFIG_SMP
 652         subf    r10,r11,r12             /* create false data dep */
 653         lwzx    r13,r11,r10             /* Get upper pte bits */
 654 #else
 655         lwz     r13,0(r12)              /* Get upper pte bits */
 656 #endif
 657 #endif
 658
 659         bne     2f                      /* Bail if permission mismach */
 660
 661         /* Jump to common TLB load point */
 662         b       finish_tlb_load
 663
 664 2:
 665         /* The bailout.  Restore registers to pre-exception conditions
 666          * and call the heavyweights to help us out.
 667          */
 668         mfspr   r11, SPRN_SPRG7R
 669         mtcr    r11
 670         mfspr   r13, SPRN_SPRG5R
 671         mfspr   r12, SPRN_SPRG4R
 672         mfspr   r11, SPRN_SPRG1
 673         mfspr   r10, SPRN_SPRG0
 674         b       InstructionStorage
 675
 676 #ifdef CONFIG_SPE
 677         /* SPE Unavailable */
 678         START_EXCEPTION(SPEUnavailable)
 679         NORMAL_EXCEPTION_PROLOG
 680         bne     load_up_spe
 681         addi    r3,r1,STACK_FRAME_OVERHEAD
 682         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 683 #else
 684         EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
 685 #endif /* CONFIG_SPE */
 686
 687         /* SPE Floating Point Data */
 688 #ifdef CONFIG_SPE
 689         EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
 690
 691         /* SPE Floating Point Round */
 692         EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
 693 #else
 694         EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
 695         EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
 696 #endif /* CONFIG_SPE */
 697
 698         /* Performance Monitor */
 699         EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
 700
 701         EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_STD)
 702
 703         /* Debug Interrupt */
 704         DEBUG_DEBUG_EXCEPTION
 705         DEBUG_CRIT_EXCEPTION
 706
 707 /*
 708  * Local functions
 709  */
 710
 711 /*
 712  * Both the instruction and data TLB miss get to this
 713  * point to load the TLB.
 714  *      r10 - available to use
 715  *      r11 - TLB (info from Linux PTE)
 716  *      r12 - available to use
 717  *      r13 - upper bits of PTE (if PTE_64BIT) or available to use
 718  *      CR5 - results of addr >= PAGE_OFFSET
 719  *      MAS0, MAS1 - loaded with proper value when we get here
 720  *      MAS2, MAS3 - will need additional info from Linux PTE
 721  *      Upon exit, we reload everything and RFI.
 722  */
 723 finish_tlb_load:
 724         /*
 725          * We set execute, because we don't have the granularity to
 726          * properly set this at the page level (Linux problem).
 727          * Many of these bits are software only.  Bits we don't set
 728          * here we (properly should) assume have the appropriate value.
 729          */
 730
 731         mfspr   r12, SPRN_MAS2
 732 #ifdef CONFIG_PTE_64BIT
 733         rlwimi  r12, r11, 26, 24, 31    /* extract ...WIMGE from pte */
 734 #else
 735         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 736 #endif
 737 #ifdef CONFIG_SMP
 738         ori     r12, r12, MAS2_M
 739 #endif
 740         mtspr   SPRN_MAS2, r12
 741
 742         li      r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
 743         rlwimi  r10, r11, 31, 29, 29    /* extract _PAGE_DIRTY into SW */
 744         and     r12, r11, r10
 745         andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
 746         slwi    r10, r12, 1
 747         or      r10, r10, r12
 748         iseleq  r12, r12, r10
 749
 750 #ifdef CONFIG_PTE_64BIT
 751         rlwimi  r12, r13, 24, 0, 7      /* grab RPN[32:39] */
 752         rlwimi  r12, r11, 24, 8, 19     /* grab RPN[40:51] */
 753         mtspr   SPRN_MAS3, r12
 754 BEGIN_MMU_FTR_SECTION
 755         srwi    r10, r13, 8             /* grab RPN[8:31] */
 756         mtspr   SPRN_MAS7, r10
 757 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
 758 #else
 759         rlwimi  r11, r12, 0, 20, 31     /* Extract RPN from PTE and merge with perms */
 760         mtspr   SPRN_MAS3, r11
 761 #endif
 762 #ifdef CONFIG_E200
 763         /* Round robin TLB1 entries assignment */
 764         mfspr   r12, SPRN_MAS0
 765
 766         /* Extract TLB1CFG(NENTRY) */
 767         mfspr   r11, SPRN_TLB1CFG
 768         andi.   r11, r11, 0xfff
 769
 770         /* Extract MAS0(NV) */
 771         andi.   r13, r12, 0xfff
 772         addi    r13, r13, 1
 773         cmpw    0, r13, r11
 774         addi    r12, r12, 1
 775
 776         /* check if we need to wrap */
 777         blt     7f
 778
 779         /* wrap back to first free tlbcam entry */
 780         lis     r13, tlbcam_index@ha
 781         lwz     r13, tlbcam_index@l(r13)
 782         rlwimi  r12, r13, 0, 20, 31
 783 7:
 784         mtspr   SPRN_MAS0,r12
 785 #endif /* CONFIG_E200 */
 786
 787         tlbwe
 788
 789         /* Done...restore registers and get out of here.  */
 790         mfspr   r11, SPRN_SPRG7R
 791         mtcr    r11
 792         mfspr   r13, SPRN_SPRG5R
 793         mfspr   r12, SPRN_SPRG4R
 794         mfspr   r11, SPRN_SPRG1
 795         mfspr   r10, SPRN_SPRG0
 796         rfi                                     /* Force context change */
 797
 798 #ifdef CONFIG_SPE
 799 /* Note that the SPE support is closely modeled after the AltiVec
 800  * support.  Changes to one are likely to be applicable to the
 801  * other!  */
 802 load_up_spe:
 803 /*
 804  * Disable SPE for the task which had SPE previously,
 805  * and save its SPE registers in its thread_struct.
 806  * Enables SPE for use in the kernel on return.
 807  * On SMP we know the SPE units are free, since we give it up every
 808  * switch.  -- Kumar
 809  */
 810         mfmsr   r5
 811         oris    r5,r5,MSR_SPE@h
 812         mtmsr   r5                      /* enable use of SPE now */
 813         isync
 814 /*
 815  * For SMP, we don't do lazy SPE switching because it just gets too
 816  * horrendously complex, especially when a task switches from one CPU
 817  * to another.  Instead we call giveup_spe in switch_to.
 818  */
 819 #ifndef CONFIG_SMP
 820         lis     r3,last_task_used_spe@ha
 821         lwz     r4,last_task_used_spe@l(r3)
 822         cmpi    0,r4,0
 823         beq     1f
 824         addi    r4,r4,THREAD    /* want THREAD of last_task_used_spe */
 825         SAVE_32EVRS(0,r10,r4)
 826         evxor   evr10, evr10, evr10     /* clear out evr10 */
 827         evmwumiaa evr10, evr10, evr10   /* evr10 <- ACC = 0 * 0 + ACC */
 828         li      r5,THREAD_ACC
 829         evstddx evr10, r4, r5           /* save off accumulator */
 830         lwz     r5,PT_REGS(r4)
 831         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 832         lis     r10,MSR_SPE@h
 833         andc    r4,r4,r10       /* disable SPE for previous task */
 834         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 835 1:
 836 #endif /* !CONFIG_SMP */
 837         /* enable use of SPE after return */
 838         oris    r9,r9,MSR_SPE@h
 839         mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
 840         li      r4,1
 841         li      r10,THREAD_ACC
 842         stw     r4,THREAD_USED_SPE(r5)
 843         evlddx  evr4,r10,r5
 844         evmra   evr4,evr4
 845         REST_32EVRS(0,r10,r5)
 846 #ifndef CONFIG_SMP
 847         subi    r4,r5,THREAD
 848         stw     r4,last_task_used_spe@l(r3)
 849 #endif /* !CONFIG_SMP */
 850         /* restore registers and return */
 851 2:      REST_4GPRS(3, r11)
 852         lwz     r10,_CCR(r11)
 853         REST_GPR(1, r11)
 854         mtcr    r10
 855         lwz     r10,_LINK(r11)
 856         mtlr    r10
 857         REST_GPR(10, r11)
 858         mtspr   SPRN_SRR1,r9
 859         mtspr   SPRN_SRR0,r12
 860         REST_GPR(9, r11)
 861         REST_GPR(12, r11)
 862         lwz     r11,GPR11(r11)
 863         rfi
 864
 865 /*
 866  * SPE unavailable trap from kernel - print a message, but let
 867  * the task use SPE in the kernel until it returns to user mode.
 868  */
 869 KernelSPE:
 870         lwz     r3,_MSR(r1)
 871         oris    r3,r3,MSR_SPE@h
 872         stw     r3,_MSR(r1)     /* enable use of SPE after return */
 873         lis     r3,87f@h
 874         ori     r3,r3,87f@l
 875         mr      r4,r2           /* current */
 876         lwz     r5,_NIP(r1)
 877         bl      printk
 878         b       ret_from_except
 879 87:     .string "SPE used in kernel  (task=%p, pc=%x)  \n"
 880         .align  4,0
 881
 882 #endif /* CONFIG_SPE */
 883
 884 /*
 885  * Global functions
 886  */
 887
 888 /* Adjust or setup IVORs for e200 */
 889 _GLOBAL(__setup_e200_ivors)
 890         li      r3,DebugDebug@l
 891         mtspr   SPRN_IVOR15,r3
 892         li      r3,SPEUnavailable@l
 893         mtspr   SPRN_IVOR32,r3
 894         li      r3,SPEFloatingPointData@l
 895         mtspr   SPRN_IVOR33,r3
 896         li      r3,SPEFloatingPointRound@l
 897         mtspr   SPRN_IVOR34,r3
 898         sync
 899         blr
 900
 901 /* Adjust or setup IVORs for e500v1/v2 */
 902 _GLOBAL(__setup_e500_ivors)
 903         li      r3,DebugCrit@l
 904         mtspr   SPRN_IVOR15,r3
 905         li      r3,SPEUnavailable@l
 906         mtspr   SPRN_IVOR32,r3
 907         li      r3,SPEFloatingPointData@l
 908         mtspr   SPRN_IVOR33,r3
 909         li      r3,SPEFloatingPointRound@l
 910         mtspr   SPRN_IVOR34,r3
 911         li      r3,PerformanceMonitor@l
 912         mtspr   SPRN_IVOR35,r3
 913         sync
 914         blr
 915
 916 /* Adjust or setup IVORs for e500mc */
 917 _GLOBAL(__setup_e500mc_ivors)
 918         li      r3,DebugDebug@l
 919         mtspr   SPRN_IVOR15,r3
 920         li      r3,PerformanceMonitor@l
 921         mtspr   SPRN_IVOR35,r3
 922         li      r3,Doorbell@l
 923         mtspr   SPRN_IVOR36,r3
 924         sync
 925         blr
 926
 927 /*
 928  * extern void loadcam_entry(unsigned int index)
 929  *
 930  * Load TLBCAM[index] entry in to the L2 CAM MMU
 931  */
 932 _GLOBAL(loadcam_entry)
 933         lis     r4,TLBCAM@ha
 934         addi    r4,r4,TLBCAM@l
 935         mulli   r5,r3,TLBCAM_SIZE
 936         add     r3,r5,r4
 937         lwz     r4,0(r3)
 938         mtspr   SPRN_MAS0,r4
 939         lwz     r4,4(r3)
 940         mtspr   SPRN_MAS1,r4
 941         lwz     r4,8(r3)
 942         mtspr   SPRN_MAS2,r4
 943         lwz     r4,12(r3)
 944         mtspr   SPRN_MAS3,r4
 945         tlbwe
 946         isync
 947         blr
 948
 949 /*
 950  * extern void giveup_altivec(struct task_struct *prev)
 951  *
 952  * The e500 core does not have an AltiVec unit.
 953  */
 954 _GLOBAL(giveup_altivec)
 955         blr
 956
 957 #ifdef CONFIG_SPE
 958 /*
 959  * extern void giveup_spe(struct task_struct *prev)
 960  *
 961  */
 962 _GLOBAL(giveup_spe)
 963         mfmsr   r5
 964         oris    r5,r5,MSR_SPE@h
 965         mtmsr   r5                      /* enable use of SPE now */
 966         isync
 967         cmpi    0,r3,0
 968         beqlr-                          /* if no previous owner, done */
 969         addi    r3,r3,THREAD            /* want THREAD of task */
 970         lwz     r5,PT_REGS(r3)
 971         cmpi    0,r5,0
 972         SAVE_32EVRS(0, r4, r3)
 973         evxor   evr6, evr6, evr6        /* clear out evr6 */
 974         evmwumiaa evr6, evr6, evr6      /* evr6 <- ACC = 0 * 0 + ACC */
 975         li      r4,THREAD_ACC
 976         evstddx evr6, r4, r3            /* save off accumulator */
 977         mfspr   r6,SPRN_SPEFSCR
 978         stw     r6,THREAD_SPEFSCR(r3)   /* save spefscr register value */
 979         beq     1f
 980         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 981         lis     r3,MSR_SPE@h
 982         andc    r4,r4,r3                /* disable SPE for previous task */
 983         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 984 1:
 985 #ifndef CONFIG_SMP
 986         li      r5,0
 987         lis     r4,last_task_used_spe@ha
 988         stw     r5,last_task_used_spe@l(r4)
 989 #endif /* !CONFIG_SMP */
 990         blr
 991 #endif /* CONFIG_SPE */
 992
 993 /*
 994  * extern void giveup_fpu(struct task_struct *prev)
 995  *
 996  * Not all FSL Book-E cores have an FPU
 997  */
 998 #ifndef CONFIG_PPC_FPU
 999 _GLOBAL(giveup_fpu)
1000         blr
1001 #endif
1002
1003 /*
1004  * extern void abort(void)
1005  *
1006  * At present, this routine just applies a system reset.
1007  */
1008 _GLOBAL(abort)
1009         li      r13,0
1010         mtspr   SPRN_DBCR0,r13          /* disable all debug events */
1011         isync
1012         mfmsr   r13
1013         ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
1014         mtmsr   r13
1015         isync
1016         mfspr   r13,SPRN_DBCR0
1017         lis     r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1018         mtspr   SPRN_DBCR0,r13
1019         isync
1020
1021 _GLOBAL(set_context)
1022
1023 #ifdef CONFIG_BDI_SWITCH
1024         /* Context switch the PTE pointer for the Abatron BDI2000.
1025          * The PGDIR is the second parameter.
1026          */
1027         lis     r5, abatron_pteptrs@h
1028         ori     r5, r5, abatron_pteptrs@l
1029         stw     r4, 0x4(r5)
1030 #endif
1031         mtspr   SPRN_PID,r3
1032         isync                   /* Force context change */
1033         blr
1034
1035 _GLOBAL(flush_dcache_L1)
1036         mfspr   r3,SPRN_L1CFG0
1037
1038         rlwinm  r5,r3,9,3       /* Extract cache block size */
1039         twlgti  r5,1            /* Only 32 and 64 byte cache blocks
1040                                  * are currently defined.
1041                                  */
1042         li      r4,32
1043         subfic  r6,r5,2         /* r6 = log2(1KiB / cache block size) -
1044                                  *      log2(number of ways)
1045                                  */
1046         slw     r5,r4,r5        /* r5 = cache block size */
1047
1048         rlwinm  r7,r3,0,0xff    /* Extract number of KiB in the cache */
1049         mulli   r7,r7,13        /* An 8-way cache will require 13
1050                                  * loads per set.
1051                                  */
1052         slw     r7,r7,r6
1053
1054         /* save off HID0 and set DCFA */
1055         mfspr   r8,SPRN_HID0
1056         ori     r9,r8,HID0_DCFA@l
1057         mtspr   SPRN_HID0,r9
1058         isync
1059
1060         lis     r4,KERNELBASE@h
1061         mtctr   r7
1062
1063 1:      lwz     r3,0(r4)        /* Load... */
1064         add     r4,r4,r5
1065         bdnz    1b
1066
1067         msync
1068         lis     r4,KERNELBASE@h
1069         mtctr   r7
1070
1071 1:      dcbf    0,r4            /* ...and flush. */
1072         add     r4,r4,r5
1073         bdnz    1b
1074
1075         /* restore HID0 */
1076         mtspr   SPRN_HID0,r8
1077         isync
1078
1079         blr
1080
1081 #ifdef CONFIG_SMP
1082 /* When we get here, r24 needs to hold the CPU # */
1083         .globl __secondary_start
1084 __secondary_start:
1085         lis     r3,__secondary_hold_acknowledge@h
1086         ori     r3,r3,__secondary_hold_acknowledge@l
1087         stw     r24,0(r3)
1088
1089         li      r3,0
1090         mr      r4,r24          /* Why? */
1091         bl      call_setup_cpu
1092
1093         lis     r3,tlbcam_index@ha
1094         lwz     r3,tlbcam_index@l(r3)
1095         mtctr   r3
1096         li      r26,0           /* r26 safe? */
1097
1098         /* Load each CAM entry */
1099 1:      mr      r3,r26
1100         bl      loadcam_entry
1101         addi    r26,r26,1
1102         bdnz    1b
1103
1104         /* get current_thread_info and current */
1105         lis     r1,secondary_ti@ha
1106         lwz     r1,secondary_ti@l(r1)
1107         lwz     r2,TI_TASK(r1)
1108
1109         /* stack */
1110         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1111         li      r0,0
1112         stw     r0,0(r1)
1113
1114         /* ptr to current thread */
1115         addi    r4,r2,THREAD    /* address of our thread_struct */
1116         mtspr   SPRN_SPRG3,r4
1117
1118         /* Setup the defaults for TLB entries */
1119         li      r4,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
1120         mtspr   SPRN_MAS4,r4
1121
1122         /* Jump to start_secondary */
1123         lis     r4,MSR_KERNEL@h
1124         ori     r4,r4,MSR_KERNEL@l
1125         lis     r3,start_secondary@h
1126         ori     r3,r3,start_secondary@l
1127         mtspr   SPRN_SRR0,r3
1128         mtspr   SPRN_SRR1,r4
1129         sync
1130         rfi
1131         sync
1132
1133         .globl __secondary_hold_acknowledge
1134 __secondary_hold_acknowledge:
1135         .long   -1
1136 #endif
1137
1138 /*
1139  * We put a few things here that have to be page-aligned. This stuff
1140  * goes at the beginning of the data segment, which is page-aligned.
1141  */
1142         .data
1143         .align  12
1144         .globl  sdata
1145 sdata:
1146         .globl  empty_zero_page
1147 empty_zero_page:
1148         .space  4096
1149         .globl  swapper_pg_dir
1150 swapper_pg_dir:
1151         .space  PGD_TABLE_SIZE
1152
1153 /*
1154  * Room for two PTE pointers, usually the kernel and current user pointers
1155  * to their respective root page table.
1156  */
1157 abatron_pteptrs:
1158         .space  8