arch/powerpc/kernel/head_fsl_booke.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2004 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *    Copyright 2004 Freescale Semiconductor, Inc
  25  *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  */
  32
  33 #include <linux/threads.h>
  34 #include <asm/processor.h>
  35 #include <asm/page.h>
  36 #include <asm/mmu.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/cputable.h>
  39 #include <asm/thread_info.h>
  40 #include <asm/ppc_asm.h>
  41 #include <asm/asm-offsets.h>
  42 #include <asm/cache.h>
  43 #include "head_booke.h"
  44
  45 /* As with the other PowerPC ports, it is expected that when code
  46  * execution begins here, the following registers contain valid, yet
  47  * optional, information:
  48  *
  49  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  50  *   r4 - Starting address of the init RAM disk
  51  *   r5 - Ending address of the init RAM disk
  52  *   r6 - Start of kernel command line string (e.g. "mem=128")
  53  *   r7 - End of kernel command line string
  54  *
  55  */
  56         .section        .text.head, "ax"
  57 _ENTRY(_stext);
  58 _ENTRY(_start);
  59         /*
  60          * Reserve a word at a fixed location to store the address
  61          * of abatron_pteptrs
  62          */
  63         nop
  64 /*
  65  * Save parameters we are passed
  66  */
  67         mr      r31,r3
  68         mr      r30,r4
  69         mr      r29,r5
  70         mr      r28,r6
  71         mr      r27,r7
  72         li      r25,0           /* phys kernel start (low) */
  73         li      r24,0           /* CPU number */
  74         li      r23,0           /* phys kernel start (high) */
  75
  76 /* We try to not make any assumptions about how the boot loader
  77  * setup or used the TLBs.  We invalidate all mappings from the
  78  * boot loader and load a single entry in TLB1[0] to map the
  79  * first 64M of kernel memory.  Any boot info passed from the
  80  * bootloader needs to live in this first 64M.
  81  *
  82  * Requirement on bootloader:
  83  *  - The page we're executing in needs to reside in TLB1 and
  84  *    have IPROT=1.  If not an invalidate broadcast could
  85  *    evict the entry we're currently executing in.
  86  *
  87  *  r3 = Index of TLB1 were executing in
  88  *  r4 = Current MSR[IS]
  89  *  r5 = Index of TLB1 temp mapping
  90  *
  91  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
  92  * if needed
  93  */
  94
  95 /* 1. Find the index of the entry we're executing in */
  96         bl      invstr                          /* Find our address */
  97 invstr: mflr    r6                              /* Make it accessible */
  98         mfmsr   r7
  99         rlwinm  r4,r7,27,31,31                  /* extract MSR[IS] */
 100         mfspr   r7, SPRN_PID0
 101         slwi    r7,r7,16
 102         or      r7,r7,r4
 103         mtspr   SPRN_MAS6,r7
 104         tlbsx   0,r6                            /* search MSR[IS], SPID=PID0 */
 105 #ifndef CONFIG_E200
 106         mfspr   r7,SPRN_MAS1
 107         andis.  r7,r7,MAS1_VALID@h
 108         bne     match_TLB
 109         mfspr   r7,SPRN_PID1
 110         slwi    r7,r7,16
 111         or      r7,r7,r4
 112         mtspr   SPRN_MAS6,r7
 113         tlbsx   0,r6                            /* search MSR[IS], SPID=PID1 */
 114         mfspr   r7,SPRN_MAS1
 115         andis.  r7,r7,MAS1_VALID@h
 116         bne     match_TLB
 117         mfspr   r7, SPRN_PID2
 118         slwi    r7,r7,16
 119         or      r7,r7,r4
 120         mtspr   SPRN_MAS6,r7
 121         tlbsx   0,r6                            /* Fall through, we had to match */
 122 #endif
 123 match_TLB:
 124         mfspr   r7,SPRN_MAS0
 125         rlwinm  r3,r7,16,20,31                  /* Extract MAS0(Entry) */
 126
 127         mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
 128         oris    r7,r7,MAS1_IPROT@h
 129         mtspr   SPRN_MAS1,r7
 130         tlbwe
 131
 132 /* 2. Invalidate all entries except the entry we're executing in */
 133         mfspr   r9,SPRN_TLB1CFG
 134         andi.   r9,r9,0xfff
 135         li      r6,0                            /* Set Entry counter to 0 */
 136 1:      lis     r7,0x1000                       /* Set MAS0(TLBSEL) = 1 */
 137         rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
 138         mtspr   SPRN_MAS0,r7
 139         tlbre
 140         mfspr   r7,SPRN_MAS1
 141         rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
 142         cmpw    r3,r6
 143         beq     skpinv                          /* Dont update the current execution TLB */
 144         mtspr   SPRN_MAS1,r7
 145         tlbwe
 146         isync
 147 skpinv: addi    r6,r6,1                         /* Increment */
 148         cmpw    r6,r9                           /* Are we done? */
 149         bne     1b                              /* If not, repeat */
 150
 151         /* Invalidate TLB0 */
 152         li      r6,0x04
 153         tlbivax 0,r6
 154         TLBSYNC
 155         /* Invalidate TLB1 */
 156         li      r6,0x0c
 157         tlbivax 0,r6
 158         TLBSYNC
 159
 160 /* 3. Setup a temp mapping and jump to it */
 161         andi.   r5, r3, 0x1     /* Find an entry not used and is non-zero */
 162         addi    r5, r5, 0x1
 163         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 164         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 165         mtspr   SPRN_MAS0,r7
 166         tlbre
 167
 168         /* grab and fixup the RPN */
 169         mfspr   r6,SPRN_MAS1    /* extract MAS1[SIZE] */
 170         rlwinm  r6,r6,25,27,30
 171         li      r8,-1
 172         addi    r6,r6,10
 173         slw     r6,r8,r6        /* convert to mask */
 174
 175         bl      1f              /* Find our address */
 176 1:      mflr    r7
 177
 178         mfspr   r8,SPRN_MAS3
 179 #ifdef CONFIG_PHYS_64BIT
 180         mfspr   r23,SPRN_MAS7
 181 #endif
 182         and     r8,r6,r8
 183         subfic  r9,r6,-4096
 184         and     r9,r9,r7
 185
 186         or      r25,r8,r9
 187         ori     r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
 188
 189         /* Just modify the entry ID and EPN for the temp mapping */
 190         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 191         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 192         mtspr   SPRN_MAS0,r7
 193         xori    r6,r4,1         /* Setup TMP mapping in the other Address space */
 194         slwi    r6,r6,12
 195         oris    r6,r6,(MAS1_VALID|MAS1_IPROT)@h
 196         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 197         mtspr   SPRN_MAS1,r6
 198         mfspr   r6,SPRN_MAS2
 199         li      r7,0            /* temp EPN = 0 */
 200         rlwimi  r7,r6,0,20,31
 201         mtspr   SPRN_MAS2,r7
 202         mtspr   SPRN_MAS3,r8
 203         tlbwe
 204
 205         xori    r6,r4,1
 206         slwi    r6,r6,5         /* setup new context with other address space */
 207         bl      1f              /* Find our address */
 208 1:      mflr    r9
 209         rlwimi  r7,r9,0,20,31
 210         addi    r7,r7,24
 211         mtspr   SPRN_SRR0,r7
 212         mtspr   SPRN_SRR1,r6
 213         rfi
 214
 215 /* 4. Clear out PIDs & Search info */
 216         li      r6,0
 217         mtspr   SPRN_PID0,r6
 218 #ifndef CONFIG_E200
 219         mtspr   SPRN_PID1,r6
 220         mtspr   SPRN_PID2,r6
 221 #endif
 222         mtspr   SPRN_MAS6,r6
 223
 224 /* 5. Invalidate mapping we started in */
 225         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 226         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 227         mtspr   SPRN_MAS0,r7
 228         tlbre
 229         mfspr   r6,SPRN_MAS1
 230         rlwinm  r6,r6,0,2,0     /* clear IPROT */
 231         mtspr   SPRN_MAS1,r6
 232         tlbwe
 233         /* Invalidate TLB1 */
 234         li      r9,0x0c
 235         tlbivax 0,r9
 236         TLBSYNC
 237
 238 /* The mapping only needs to be cache-coherent on SMP */
 239 #ifdef CONFIG_SMP
 240 #define M_IF_SMP        MAS2_M
 241 #else
 242 #define M_IF_SMP        0
 243 #endif
 244
 245 /* 6. Setup KERNELBASE mapping in TLB1[0] */
 246         lis     r6,0x1000               /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
 247         mtspr   SPRN_MAS0,r6
 248         lis     r6,(MAS1_VALID|MAS1_IPROT)@h
 249         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
 250         mtspr   SPRN_MAS1,r6
 251         lis     r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@h
 252         ori     r6,r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@l
 253         mtspr   SPRN_MAS2,r6
 254         mtspr   SPRN_MAS3,r8
 255         tlbwe
 256
 257 /* 7. Jump to KERNELBASE mapping */
 258         lis     r6,(KERNELBASE & ~0xfff)@h
 259         ori     r6,r6,(KERNELBASE & ~0xfff)@l
 260         lis     r7,MSR_KERNEL@h
 261         ori     r7,r7,MSR_KERNEL@l
 262         bl      1f                      /* Find our address */
 263 1:      mflr    r9
 264         rlwimi  r6,r9,0,20,31
 265         addi    r6,r6,(2f - 1b)
 266         mtspr   SPRN_SRR0,r6
 267         mtspr   SPRN_SRR1,r7
 268         rfi                             /* start execution out of TLB1[0] entry */
 269
 270 /* 8. Clear out the temp mapping */
 271 2:      lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 272         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 273         mtspr   SPRN_MAS0,r7
 274         tlbre
 275         mfspr   r8,SPRN_MAS1
 276         rlwinm  r8,r8,0,2,0     /* clear IPROT */
 277         mtspr   SPRN_MAS1,r8
 278         tlbwe
 279         /* Invalidate TLB1 */
 280         li      r9,0x0c
 281         tlbivax 0,r9
 282         TLBSYNC
 283
 284         /* Establish the interrupt vector offsets */
 285         SET_IVOR(0,  CriticalInput);
 286         SET_IVOR(1,  MachineCheck);
 287         SET_IVOR(2,  DataStorage);
 288         SET_IVOR(3,  InstructionStorage);
 289         SET_IVOR(4,  ExternalInput);
 290         SET_IVOR(5,  Alignment);
 291         SET_IVOR(6,  Program);
 292         SET_IVOR(7,  FloatingPointUnavailable);
 293         SET_IVOR(8,  SystemCall);
 294         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 295         SET_IVOR(10, Decrementer);
 296         SET_IVOR(11, FixedIntervalTimer);
 297         SET_IVOR(12, WatchdogTimer);
 298         SET_IVOR(13, DataTLBError);
 299         SET_IVOR(14, InstructionTLBError);
 300         SET_IVOR(15, DebugDebug);
 301 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
 302         SET_IVOR(15, DebugCrit);
 303 #endif
 304         SET_IVOR(32, SPEUnavailable);
 305         SET_IVOR(33, SPEFloatingPointData);
 306         SET_IVOR(34, SPEFloatingPointRound);
 307 #ifndef CONFIG_E200
 308         SET_IVOR(35, PerformanceMonitor);
 309 #endif
 310 #ifdef CONFIG_PPC_E500MC
 311         SET_IVOR(36, Doorbell);
 312 #endif
 313
 314         /* Establish the interrupt vector base */
 315         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 316         mtspr   SPRN_IVPR,r4
 317
 318         /* Setup the defaults for TLB entries */
 319         li      r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
 320 #ifdef CONFIG_E200
 321         oris    r2,r2,MAS4_TLBSELD(1)@h
 322 #endif
 323         mtspr   SPRN_MAS4, r2
 324
 325 #if 0
 326         /* Enable DOZE */
 327         mfspr   r2,SPRN_HID0
 328         oris    r2,r2,HID0_DOZE@h
 329         mtspr   SPRN_HID0, r2
 330 #endif
 331 #ifdef CONFIG_E200
 332         /* enable dedicated debug exception handling resources (Debug APU) */
 333         mfspr   r2,SPRN_HID0
 334         ori     r2,r2,HID0_DAPUEN@l
 335         mtspr   SPRN_HID0,r2
 336 #endif
 337
 338 #if !defined(CONFIG_BDI_SWITCH)
 339         /*
 340          * The Abatron BDI JTAG debugger does not tolerate others
 341          * mucking with the debug registers.
 342          */
 343         lis     r2,DBCR0_IDM@h
 344         mtspr   SPRN_DBCR0,r2
 345         isync
 346         /* clear any residual debug events */
 347         li      r2,-1
 348         mtspr   SPRN_DBSR,r2
 349 #endif
 350
 351         /*
 352          * This is where the main kernel code starts.
 353          */
 354
 355         /* ptr to current */
 356         lis     r2,init_task@h
 357         ori     r2,r2,init_task@l
 358
 359         /* ptr to current thread */
 360         addi    r4,r2,THREAD    /* init task's THREAD */
 361         mtspr   SPRN_SPRG3,r4
 362
 363         /* stack */
 364         lis     r1,init_thread_union@h
 365         ori     r1,r1,init_thread_union@l
 366         li      r0,0
 367         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 368
 369         bl      early_init
 370
 371 #ifdef CONFIG_RELOCATABLE
 372         lis     r3,kernstart_addr@ha
 373         la      r3,kernstart_addr@l(r3)
 374 #ifdef CONFIG_PHYS_64BIT
 375         stw     r23,0(r3)
 376         stw     r25,4(r3)
 377 #else
 378         stw     r25,0(r3)
 379 #endif
 380 #endif
 381
 382         mfspr   r3,SPRN_TLB1CFG
 383         andi.   r3,r3,0xfff
 384         lis     r4,num_tlbcam_entries@ha
 385         stw     r3,num_tlbcam_entries@l(r4)
 386 /*
 387  * Decide what sort of machine this is and initialize the MMU.
 388  */
 389         mr      r3,r31
 390         mr      r4,r30
 391         mr      r5,r29
 392         mr      r6,r28
 393         mr      r7,r27
 394         bl      machine_init
 395         bl      MMU_init
 396
 397         /* Setup PTE pointers for the Abatron bdiGDB */
 398         lis     r6, swapper_pg_dir@h
 399         ori     r6, r6, swapper_pg_dir@l
 400         lis     r5, abatron_pteptrs@h
 401         ori     r5, r5, abatron_pteptrs@l
 402         lis     r4, KERNELBASE@h
 403         ori     r4, r4, KERNELBASE@l
 404         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 405         stw     r6, 0(r5)
 406
 407         /* Let's move on */
 408         lis     r4,start_kernel@h
 409         ori     r4,r4,start_kernel@l
 410         lis     r3,MSR_KERNEL@h
 411         ori     r3,r3,MSR_KERNEL@l
 412         mtspr   SPRN_SRR0,r4
 413         mtspr   SPRN_SRR1,r3
 414         rfi                     /* change context and jump to start_kernel */
 415
 416 /* Macros to hide the PTE size differences
 417  *
 418  * FIND_PTE -- walks the page tables given EA & pgdir pointer
 419  *   r10 -- EA of fault
 420  *   r11 -- PGDIR pointer
 421  *   r12 -- free
 422  *   label 2: is the bailout case
 423  *
 424  * if we find the pte (fall through):
 425  *   r11 is low pte word
 426  *   r12 is pointer to the pte
 427  */
 428 #ifdef CONFIG_PTE_64BIT
 429 #define FIND_PTE        \
 430         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 431         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 432         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 433         beq     2f;                     /* Bail if no table */          \
 434         rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 435         lwz     r11, 4(r12);            /* Get pte entry */
 436 #else
 437 #define FIND_PTE        \
 438         rlwimi  r11, r10, 12, 20, 29;   /* Create L1 (pgdir/pmd) address */     \
 439         lwz     r11, 0(r11);            /* Get L1 entry */                      \
 440         rlwinm. r12, r11, 0, 0, 19;     /* Extract L2 (pte) base address */     \
 441         beq     2f;                     /* Bail if no table */                  \
 442         rlwimi  r12, r10, 22, 20, 29;   /* Compute PTE address */               \
 443         lwz     r11, 0(r12);            /* Get Linux PTE */
 444 #endif
 445
 446 /*
 447  * Interrupt vector entry code
 448  *
 449  * The Book E MMUs are always on so we don't need to handle
 450  * interrupts in real mode as with previous PPC processors. In
 451  * this case we handle interrupts in the kernel virtual address
 452  * space.
 453  *
 454  * Interrupt vectors are dynamically placed relative to the
 455  * interrupt prefix as determined by the address of interrupt_base.
 456  * The interrupt vectors offsets are programmed using the labels
 457  * for each interrupt vector entry.
 458  *
 459  * Interrupt vectors must be aligned on a 16 byte boundary.
 460  * We align on a 32 byte cache line boundary for good measure.
 461  */
 462
 463 interrupt_base:
 464         /* Critical Input Interrupt */
 465         CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
 466
 467         /* Machine Check Interrupt */
 468 #ifdef CONFIG_E200
 469         /* no RFMCI, MCSRRs on E200 */
 470         CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 471 #else
 472         MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 473 #endif
 474
 475         /* Data Storage Interrupt */
 476         START_EXCEPTION(DataStorage)
 477         NORMAL_EXCEPTION_PROLOG
 478         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 479         stw     r5,_ESR(r11)
 480         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 481         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
 482         bne     1f
 483         EXC_XFER_EE_LITE(0x0300, handle_page_fault)
 484 1:
 485         addi    r3,r1,STACK_FRAME_OVERHEAD
 486         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
 487
 488         /* Instruction Storage Interrupt */
 489         INSTRUCTION_STORAGE_EXCEPTION
 490
 491         /* External Input Interrupt */
 492         EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
 493
 494         /* Alignment Interrupt */
 495         ALIGNMENT_EXCEPTION
 496
 497         /* Program Interrupt */
 498         PROGRAM_EXCEPTION
 499
 500         /* Floating Point Unavailable Interrupt */
 501 #ifdef CONFIG_PPC_FPU
 502         FP_UNAVAILABLE_EXCEPTION
 503 #else
 504 #ifdef CONFIG_E200
 505         /* E200 treats 'normal' floating point instructions as FP Unavail exception */
 506         EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
 507 #else
 508         EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
 509 #endif
 510 #endif
 511
 512         /* System Call Interrupt */
 513         START_EXCEPTION(SystemCall)
 514         NORMAL_EXCEPTION_PROLOG
 515         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 516
 517         /* Auxillary Processor Unavailable Interrupt */
 518         EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
 519
 520         /* Decrementer Interrupt */
 521         DECREMENTER_EXCEPTION
 522
 523         /* Fixed Internal Timer Interrupt */
 524         /* TODO: Add FIT support */
 525         EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
 526
 527         /* Watchdog Timer Interrupt */
 528 #ifdef CONFIG_BOOKE_WDT
 529         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
 530 #else
 531         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
 532 #endif
 533
 534         /* Data TLB Error Interrupt */
 535         START_EXCEPTION(DataTLBError)
 536         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 537         mtspr   SPRN_SPRG1, r11
 538         mtspr   SPRN_SPRG4W, r12
 539         mtspr   SPRN_SPRG5W, r13
 540         mfcr    r11
 541         mtspr   SPRN_SPRG7W, r11
 542         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 543
 544         /* If we are faulting a kernel address, we have to use the
 545          * kernel page tables.
 546          */
 547         lis     r11, PAGE_OFFSET@h
 548         cmplw   5, r10, r11
 549         blt     5, 3f
 550         lis     r11, swapper_pg_dir@h
 551         ori     r11, r11, swapper_pg_dir@l
 552
 553         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 554         rlwinm  r12,r12,0,16,1
 555         mtspr   SPRN_MAS1,r12
 556
 557         b       4f
 558
 559         /* Get the PGD for the current thread */
 560 3:
 561         mfspr   r11,SPRN_SPRG3
 562         lwz     r11,PGDIR(r11)
 563
 564 4:
 565         /* Mask of required permission bits. Note that while we
 566          * do copy ESR:ST to _PAGE_RW position as trying to write
 567          * to an RO page is pretty common, we don't do it with
 568          * _PAGE_DIRTY. We could do it, but it's a fairly rare
 569          * event so I'd rather take the overhead when it happens
 570          * rather than adding an instruction here. We should measure
 571          * whether the whole thing is worth it in the first place
 572          * as we could avoid loading SPRN_ESR completely in the first
 573          * place...
 574          *
 575          * TODO: Is it worth doing that mfspr & rlwimi in the first
 576          *       place or can we save a couple of instructions here ?
 577          */
 578         mfspr   r12,SPRN_ESR
 579         li      r13,_PAGE_PRESENT|_PAGE_ACCESSED
 580         rlwimi  r13,r12,11,29,29
 581
 582         FIND_PTE
 583         andc.   r13,r13,r11             /* Check permission */
 584
 585 #ifdef CONFIG_PTE_64BIT
 586 #ifdef CONFIG_SMP
 587         subf    r10,r11,r12             /* create false data dep */
 588         lwzx    r13,r11,r10             /* Get upper pte bits */
 589 #else
 590         lwz     r13,0(r12)              /* Get upper pte bits */
 591 #endif
 592 #endif
 593
 594         bne     2f                      /* Bail if permission/valid mismach */
 595
 596         /* Jump to common tlb load */
 597         b       finish_tlb_load
 598 2:
 599         /* The bailout.  Restore registers to pre-exception conditions
 600          * and call the heavyweights to help us out.
 601          */
 602         mfspr   r11, SPRN_SPRG7R
 603         mtcr    r11
 604         mfspr   r13, SPRN_SPRG5R
 605         mfspr   r12, SPRN_SPRG4R
 606         mfspr   r11, SPRN_SPRG1
 607         mfspr   r10, SPRN_SPRG0
 608         b       DataStorage
 609
 610         /* Instruction TLB Error Interrupt */
 611         /*
 612          * Nearly the same as above, except we get our
 613          * information from different registers and bailout
 614          * to a different point.
 615          */
 616         START_EXCEPTION(InstructionTLBError)
 617         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 618         mtspr   SPRN_SPRG1, r11
 619         mtspr   SPRN_SPRG4W, r12
 620         mtspr   SPRN_SPRG5W, r13
 621         mfcr    r11
 622         mtspr   SPRN_SPRG7W, r11
 623         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 624
 625         /* If we are faulting a kernel address, we have to use the
 626          * kernel page tables.
 627          */
 628         lis     r11, PAGE_OFFSET@h
 629         cmplw   5, r10, r11
 630         blt     5, 3f
 631         lis     r11, swapper_pg_dir@h
 632         ori     r11, r11, swapper_pg_dir@l
 633
 634         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 635         rlwinm  r12,r12,0,16,1
 636         mtspr   SPRN_MAS1,r12
 637
 638         b       4f
 639
 640         /* Get the PGD for the current thread */
 641 3:
 642         mfspr   r11,SPRN_SPRG3
 643         lwz     r11,PGDIR(r11)
 644
 645 4:
 646         /* Make up the required permissions */
 647         li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
 648
 649         FIND_PTE
 650         andc.   r13,r13,r11             /* Check permission */
 651
 652 #ifdef CONFIG_PTE_64BIT
 653 #ifdef CONFIG_SMP
 654         subf    r10,r11,r12             /* create false data dep */
 655         lwzx    r13,r11,r10             /* Get upper pte bits */
 656 #else
 657         lwz     r13,0(r12)              /* Get upper pte bits */
 658 #endif
 659 #endif
 660
 661         bne     2f                      /* Bail if permission mismach */
 662
 663         /* Jump to common TLB load point */
 664         b       finish_tlb_load
 665
 666 2:
 667         /* The bailout.  Restore registers to pre-exception conditions
 668          * and call the heavyweights to help us out.
 669          */
 670         mfspr   r11, SPRN_SPRG7R
 671         mtcr    r11
 672         mfspr   r13, SPRN_SPRG5R
 673         mfspr   r12, SPRN_SPRG4R
 674         mfspr   r11, SPRN_SPRG1
 675         mfspr   r10, SPRN_SPRG0
 676         b       InstructionStorage
 677
 678 #ifdef CONFIG_SPE
 679         /* SPE Unavailable */
 680         START_EXCEPTION(SPEUnavailable)
 681         NORMAL_EXCEPTION_PROLOG
 682         bne     load_up_spe
 683         addi    r3,r1,STACK_FRAME_OVERHEAD
 684         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 685 #else
 686         EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
 687 #endif /* CONFIG_SPE */
 688
 689         /* SPE Floating Point Data */
 690 #ifdef CONFIG_SPE
 691         EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
 692
 693         /* SPE Floating Point Round */
 694         EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
 695 #else
 696         EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
 697         EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
 698 #endif /* CONFIG_SPE */
 699
 700         /* Performance Monitor */
 701         EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
 702
 703 #ifdef CONFIG_PPC_E500MC
 704         EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE)
 705 #endif
 706
 707         /* Debug Interrupt */
 708         DEBUG_DEBUG_EXCEPTION
 709 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
 710         DEBUG_CRIT_EXCEPTION
 711 #endif
 712
 713 /*
 714  * Local functions
 715  */
 716
 717 /*
 718  * Both the instruction and data TLB miss get to this
 719  * point to load the TLB.
 720  *      r10 - available to use
 721  *      r11 - TLB (info from Linux PTE)
 722  *      r12 - available to use
 723  *      r13 - upper bits of PTE (if PTE_64BIT) or available to use
 724  *      CR5 - results of addr >= PAGE_OFFSET
 725  *      MAS0, MAS1 - loaded with proper value when we get here
 726  *      MAS2, MAS3 - will need additional info from Linux PTE
 727  *      Upon exit, we reload everything and RFI.
 728  */
 729 finish_tlb_load:
 730         /*
 731          * We set execute, because we don't have the granularity to
 732          * properly set this at the page level (Linux problem).
 733          * Many of these bits are software only.  Bits we don't set
 734          * here we (properly should) assume have the appropriate value.
 735          */
 736
 737         mfspr   r12, SPRN_MAS2
 738 #ifdef CONFIG_PTE_64BIT
 739         rlwimi  r12, r11, 26, 24, 31    /* extract ...WIMGE from pte */
 740 #else
 741         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 742 #endif
 743         mtspr   SPRN_MAS2, r12
 744
 745         li      r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
 746         rlwimi  r10, r11, 31, 29, 29    /* extract _PAGE_DIRTY into SW */
 747         and     r12, r11, r10
 748         andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
 749         slwi    r10, r12, 1
 750         or      r10, r10, r12
 751         iseleq  r12, r12, r10
 752
 753 #ifdef CONFIG_PTE_64BIT
 754 2:      rlwimi  r12, r13, 24, 0, 7      /* grab RPN[32:39] */
 755         rlwimi  r12, r11, 24, 8, 19     /* grab RPN[40:51] */
 756         mtspr   SPRN_MAS3, r12
 757 BEGIN_FTR_SECTION
 758         srwi    r10, r13, 8             /* grab RPN[8:31] */
 759         mtspr   SPRN_MAS7, r10
 760 END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
 761 #else
 762 2:      rlwimi  r11, r12, 0, 20, 31     /* Extract RPN from PTE and merge with perms */
 763         mtspr   SPRN_MAS3, r11
 764 #endif
 765 #ifdef CONFIG_E200
 766         /* Round robin TLB1 entries assignment */
 767         mfspr   r12, SPRN_MAS0
 768
 769         /* Extract TLB1CFG(NENTRY) */
 770         mfspr   r11, SPRN_TLB1CFG
 771         andi.   r11, r11, 0xfff
 772
 773         /* Extract MAS0(NV) */
 774         andi.   r13, r12, 0xfff
 775         addi    r13, r13, 1
 776         cmpw    0, r13, r11
 777         addi    r12, r12, 1
 778
 779         /* check if we need to wrap */
 780         blt     7f
 781
 782         /* wrap back to first free tlbcam entry */
 783         lis     r13, tlbcam_index@ha
 784         lwz     r13, tlbcam_index@l(r13)
 785         rlwimi  r12, r13, 0, 20, 31
 786 7:
 787         mtspr   SPRN_MAS0,r12
 788 #endif /* CONFIG_E200 */
 789
 790         tlbwe
 791
 792         /* Done...restore registers and get out of here.  */
 793         mfspr   r11, SPRN_SPRG7R
 794         mtcr    r11
 795         mfspr   r13, SPRN_SPRG5R
 796         mfspr   r12, SPRN_SPRG4R
 797         mfspr   r11, SPRN_SPRG1
 798         mfspr   r10, SPRN_SPRG0
 799         rfi                                     /* Force context change */
 800
 801 #ifdef CONFIG_SPE
 802 /* Note that the SPE support is closely modeled after the AltiVec
 803  * support.  Changes to one are likely to be applicable to the
 804  * other!  */
 805 load_up_spe:
 806 /*
 807  * Disable SPE for the task which had SPE previously,
 808  * and save its SPE registers in its thread_struct.
 809  * Enables SPE for use in the kernel on return.
 810  * On SMP we know the SPE units are free, since we give it up every
 811  * switch.  -- Kumar
 812  */
 813         mfmsr   r5
 814         oris    r5,r5,MSR_SPE@h
 815         mtmsr   r5                      /* enable use of SPE now */
 816         isync
 817 /*
 818  * For SMP, we don't do lazy SPE switching because it just gets too
 819  * horrendously complex, especially when a task switches from one CPU
 820  * to another.  Instead we call giveup_spe in switch_to.
 821  */
 822 #ifndef CONFIG_SMP
 823         lis     r3,last_task_used_spe@ha
 824         lwz     r4,last_task_used_spe@l(r3)
 825         cmpi    0,r4,0
 826         beq     1f
 827         addi    r4,r4,THREAD    /* want THREAD of last_task_used_spe */
 828         SAVE_32EVRS(0,r10,r4)
 829         evxor   evr10, evr10, evr10     /* clear out evr10 */
 830         evmwumiaa evr10, evr10, evr10   /* evr10 <- ACC = 0 * 0 + ACC */
 831         li      r5,THREAD_ACC
 832         evstddx evr10, r4, r5           /* save off accumulator */
 833         lwz     r5,PT_REGS(r4)
 834         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 835         lis     r10,MSR_SPE@h
 836         andc    r4,r4,r10       /* disable SPE for previous task */
 837         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 838 1:
 839 #endif /* !CONFIG_SMP */
 840         /* enable use of SPE after return */
 841         oris    r9,r9,MSR_SPE@h
 842         mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
 843         li      r4,1
 844         li      r10,THREAD_ACC
 845         stw     r4,THREAD_USED_SPE(r5)
 846         evlddx  evr4,r10,r5
 847         evmra   evr4,evr4
 848         REST_32EVRS(0,r10,r5)
 849 #ifndef CONFIG_SMP
 850         subi    r4,r5,THREAD
 851         stw     r4,last_task_used_spe@l(r3)
 852 #endif /* !CONFIG_SMP */
 853         /* restore registers and return */
 854 2:      REST_4GPRS(3, r11)
 855         lwz     r10,_CCR(r11)
 856         REST_GPR(1, r11)
 857         mtcr    r10
 858         lwz     r10,_LINK(r11)
 859         mtlr    r10
 860         REST_GPR(10, r11)
 861         mtspr   SPRN_SRR1,r9
 862         mtspr   SPRN_SRR0,r12
 863         REST_GPR(9, r11)
 864         REST_GPR(12, r11)
 865         lwz     r11,GPR11(r11)
 866         rfi
 867
 868 /*
 869  * SPE unavailable trap from kernel - print a message, but let
 870  * the task use SPE in the kernel until it returns to user mode.
 871  */
 872 KernelSPE:
 873         lwz     r3,_MSR(r1)
 874         oris    r3,r3,MSR_SPE@h
 875         stw     r3,_MSR(r1)     /* enable use of SPE after return */
 876         lis     r3,87f@h
 877         ori     r3,r3,87f@l
 878         mr      r4,r2           /* current */
 879         lwz     r5,_NIP(r1)
 880         bl      printk
 881         b       ret_from_except
 882 87:     .string "SPE used in kernel  (task=%p, pc=%x)  \n"
 883         .align  4,0
 884
 885 #endif /* CONFIG_SPE */
 886
 887 /*
 888  * Global functions
 889  */
 890
 891 /*
 892  * extern void loadcam_entry(unsigned int index)
 893  *
 894  * Load TLBCAM[index] entry in to the L2 CAM MMU
 895  */
 896 _GLOBAL(loadcam_entry)
 897         lis     r4,TLBCAM@ha
 898         addi    r4,r4,TLBCAM@l
 899         mulli   r5,r3,20
 900         add     r3,r5,r4
 901         lwz     r4,0(r3)
 902         mtspr   SPRN_MAS0,r4
 903         lwz     r4,4(r3)
 904         mtspr   SPRN_MAS1,r4
 905         lwz     r4,8(r3)
 906         mtspr   SPRN_MAS2,r4
 907         lwz     r4,12(r3)
 908         mtspr   SPRN_MAS3,r4
 909         tlbwe
 910         isync
 911         blr
 912
 913 /*
 914  * extern void giveup_altivec(struct task_struct *prev)
 915  *
 916  * The e500 core does not have an AltiVec unit.
 917  */
 918 _GLOBAL(giveup_altivec)
 919         blr
 920
 921 #ifdef CONFIG_SPE
 922 /*
 923  * extern void giveup_spe(struct task_struct *prev)
 924  *
 925  */
 926 _GLOBAL(giveup_spe)
 927         mfmsr   r5
 928         oris    r5,r5,MSR_SPE@h
 929         mtmsr   r5                      /* enable use of SPE now */
 930         isync
 931         cmpi    0,r3,0
 932         beqlr-                          /* if no previous owner, done */
 933         addi    r3,r3,THREAD            /* want THREAD of task */
 934         lwz     r5,PT_REGS(r3)
 935         cmpi    0,r5,0
 936         SAVE_32EVRS(0, r4, r3)
 937         evxor   evr6, evr6, evr6        /* clear out evr6 */
 938         evmwumiaa evr6, evr6, evr6      /* evr6 <- ACC = 0 * 0 + ACC */
 939         li      r4,THREAD_ACC
 940         evstddx evr6, r4, r3            /* save off accumulator */
 941         mfspr   r6,SPRN_SPEFSCR
 942         stw     r6,THREAD_SPEFSCR(r3)   /* save spefscr register value */
 943         beq     1f
 944         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 945         lis     r3,MSR_SPE@h
 946         andc    r4,r4,r3                /* disable SPE for previous task */
 947         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 948 1:
 949 #ifndef CONFIG_SMP
 950         li      r5,0
 951         lis     r4,last_task_used_spe@ha
 952         stw     r5,last_task_used_spe@l(r4)
 953 #endif /* !CONFIG_SMP */
 954         blr
 955 #endif /* CONFIG_SPE */
 956
 957 /*
 958  * extern void giveup_fpu(struct task_struct *prev)
 959  *
 960  * Not all FSL Book-E cores have an FPU
 961  */
 962 #ifndef CONFIG_PPC_FPU
 963 _GLOBAL(giveup_fpu)
 964         blr
 965 #endif
 966
 967 /*
 968  * extern void abort(void)
 969  *
 970  * At present, this routine just applies a system reset.
 971  */
 972 _GLOBAL(abort)
 973         li      r13,0
 974         mtspr   SPRN_DBCR0,r13          /* disable all debug events */
 975         isync
 976         mfmsr   r13
 977         ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
 978         mtmsr   r13
 979         isync
 980         mfspr   r13,SPRN_DBCR0
 981         lis     r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
 982         mtspr   SPRN_DBCR0,r13
 983         isync
 984
 985 _GLOBAL(set_context)
 986
 987 #ifdef CONFIG_BDI_SWITCH
 988         /* Context switch the PTE pointer for the Abatron BDI2000.
 989          * The PGDIR is the second parameter.
 990          */
 991         lis     r5, abatron_pteptrs@h
 992         ori     r5, r5, abatron_pteptrs@l
 993         stw     r4, 0x4(r5)
 994 #endif
 995         mtspr   SPRN_PID,r3
 996         isync                   /* Force context change */
 997         blr
 998
 999 _GLOBAL(flush_dcache_L1)
1000         mfspr   r3,SPRN_L1CFG0
1001
1002         rlwinm  r5,r3,9,3       /* Extract cache block size */
1003         twlgti  r5,1            /* Only 32 and 64 byte cache blocks
1004                                  * are currently defined.
1005                                  */
1006         li      r4,32
1007         subfic  r6,r5,2         /* r6 = log2(1KiB / cache block size) -
1008                                  *      log2(number of ways)
1009                                  */
1010         slw     r5,r4,r5        /* r5 = cache block size */
1011
1012         rlwinm  r7,r3,0,0xff    /* Extract number of KiB in the cache */
1013         mulli   r7,r7,13        /* An 8-way cache will require 13
1014                                  * loads per set.
1015                                  */
1016         slw     r7,r7,r6
1017
1018         /* save off HID0 and set DCFA */
1019         mfspr   r8,SPRN_HID0
1020         ori     r9,r8,HID0_DCFA@l
1021         mtspr   SPRN_HID0,r9
1022         isync
1023
1024         lis     r4,KERNELBASE@h
1025         mtctr   r7
1026
1027 1:      lwz     r3,0(r4)        /* Load... */
1028         add     r4,r4,r5
1029         bdnz    1b
1030
1031         msync
1032         lis     r4,KERNELBASE@h
1033         mtctr   r7
1034
1035 1:      dcbf    0,r4            /* ...and flush. */
1036         add     r4,r4,r5
1037         bdnz    1b
1038
1039         /* restore HID0 */
1040         mtspr   SPRN_HID0,r8
1041         isync
1042
1043         blr
1044
1045 /*
1046  * We put a few things here that have to be page-aligned. This stuff
1047  * goes at the beginning of the data segment, which is page-aligned.
1048  */
1049         .data
1050         .align  12
1051         .globl  sdata
1052 sdata:
1053         .globl  empty_zero_page
1054 empty_zero_page:
1055         .space  4096
1056         .globl  swapper_pg_dir
1057 swapper_pg_dir:
1058         .space  PGD_TABLE_SIZE
1059
1060 /*
1061  * Room for two PTE pointers, usually the kernel and current user pointers
1062  * to their respective root page table.
1063  */
1064 abatron_pteptrs:
1065         .space  8