arch/powerpc/kernel/head_fsl_booke.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2004 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *    Copyright 2004 Freescale Semiconductor, Inc
  25  *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  */
  32
  33 #include <linux/config.h>
  34 #include <linux/threads.h>
  35 #include <asm/processor.h>
  36 #include <asm/page.h>
  37 #include <asm/mmu.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/cputable.h>
  40 #include <asm/thread_info.h>
  41 #include <asm/ppc_asm.h>
  42 #include <asm/asm-offsets.h>
  43 #include "head_booke.h"
  44
  45 /* As with the other PowerPC ports, it is expected that when code
  46  * execution begins here, the following registers contain valid, yet
  47  * optional, information:
  48  *
  49  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  50  *   r4 - Starting address of the init RAM disk
  51  *   r5 - Ending address of the init RAM disk
  52  *   r6 - Start of kernel command line string (e.g. "mem=128")
  53  *   r7 - End of kernel command line string
  54  *
  55  */
  56         .text
  57 _GLOBAL(_stext)
  58 _GLOBAL(_start)
  59         /*
  60          * Reserve a word at a fixed location to store the address
  61          * of abatron_pteptrs
  62          */
  63         nop
  64 /*
  65  * Save parameters we are passed
  66  */
  67         mr      r31,r3
  68         mr      r30,r4
  69         mr      r29,r5
  70         mr      r28,r6
  71         mr      r27,r7
  72         li      r24,0           /* CPU number */
  73
  74 /* We try to not make any assumptions about how the boot loader
  75  * setup or used the TLBs.  We invalidate all mappings from the
  76  * boot loader and load a single entry in TLB1[0] to map the
  77  * first 16M of kernel memory.  Any boot info passed from the
  78  * bootloader needs to live in this first 16M.
  79  *
  80  * Requirement on bootloader:
  81  *  - The page we're executing in needs to reside in TLB1 and
  82  *    have IPROT=1.  If not an invalidate broadcast could
  83  *    evict the entry we're currently executing in.
  84  *
  85  *  r3 = Index of TLB1 were executing in
  86  *  r4 = Current MSR[IS]
  87  *  r5 = Index of TLB1 temp mapping
  88  *
  89  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
  90  * if needed
  91  */
  92
  93 /* 1. Find the index of the entry we're executing in */
  94         bl      invstr                          /* Find our address */
  95 invstr: mflr    r6                              /* Make it accessible */
  96         mfmsr   r7
  97         rlwinm  r4,r7,27,31,31                  /* extract MSR[IS] */
  98         mfspr   r7, SPRN_PID0
  99         slwi    r7,r7,16
 100         or      r7,r7,r4
 101         mtspr   SPRN_MAS6,r7
 102         tlbsx   0,r6                            /* search MSR[IS], SPID=PID0 */
 103 #ifndef CONFIG_E200
 104         mfspr   r7,SPRN_MAS1
 105         andis.  r7,r7,MAS1_VALID@h
 106         bne     match_TLB
 107         mfspr   r7,SPRN_PID1
 108         slwi    r7,r7,16
 109         or      r7,r7,r4
 110         mtspr   SPRN_MAS6,r7
 111         tlbsx   0,r6                            /* search MSR[IS], SPID=PID1 */
 112         mfspr   r7,SPRN_MAS1
 113         andis.  r7,r7,MAS1_VALID@h
 114         bne     match_TLB
 115         mfspr   r7, SPRN_PID2
 116         slwi    r7,r7,16
 117         or      r7,r7,r4
 118         mtspr   SPRN_MAS6,r7
 119         tlbsx   0,r6                            /* Fall through, we had to match */
 120 #endif
 121 match_TLB:
 122         mfspr   r7,SPRN_MAS0
 123         rlwinm  r3,r7,16,20,31                  /* Extract MAS0(Entry) */
 124
 125         mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
 126         oris    r7,r7,MAS1_IPROT@h
 127         mtspr   SPRN_MAS1,r7
 128         tlbwe
 129
 130 /* 2. Invalidate all entries except the entry we're executing in */
 131         mfspr   r9,SPRN_TLB1CFG
 132         andi.   r9,r9,0xfff
 133         li      r6,0                            /* Set Entry counter to 0 */
 134 1:      lis     r7,0x1000                       /* Set MAS0(TLBSEL) = 1 */
 135         rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
 136         mtspr   SPRN_MAS0,r7
 137         tlbre
 138         mfspr   r7,SPRN_MAS1
 139         rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
 140         cmpw    r3,r6
 141         beq     skpinv                          /* Dont update the current execution TLB */
 142         mtspr   SPRN_MAS1,r7
 143         tlbwe
 144         isync
 145 skpinv: addi    r6,r6,1                         /* Increment */
 146         cmpw    r6,r9                           /* Are we done? */
 147         bne     1b                              /* If not, repeat */
 148
 149         /* Invalidate TLB0 */
 150         li      r6,0x04
 151         tlbivax 0,r6
 152 #ifdef CONFIG_SMP
 153         tlbsync
 154 #endif
 155         /* Invalidate TLB1 */
 156         li      r6,0x0c
 157         tlbivax 0,r6
 158 #ifdef CONFIG_SMP
 159         tlbsync
 160 #endif
 161         msync
 162
 163 /* 3. Setup a temp mapping and jump to it */
 164         andi.   r5, r3, 0x1     /* Find an entry not used and is non-zero */
 165         addi    r5, r5, 0x1
 166         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 167         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 168         mtspr   SPRN_MAS0,r7
 169         tlbre
 170
 171         /* Just modify the entry ID and EPN for the temp mapping */
 172         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 173         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 174         mtspr   SPRN_MAS0,r7
 175         xori    r6,r4,1         /* Setup TMP mapping in the other Address space */
 176         slwi    r6,r6,12
 177         oris    r6,r6,(MAS1_VALID|MAS1_IPROT)@h
 178         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 179         mtspr   SPRN_MAS1,r6
 180         mfspr   r6,SPRN_MAS2
 181         li      r7,0            /* temp EPN = 0 */
 182         rlwimi  r7,r6,0,20,31
 183         mtspr   SPRN_MAS2,r7
 184         tlbwe
 185
 186         xori    r6,r4,1
 187         slwi    r6,r6,5         /* setup new context with other address space */
 188         bl      1f              /* Find our address */
 189 1:      mflr    r9
 190         rlwimi  r7,r9,0,20,31
 191         addi    r7,r7,24
 192         mtspr   SPRN_SRR0,r7
 193         mtspr   SPRN_SRR1,r6
 194         rfi
 195
 196 /* 4. Clear out PIDs & Search info */
 197         li      r6,0
 198         mtspr   SPRN_PID0,r6
 199 #ifndef CONFIG_E200
 200         mtspr   SPRN_PID1,r6
 201         mtspr   SPRN_PID2,r6
 202 #endif
 203         mtspr   SPRN_MAS6,r6
 204
 205 /* 5. Invalidate mapping we started in */
 206         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 207         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 208         mtspr   SPRN_MAS0,r7
 209         tlbre
 210         li      r6,0
 211         mtspr   SPRN_MAS1,r6
 212         tlbwe
 213         /* Invalidate TLB1 */
 214         li      r9,0x0c
 215         tlbivax 0,r9
 216 #ifdef CONFIG_SMP
 217         tlbsync
 218 #endif
 219         msync
 220
 221 /* 6. Setup KERNELBASE mapping in TLB1[0] */
 222         lis     r6,0x1000               /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
 223         mtspr   SPRN_MAS0,r6
 224         lis     r6,(MAS1_VALID|MAS1_IPROT)@h
 225         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l
 226         mtspr   SPRN_MAS1,r6
 227         li      r7,0
 228         lis     r6,KERNELBASE@h
 229         ori     r6,r6,KERNELBASE@l
 230         rlwimi  r6,r7,0,20,31
 231         mtspr   SPRN_MAS2,r6
 232         li      r7,(MAS3_SX|MAS3_SW|MAS3_SR)
 233         mtspr   SPRN_MAS3,r7
 234         tlbwe
 235
 236 /* 7. Jump to KERNELBASE mapping */
 237         lis     r7,MSR_KERNEL@h
 238         ori     r7,r7,MSR_KERNEL@l
 239         bl      1f                      /* Find our address */
 240 1:      mflr    r9
 241         rlwimi  r6,r9,0,20,31
 242         addi    r6,r6,24
 243         mtspr   SPRN_SRR0,r6
 244         mtspr   SPRN_SRR1,r7
 245         rfi                             /* start execution out of TLB1[0] entry */
 246
 247 /* 8. Clear out the temp mapping */
 248         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 249         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 250         mtspr   SPRN_MAS0,r7
 251         tlbre
 252         mtspr   SPRN_MAS1,r8
 253         tlbwe
 254         /* Invalidate TLB1 */
 255         li      r9,0x0c
 256         tlbivax 0,r9
 257 #ifdef CONFIG_SMP
 258         tlbsync
 259 #endif
 260         msync
 261
 262         /* Establish the interrupt vector offsets */
 263         SET_IVOR(0,  CriticalInput);
 264         SET_IVOR(1,  MachineCheck);
 265         SET_IVOR(2,  DataStorage);
 266         SET_IVOR(3,  InstructionStorage);
 267         SET_IVOR(4,  ExternalInput);
 268         SET_IVOR(5,  Alignment);
 269         SET_IVOR(6,  Program);
 270         SET_IVOR(7,  FloatingPointUnavailable);
 271         SET_IVOR(8,  SystemCall);
 272         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 273         SET_IVOR(10, Decrementer);
 274         SET_IVOR(11, FixedIntervalTimer);
 275         SET_IVOR(12, WatchdogTimer);
 276         SET_IVOR(13, DataTLBError);
 277         SET_IVOR(14, InstructionTLBError);
 278         SET_IVOR(15, Debug);
 279         SET_IVOR(32, SPEUnavailable);
 280         SET_IVOR(33, SPEFloatingPointData);
 281         SET_IVOR(34, SPEFloatingPointRound);
 282 #ifndef CONFIG_E200
 283         SET_IVOR(35, PerformanceMonitor);
 284 #endif
 285
 286         /* Establish the interrupt vector base */
 287         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 288         mtspr   SPRN_IVPR,r4
 289
 290         /* Setup the defaults for TLB entries */
 291         li      r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
 292 #ifdef CONFIG_E200
 293         oris    r2,r2,MAS4_TLBSELD(1)@h
 294 #endif
 295         mtspr   SPRN_MAS4, r2
 296
 297 #if 0
 298         /* Enable DOZE */
 299         mfspr   r2,SPRN_HID0
 300         oris    r2,r2,HID0_DOZE@h
 301         mtspr   SPRN_HID0, r2
 302 #endif
 303 #ifdef CONFIG_E200
 304         /* enable dedicated debug exception handling resources (Debug APU) */
 305         mfspr   r2,SPRN_HID0
 306         ori     r2,r2,HID0_DAPUEN@l
 307         mtspr   SPRN_HID0,r2
 308 #endif
 309
 310 #if !defined(CONFIG_BDI_SWITCH)
 311         /*
 312          * The Abatron BDI JTAG debugger does not tolerate others
 313          * mucking with the debug registers.
 314          */
 315         lis     r2,DBCR0_IDM@h
 316         mtspr   SPRN_DBCR0,r2
 317         isync
 318         /* clear any residual debug events */
 319         li      r2,-1
 320         mtspr   SPRN_DBSR,r2
 321 #endif
 322
 323         /*
 324          * This is where the main kernel code starts.
 325          */
 326
 327         /* ptr to current */
 328         lis     r2,init_task@h
 329         ori     r2,r2,init_task@l
 330
 331         /* ptr to current thread */
 332         addi    r4,r2,THREAD    /* init task's THREAD */
 333         mtspr   SPRN_SPRG3,r4
 334
 335         /* stack */
 336         lis     r1,init_thread_union@h
 337         ori     r1,r1,init_thread_union@l
 338         li      r0,0
 339         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 340
 341         bl      early_init
 342
 343         mfspr   r3,SPRN_TLB1CFG
 344         andi.   r3,r3,0xfff
 345         lis     r4,num_tlbcam_entries@ha
 346         stw     r3,num_tlbcam_entries@l(r4)
 347 /*
 348  * Decide what sort of machine this is and initialize the MMU.
 349  */
 350         mr      r3,r31
 351         mr      r4,r30
 352         mr      r5,r29
 353         mr      r6,r28
 354         mr      r7,r27
 355         bl      machine_init
 356         bl      MMU_init
 357
 358         /* Setup PTE pointers for the Abatron bdiGDB */
 359         lis     r6, swapper_pg_dir@h
 360         ori     r6, r6, swapper_pg_dir@l
 361         lis     r5, abatron_pteptrs@h
 362         ori     r5, r5, abatron_pteptrs@l
 363         lis     r4, KERNELBASE@h
 364         ori     r4, r4, KERNELBASE@l
 365         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 366         stw     r6, 0(r5)
 367
 368         /* Let's move on */
 369         lis     r4,start_kernel@h
 370         ori     r4,r4,start_kernel@l
 371         lis     r3,MSR_KERNEL@h
 372         ori     r3,r3,MSR_KERNEL@l
 373         mtspr   SPRN_SRR0,r4
 374         mtspr   SPRN_SRR1,r3
 375         rfi                     /* change context and jump to start_kernel */
 376
 377 /* Macros to hide the PTE size differences
 378  *
 379  * FIND_PTE -- walks the page tables given EA & pgdir pointer
 380  *   r10 -- EA of fault
 381  *   r11 -- PGDIR pointer
 382  *   r12 -- free
 383  *   label 2: is the bailout case
 384  *
 385  * if we find the pte (fall through):
 386  *   r11 is low pte word
 387  *   r12 is pointer to the pte
 388  */
 389 #ifdef CONFIG_PTE_64BIT
 390 #define PTE_FLAGS_OFFSET        4
 391 #define FIND_PTE        \
 392         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 393         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 394         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 395         beq     2f;                     /* Bail if no table */          \
 396         rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 397         lwz     r11, 4(r12);            /* Get pte entry */
 398 #else
 399 #define PTE_FLAGS_OFFSET        0
 400 #define FIND_PTE        \
 401         rlwimi  r11, r10, 12, 20, 29;   /* Create L1 (pgdir/pmd) address */     \
 402         lwz     r11, 0(r11);            /* Get L1 entry */                      \
 403         rlwinm. r12, r11, 0, 0, 19;     /* Extract L2 (pte) base address */     \
 404         beq     2f;                     /* Bail if no table */                  \
 405         rlwimi  r12, r10, 22, 20, 29;   /* Compute PTE address */               \
 406         lwz     r11, 0(r12);            /* Get Linux PTE */
 407 #endif
 408
 409 /*
 410  * Interrupt vector entry code
 411  *
 412  * The Book E MMUs are always on so we don't need to handle
 413  * interrupts in real mode as with previous PPC processors. In
 414  * this case we handle interrupts in the kernel virtual address
 415  * space.
 416  *
 417  * Interrupt vectors are dynamically placed relative to the
 418  * interrupt prefix as determined by the address of interrupt_base.
 419  * The interrupt vectors offsets are programmed using the labels
 420  * for each interrupt vector entry.
 421  *
 422  * Interrupt vectors must be aligned on a 16 byte boundary.
 423  * We align on a 32 byte cache line boundary for good measure.
 424  */
 425
 426 interrupt_base:
 427         /* Critical Input Interrupt */
 428         CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
 429
 430         /* Machine Check Interrupt */
 431 #ifdef CONFIG_E200
 432         /* no RFMCI, MCSRRs on E200 */
 433         CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 434 #else
 435         MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 436 #endif
 437
 438         /* Data Storage Interrupt */
 439         START_EXCEPTION(DataStorage)
 440         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 441         mtspr   SPRN_SPRG1, r11
 442         mtspr   SPRN_SPRG4W, r12
 443         mtspr   SPRN_SPRG5W, r13
 444         mfcr    r11
 445         mtspr   SPRN_SPRG7W, r11
 446
 447         /*
 448          * Check if it was a store fault, if not then bail
 449          * because a user tried to access a kernel or
 450          * read-protected page.  Otherwise, get the
 451          * offending address and handle it.
 452          */
 453         mfspr   r10, SPRN_ESR
 454         andis.  r10, r10, ESR_ST@h
 455         beq     2f
 456
 457         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 458
 459         /* If we are faulting a kernel address, we have to use the
 460          * kernel page tables.
 461          */
 462         lis     r11, TASK_SIZE@h
 463         ori     r11, r11, TASK_SIZE@l
 464         cmplw   0, r10, r11
 465         bge     2f
 466
 467         /* Get the PGD for the current thread */
 468 3:
 469         mfspr   r11,SPRN_SPRG3
 470         lwz     r11,PGDIR(r11)
 471 4:
 472         FIND_PTE
 473
 474         /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
 475         andi.   r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
 476         cmpwi   0, r13, _PAGE_RW|_PAGE_USER
 477         bne     2f                      /* Bail if not */
 478
 479         /* Update 'changed'. */
 480         ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 481         stw     r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
 482
 483         /* MAS2 not updated as the entry does exist in the tlb, this
 484            fault taken to detect state transition (eg: COW -> DIRTY)
 485          */
 486         andi.   r11, r11, _PAGE_HWEXEC
 487         rlwimi  r11, r11, 31, 27, 27    /* SX <- _PAGE_HWEXEC */
 488         ori     r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
 489
 490         /* update search PID in MAS6, AS = 0 */
 491         mfspr   r12, SPRN_PID0
 492         slwi    r12, r12, 16
 493         mtspr   SPRN_MAS6, r12
 494
 495         /* find the TLB index that caused the fault.  It has to be here. */
 496         tlbsx   0, r10
 497
 498         /* only update the perm bits, assume the RPN is fine */
 499         mfspr   r12, SPRN_MAS3
 500         rlwimi  r12, r11, 0, 20, 31
 501         mtspr   SPRN_MAS3,r12
 502         tlbwe
 503
 504         /* Done...restore registers and get out of here.  */
 505         mfspr   r11, SPRN_SPRG7R
 506         mtcr    r11
 507         mfspr   r13, SPRN_SPRG5R
 508         mfspr   r12, SPRN_SPRG4R
 509         mfspr   r11, SPRN_SPRG1
 510         mfspr   r10, SPRN_SPRG0
 511         rfi                     /* Force context change */
 512
 513 2:
 514         /*
 515          * The bailout.  Restore registers to pre-exception conditions
 516          * and call the heavyweights to help us out.
 517          */
 518         mfspr   r11, SPRN_SPRG7R
 519         mtcr    r11
 520         mfspr   r13, SPRN_SPRG5R
 521         mfspr   r12, SPRN_SPRG4R
 522         mfspr   r11, SPRN_SPRG1
 523         mfspr   r10, SPRN_SPRG0
 524         b       data_access
 525
 526         /* Instruction Storage Interrupt */
 527         INSTRUCTION_STORAGE_EXCEPTION
 528
 529         /* External Input Interrupt */
 530         EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
 531
 532         /* Alignment Interrupt */
 533         ALIGNMENT_EXCEPTION
 534
 535         /* Program Interrupt */
 536         PROGRAM_EXCEPTION
 537
 538         /* Floating Point Unavailable Interrupt */
 539 #ifdef CONFIG_PPC_FPU
 540         FP_UNAVAILABLE_EXCEPTION
 541 #else
 542 #ifdef CONFIG_E200
 543         /* E200 treats 'normal' floating point instructions as FP Unavail exception */
 544         EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
 545 #else
 546         EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
 547 #endif
 548 #endif
 549
 550         /* System Call Interrupt */
 551         START_EXCEPTION(SystemCall)
 552         NORMAL_EXCEPTION_PROLOG
 553         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 554
 555         /* Auxillary Processor Unavailable Interrupt */
 556         EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
 557
 558         /* Decrementer Interrupt */
 559         DECREMENTER_EXCEPTION
 560
 561         /* Fixed Internal Timer Interrupt */
 562         /* TODO: Add FIT support */
 563         EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
 564
 565         /* Watchdog Timer Interrupt */
 566 #ifdef CONFIG_BOOKE_WDT
 567         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
 568 #else
 569         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
 570 #endif
 571
 572         /* Data TLB Error Interrupt */
 573         START_EXCEPTION(DataTLBError)
 574         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 575         mtspr   SPRN_SPRG1, r11
 576         mtspr   SPRN_SPRG4W, r12
 577         mtspr   SPRN_SPRG5W, r13
 578         mfcr    r11
 579         mtspr   SPRN_SPRG7W, r11
 580         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 581
 582         /* If we are faulting a kernel address, we have to use the
 583          * kernel page tables.
 584          */
 585         lis     r11, TASK_SIZE@h
 586         ori     r11, r11, TASK_SIZE@l
 587         cmplw   5, r10, r11
 588         blt     5, 3f
 589         lis     r11, swapper_pg_dir@h
 590         ori     r11, r11, swapper_pg_dir@l
 591
 592         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 593         rlwinm  r12,r12,0,16,1
 594         mtspr   SPRN_MAS1,r12
 595
 596         b       4f
 597
 598         /* Get the PGD for the current thread */
 599 3:
 600         mfspr   r11,SPRN_SPRG3
 601         lwz     r11,PGDIR(r11)
 602
 603 4:
 604         FIND_PTE
 605         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 606         beq     2f                      /* Bail if not present */
 607
 608 #ifdef CONFIG_PTE_64BIT
 609         lwz     r13, 0(r12)
 610 #endif
 611         ori     r11, r11, _PAGE_ACCESSED
 612         stw     r11, PTE_FLAGS_OFFSET(r12)
 613
 614          /* Jump to common tlb load */
 615         b       finish_tlb_load
 616 2:
 617         /* The bailout.  Restore registers to pre-exception conditions
 618          * and call the heavyweights to help us out.
 619          */
 620         mfspr   r11, SPRN_SPRG7R
 621         mtcr    r11
 622         mfspr   r13, SPRN_SPRG5R
 623         mfspr   r12, SPRN_SPRG4R
 624         mfspr   r11, SPRN_SPRG1
 625         mfspr   r10, SPRN_SPRG0
 626         b       data_access
 627
 628         /* Instruction TLB Error Interrupt */
 629         /*
 630          * Nearly the same as above, except we get our
 631          * information from different registers and bailout
 632          * to a different point.
 633          */
 634         START_EXCEPTION(InstructionTLBError)
 635         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 636         mtspr   SPRN_SPRG1, r11
 637         mtspr   SPRN_SPRG4W, r12
 638         mtspr   SPRN_SPRG5W, r13
 639         mfcr    r11
 640         mtspr   SPRN_SPRG7W, r11
 641         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 642
 643         /* If we are faulting a kernel address, we have to use the
 644          * kernel page tables.
 645          */
 646         lis     r11, TASK_SIZE@h
 647         ori     r11, r11, TASK_SIZE@l
 648         cmplw   5, r10, r11
 649         blt     5, 3f
 650         lis     r11, swapper_pg_dir@h
 651         ori     r11, r11, swapper_pg_dir@l
 652
 653         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 654         rlwinm  r12,r12,0,16,1
 655         mtspr   SPRN_MAS1,r12
 656
 657         b       4f
 658
 659         /* Get the PGD for the current thread */
 660 3:
 661         mfspr   r11,SPRN_SPRG3
 662         lwz     r11,PGDIR(r11)
 663
 664 4:
 665         FIND_PTE
 666         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 667         beq     2f                      /* Bail if not present */
 668
 669 #ifdef CONFIG_PTE_64BIT
 670         lwz     r13, 0(r12)
 671 #endif
 672         ori     r11, r11, _PAGE_ACCESSED
 673         stw     r11, PTE_FLAGS_OFFSET(r12)
 674
 675         /* Jump to common TLB load point */
 676         b       finish_tlb_load
 677
 678 2:
 679         /* The bailout.  Restore registers to pre-exception conditions
 680          * and call the heavyweights to help us out.
 681          */
 682         mfspr   r11, SPRN_SPRG7R
 683         mtcr    r11
 684         mfspr   r13, SPRN_SPRG5R
 685         mfspr   r12, SPRN_SPRG4R
 686         mfspr   r11, SPRN_SPRG1
 687         mfspr   r10, SPRN_SPRG0
 688         b       InstructionStorage
 689
 690 #ifdef CONFIG_SPE
 691         /* SPE Unavailable */
 692         START_EXCEPTION(SPEUnavailable)
 693         NORMAL_EXCEPTION_PROLOG
 694         bne     load_up_spe
 695         addi    r3,r1,STACK_FRAME_OVERHEAD
 696         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 697 #else
 698         EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
 699 #endif /* CONFIG_SPE */
 700
 701         /* SPE Floating Point Data */
 702 #ifdef CONFIG_SPE
 703         EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
 704 #else
 705         EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
 706 #endif /* CONFIG_SPE */
 707
 708         /* SPE Floating Point Round */
 709         EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
 710
 711         /* Performance Monitor */
 712         EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
 713
 714
 715         /* Debug Interrupt */
 716         DEBUG_EXCEPTION
 717
 718 /*
 719  * Local functions
 720  */
 721
 722         /*
 723          * Data TLB exceptions will bail out to this point
 724          * if they can't resolve the lightweight TLB fault.
 725          */
 726 data_access:
 727         NORMAL_EXCEPTION_PROLOG
 728         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 729         stw     r5,_ESR(r11)
 730         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 731         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
 732         bne     1f
 733         EXC_XFER_EE_LITE(0x0300, handle_page_fault)
 734 1:
 735         addi    r3,r1,STACK_FRAME_OVERHEAD
 736         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
 737
 738 /*
 739
 740  * Both the instruction and data TLB miss get to this
 741  * point to load the TLB.
 742  *      r10 - EA of fault
 743  *      r11 - TLB (info from Linux PTE)
 744  *      r12, r13 - available to use
 745  *      CR5 - results of addr < TASK_SIZE
 746  *      MAS0, MAS1 - loaded with proper value when we get here
 747  *      MAS2, MAS3 - will need additional info from Linux PTE
 748  *      Upon exit, we reload everything and RFI.
 749  */
 750 finish_tlb_load:
 751         /*
 752          * We set execute, because we don't have the granularity to
 753          * properly set this at the page level (Linux problem).
 754          * Many of these bits are software only.  Bits we don't set
 755          * here we (properly should) assume have the appropriate value.
 756          */
 757
 758         mfspr   r12, SPRN_MAS2
 759 #ifdef CONFIG_PTE_64BIT
 760         rlwimi  r12, r11, 26, 24, 31    /* extract ...WIMGE from pte */
 761 #else
 762         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 763 #endif
 764         mtspr   SPRN_MAS2, r12
 765
 766         bge     5, 1f
 767
 768         /* is user addr */
 769         andi.   r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
 770         andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
 771         srwi    r10, r12, 1
 772         or      r12, r12, r10   /* Copy user perms into supervisor */
 773         iseleq  r12, 0, r12
 774         b       2f
 775
 776         /* is kernel addr */
 777 1:      rlwinm  r12, r11, 31, 29, 29    /* Extract _PAGE_HWWRITE into SW */
 778         ori     r12, r12, (MAS3_SX | MAS3_SR)
 779
 780 #ifdef CONFIG_PTE_64BIT
 781 2:      rlwimi  r12, r13, 24, 0, 7      /* grab RPN[32:39] */
 782         rlwimi  r12, r11, 24, 8, 19     /* grab RPN[40:51] */
 783         mtspr   SPRN_MAS3, r12
 784 BEGIN_FTR_SECTION
 785         srwi    r10, r13, 8             /* grab RPN[8:31] */
 786         mtspr   SPRN_MAS7, r10
 787 END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
 788 #else
 789 2:      rlwimi  r11, r12, 0, 20, 31     /* Extract RPN from PTE and merge with perms */
 790         mtspr   SPRN_MAS3, r11
 791 #endif
 792 #ifdef CONFIG_E200
 793         /* Round robin TLB1 entries assignment */
 794         mfspr   r12, SPRN_MAS0
 795
 796         /* Extract TLB1CFG(NENTRY) */
 797         mfspr   r11, SPRN_TLB1CFG
 798         andi.   r11, r11, 0xfff
 799
 800         /* Extract MAS0(NV) */
 801         andi.   r13, r12, 0xfff
 802         addi    r13, r13, 1
 803         cmpw    0, r13, r11
 804         addi    r12, r12, 1
 805
 806         /* check if we need to wrap */
 807         blt     7f
 808
 809         /* wrap back to first free tlbcam entry */
 810         lis     r13, tlbcam_index@ha
 811         lwz     r13, tlbcam_index@l(r13)
 812         rlwimi  r12, r13, 0, 20, 31
 813 7:
 814         mtspr   SPRN_MAS0,r12
 815 #endif /* CONFIG_E200 */
 816
 817         tlbwe
 818
 819         /* Done...restore registers and get out of here.  */
 820         mfspr   r11, SPRN_SPRG7R
 821         mtcr    r11
 822         mfspr   r13, SPRN_SPRG5R
 823         mfspr   r12, SPRN_SPRG4R
 824         mfspr   r11, SPRN_SPRG1
 825         mfspr   r10, SPRN_SPRG0
 826         rfi                                     /* Force context change */
 827
 828 #ifdef CONFIG_SPE
 829 /* Note that the SPE support is closely modeled after the AltiVec
 830  * support.  Changes to one are likely to be applicable to the
 831  * other!  */
 832 load_up_spe:
 833 /*
 834  * Disable SPE for the task which had SPE previously,
 835  * and save its SPE registers in its thread_struct.
 836  * Enables SPE for use in the kernel on return.
 837  * On SMP we know the SPE units are free, since we give it up every
 838  * switch.  -- Kumar
 839  */
 840         mfmsr   r5
 841         oris    r5,r5,MSR_SPE@h
 842         mtmsr   r5                      /* enable use of SPE now */
 843         isync
 844 /*
 845  * For SMP, we don't do lazy SPE switching because it just gets too
 846  * horrendously complex, especially when a task switches from one CPU
 847  * to another.  Instead we call giveup_spe in switch_to.
 848  */
 849 #ifndef CONFIG_SMP
 850         lis     r3,last_task_used_spe@ha
 851         lwz     r4,last_task_used_spe@l(r3)
 852         cmpi    0,r4,0
 853         beq     1f
 854         addi    r4,r4,THREAD    /* want THREAD of last_task_used_spe */
 855         SAVE_32EVRS(0,r10,r4)
 856         evxor   evr10, evr10, evr10     /* clear out evr10 */
 857         evmwumiaa evr10, evr10, evr10   /* evr10 <- ACC = 0 * 0 + ACC */
 858         li      r5,THREAD_ACC
 859         evstddx evr10, r4, r5           /* save off accumulator */
 860         lwz     r5,PT_REGS(r4)
 861         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 862         lis     r10,MSR_SPE@h
 863         andc    r4,r4,r10       /* disable SPE for previous task */
 864         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 865 1:
 866 #endif /* CONFIG_SMP */
 867         /* enable use of SPE after return */
 868         oris    r9,r9,MSR_SPE@h
 869         mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
 870         li      r4,1
 871         li      r10,THREAD_ACC
 872         stw     r4,THREAD_USED_SPE(r5)
 873         evlddx  evr4,r10,r5
 874         evmra   evr4,evr4
 875         REST_32EVRS(0,r10,r5)
 876 #ifndef CONFIG_SMP
 877         subi    r4,r5,THREAD
 878         stw     r4,last_task_used_spe@l(r3)
 879 #endif /* CONFIG_SMP */
 880         /* restore registers and return */
 881 2:      REST_4GPRS(3, r11)
 882         lwz     r10,_CCR(r11)
 883         REST_GPR(1, r11)
 884         mtcr    r10
 885         lwz     r10,_LINK(r11)
 886         mtlr    r10
 887         REST_GPR(10, r11)
 888         mtspr   SPRN_SRR1,r9
 889         mtspr   SPRN_SRR0,r12
 890         REST_GPR(9, r11)
 891         REST_GPR(12, r11)
 892         lwz     r11,GPR11(r11)
 893         SYNC
 894         rfi
 895
 896 /*
 897  * SPE unavailable trap from kernel - print a message, but let
 898  * the task use SPE in the kernel until it returns to user mode.
 899  */
 900 KernelSPE:
 901         lwz     r3,_MSR(r1)
 902         oris    r3,r3,MSR_SPE@h
 903         stw     r3,_MSR(r1)     /* enable use of SPE after return */
 904         lis     r3,87f@h
 905         ori     r3,r3,87f@l
 906         mr      r4,r2           /* current */
 907         lwz     r5,_NIP(r1)
 908         bl      printk
 909         b       ret_from_except
 910 87:     .string "SPE used in kernel  (task=%p, pc=%x)  \n"
 911         .align  4,0
 912
 913 #endif /* CONFIG_SPE */
 914
 915 /*
 916  * Global functions
 917  */
 918
 919 /*
 920  * extern void loadcam_entry(unsigned int index)
 921  *
 922  * Load TLBCAM[index] entry in to the L2 CAM MMU
 923  */
 924 _GLOBAL(loadcam_entry)
 925         lis     r4,TLBCAM@ha
 926         addi    r4,r4,TLBCAM@l
 927         mulli   r5,r3,20
 928         add     r3,r5,r4
 929         lwz     r4,0(r3)
 930         mtspr   SPRN_MAS0,r4
 931         lwz     r4,4(r3)
 932         mtspr   SPRN_MAS1,r4
 933         lwz     r4,8(r3)
 934         mtspr   SPRN_MAS2,r4
 935         lwz     r4,12(r3)
 936         mtspr   SPRN_MAS3,r4
 937         tlbwe
 938         isync
 939         blr
 940
 941 /*
 942  * extern void giveup_altivec(struct task_struct *prev)
 943  *
 944  * The e500 core does not have an AltiVec unit.
 945  */
 946 _GLOBAL(giveup_altivec)
 947         blr
 948
 949 #ifdef CONFIG_SPE
 950 /*
 951  * extern void giveup_spe(struct task_struct *prev)
 952  *
 953  */
 954 _GLOBAL(giveup_spe)
 955         mfmsr   r5
 956         oris    r5,r5,MSR_SPE@h
 957         SYNC
 958         mtmsr   r5                      /* enable use of SPE now */
 959         isync
 960         cmpi    0,r3,0
 961         beqlr-                          /* if no previous owner, done */
 962         addi    r3,r3,THREAD            /* want THREAD of task */
 963         lwz     r5,PT_REGS(r3)
 964         cmpi    0,r5,0
 965         SAVE_32EVRS(0, r4, r3)
 966         evxor   evr6, evr6, evr6        /* clear out evr6 */
 967         evmwumiaa evr6, evr6, evr6      /* evr6 <- ACC = 0 * 0 + ACC */
 968         li      r4,THREAD_ACC
 969         evstddx evr6, r4, r3            /* save off accumulator */
 970         mfspr   r6,SPRN_SPEFSCR
 971         stw     r6,THREAD_SPEFSCR(r3)   /* save spefscr register value */
 972         beq     1f
 973         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 974         lis     r3,MSR_SPE@h
 975         andc    r4,r4,r3                /* disable SPE for previous task */
 976         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 977 1:
 978 #ifndef CONFIG_SMP
 979         li      r5,0
 980         lis     r4,last_task_used_spe@ha
 981         stw     r5,last_task_used_spe@l(r4)
 982 #endif /* CONFIG_SMP */
 983         blr
 984 #endif /* CONFIG_SPE */
 985
 986 /*
 987  * extern void giveup_fpu(struct task_struct *prev)
 988  *
 989  * Not all FSL Book-E cores have an FPU
 990  */
 991 #ifndef CONFIG_PPC_FPU
 992 _GLOBAL(giveup_fpu)
 993         blr
 994 #endif
 995
 996 /*
 997  * extern void abort(void)
 998  *
 999  * At present, this routine just applies a system reset.
1000  */
1001 _GLOBAL(abort)
1002         li      r13,0
1003         mtspr   SPRN_DBCR0,r13          /* disable all debug events */
1004         isync
1005         mfmsr   r13
1006         ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
1007         mtmsr   r13
1008         isync
1009         mfspr   r13,SPRN_DBCR0
1010         lis     r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1011         mtspr   SPRN_DBCR0,r13
1012         isync
1013
1014 _GLOBAL(set_context)
1015
1016 #ifdef CONFIG_BDI_SWITCH
1017         /* Context switch the PTE pointer for the Abatron BDI2000.
1018          * The PGDIR is the second parameter.
1019          */
1020         lis     r5, abatron_pteptrs@h
1021         ori     r5, r5, abatron_pteptrs@l
1022         stw     r4, 0x4(r5)
1023 #endif
1024         mtspr   SPRN_PID,r3
1025         isync                   /* Force context change */
1026         blr
1027
1028 /*
1029  * We put a few things here that have to be page-aligned. This stuff
1030  * goes at the beginning of the data segment, which is page-aligned.
1031  */
1032         .data
1033         .align  12
1034         .globl  sdata
1035 sdata:
1036         .globl  empty_zero_page
1037 empty_zero_page:
1038         .space  4096
1039         .globl  swapper_pg_dir
1040 swapper_pg_dir:
1041         .space  4096
1042
1043 /* Reserved 4k for the critical exception stack & 4k for the machine
1044  * check stack per CPU for kernel mode exceptions */
1045         .section .bss
1046         .align 12
1047 exception_stack_bottom:
1048         .space  BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
1049         .globl  exception_stack_top
1050 exception_stack_top:
1051
1052 /*
1053  * This space gets a copy of optional info passed to us by the bootstrap
1054  * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
1055  */
1056         .globl  cmd_line
1057 cmd_line:
1058         .space  512
1059
1060 /*
1061  * Room for two PTE pointers, usually the kernel and current user pointers
1062  * to their respective root page table.
1063  */
1064 abatron_pteptrs:
1065         .space  8