arch/powerpc/kernel/head_fsl_booke.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2004 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *    Copyright 2004 Freescale Semiconductor, Inc
  25  *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  */
  32
  33 #include <linux/threads.h>
  34 #include <asm/processor.h>
  35 #include <asm/page.h>
  36 #include <asm/mmu.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/cputable.h>
  39 #include <asm/thread_info.h>
  40 #include <asm/ppc_asm.h>
  41 #include <asm/asm-offsets.h>
  42 #include "head_booke.h"
  43
  44 /* As with the other PowerPC ports, it is expected that when code
  45  * execution begins here, the following registers contain valid, yet
  46  * optional, information:
  47  *
  48  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  49  *   r4 - Starting address of the init RAM disk
  50  *   r5 - Ending address of the init RAM disk
  51  *   r6 - Start of kernel command line string (e.g. "mem=128")
  52  *   r7 - End of kernel command line string
  53  *
  54  */
  55         .section        .text.head, "ax"
  56 _ENTRY(_stext);
  57 _ENTRY(_start);
  58         /*
  59          * Reserve a word at a fixed location to store the address
  60          * of abatron_pteptrs
  61          */
  62         nop
  63 /*
  64  * Save parameters we are passed
  65  */
  66         mr      r31,r3
  67         mr      r30,r4
  68         mr      r29,r5
  69         mr      r28,r6
  70         mr      r27,r7
  71         li      r25,0           /* phys kernel start (low) */
  72         li      r24,0           /* CPU number */
  73         li      r23,0           /* phys kernel start (high) */
  74
  75 /* We try to not make any assumptions about how the boot loader
  76  * setup or used the TLBs.  We invalidate all mappings from the
  77  * boot loader and load a single entry in TLB1[0] to map the
  78  * first 64M of kernel memory.  Any boot info passed from the
  79  * bootloader needs to live in this first 64M.
  80  *
  81  * Requirement on bootloader:
  82  *  - The page we're executing in needs to reside in TLB1 and
  83  *    have IPROT=1.  If not an invalidate broadcast could
  84  *    evict the entry we're currently executing in.
  85  *
  86  *  r3 = Index of TLB1 were executing in
  87  *  r4 = Current MSR[IS]
  88  *  r5 = Index of TLB1 temp mapping
  89  *
  90  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
  91  * if needed
  92  */
  93
  94 /* 1. Find the index of the entry we're executing in */
  95         bl      invstr                          /* Find our address */
  96 invstr: mflr    r6                              /* Make it accessible */
  97         mfmsr   r7
  98         rlwinm  r4,r7,27,31,31                  /* extract MSR[IS] */
  99         mfspr   r7, SPRN_PID0
 100         slwi    r7,r7,16
 101         or      r7,r7,r4
 102         mtspr   SPRN_MAS6,r7
 103         tlbsx   0,r6                            /* search MSR[IS], SPID=PID0 */
 104 #ifndef CONFIG_E200
 105         mfspr   r7,SPRN_MAS1
 106         andis.  r7,r7,MAS1_VALID@h
 107         bne     match_TLB
 108         mfspr   r7,SPRN_PID1
 109         slwi    r7,r7,16
 110         or      r7,r7,r4
 111         mtspr   SPRN_MAS6,r7
 112         tlbsx   0,r6                            /* search MSR[IS], SPID=PID1 */
 113         mfspr   r7,SPRN_MAS1
 114         andis.  r7,r7,MAS1_VALID@h
 115         bne     match_TLB
 116         mfspr   r7, SPRN_PID2
 117         slwi    r7,r7,16
 118         or      r7,r7,r4
 119         mtspr   SPRN_MAS6,r7
 120         tlbsx   0,r6                            /* Fall through, we had to match */
 121 #endif
 122 match_TLB:
 123         mfspr   r7,SPRN_MAS0
 124         rlwinm  r3,r7,16,20,31                  /* Extract MAS0(Entry) */
 125
 126         mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
 127         oris    r7,r7,MAS1_IPROT@h
 128         mtspr   SPRN_MAS1,r7
 129         tlbwe
 130
 131 /* 2. Invalidate all entries except the entry we're executing in */
 132         mfspr   r9,SPRN_TLB1CFG
 133         andi.   r9,r9,0xfff
 134         li      r6,0                            /* Set Entry counter to 0 */
 135 1:      lis     r7,0x1000                       /* Set MAS0(TLBSEL) = 1 */
 136         rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
 137         mtspr   SPRN_MAS0,r7
 138         tlbre
 139         mfspr   r7,SPRN_MAS1
 140         rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
 141         cmpw    r3,r6
 142         beq     skpinv                          /* Dont update the current execution TLB */
 143         mtspr   SPRN_MAS1,r7
 144         tlbwe
 145         isync
 146 skpinv: addi    r6,r6,1                         /* Increment */
 147         cmpw    r6,r9                           /* Are we done? */
 148         bne     1b                              /* If not, repeat */
 149
 150         /* Invalidate TLB0 */
 151         li      r6,0x04
 152         tlbivax 0,r6
 153 #ifdef CONFIG_SMP
 154         tlbsync
 155 #endif
 156         /* Invalidate TLB1 */
 157         li      r6,0x0c
 158         tlbivax 0,r6
 159 #ifdef CONFIG_SMP
 160         tlbsync
 161 #endif
 162         msync
 163
 164 /* 3. Setup a temp mapping and jump to it */
 165         andi.   r5, r3, 0x1     /* Find an entry not used and is non-zero */
 166         addi    r5, r5, 0x1
 167         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 168         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 169         mtspr   SPRN_MAS0,r7
 170         tlbre
 171
 172         /* grab and fixup the RPN */
 173         mfspr   r6,SPRN_MAS1    /* extract MAS1[SIZE] */
 174         rlwinm  r6,r6,25,27,30
 175         li      r8,-1
 176         addi    r6,r6,10
 177         slw     r6,r8,r6        /* convert to mask */
 178
 179         bl      1f              /* Find our address */
 180 1:      mflr    r7
 181
 182         mfspr   r8,SPRN_MAS3
 183 #ifdef CONFIG_PHYS_64BIT
 184         mfspr   r23,SPRN_MAS7
 185 #endif
 186         and     r8,r6,r8
 187         subfic  r9,r6,-4096
 188         and     r9,r9,r7
 189
 190         or      r25,r8,r9
 191         ori     r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
 192
 193         /* Just modify the entry ID and EPN for the temp mapping */
 194         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 195         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 196         mtspr   SPRN_MAS0,r7
 197         xori    r6,r4,1         /* Setup TMP mapping in the other Address space */
 198         slwi    r6,r6,12
 199         oris    r6,r6,(MAS1_VALID|MAS1_IPROT)@h
 200         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 201         mtspr   SPRN_MAS1,r6
 202         mfspr   r6,SPRN_MAS2
 203         li      r7,0            /* temp EPN = 0 */
 204         rlwimi  r7,r6,0,20,31
 205         mtspr   SPRN_MAS2,r7
 206         mtspr   SPRN_MAS3,r8
 207         tlbwe
 208
 209         xori    r6,r4,1
 210         slwi    r6,r6,5         /* setup new context with other address space */
 211         bl      1f              /* Find our address */
 212 1:      mflr    r9
 213         rlwimi  r7,r9,0,20,31
 214         addi    r7,r7,24
 215         mtspr   SPRN_SRR0,r7
 216         mtspr   SPRN_SRR1,r6
 217         rfi
 218
 219 /* 4. Clear out PIDs & Search info */
 220         li      r6,0
 221         mtspr   SPRN_PID0,r6
 222 #ifndef CONFIG_E200
 223         mtspr   SPRN_PID1,r6
 224         mtspr   SPRN_PID2,r6
 225 #endif
 226         mtspr   SPRN_MAS6,r6
 227
 228 /* 5. Invalidate mapping we started in */
 229         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 230         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 231         mtspr   SPRN_MAS0,r7
 232         tlbre
 233         mfspr   r6,SPRN_MAS1
 234         rlwinm  r6,r6,0,2,0     /* clear IPROT */
 235         mtspr   SPRN_MAS1,r6
 236         tlbwe
 237         /* Invalidate TLB1 */
 238         li      r9,0x0c
 239         tlbivax 0,r9
 240 #ifdef CONFIG_SMP
 241         tlbsync
 242 #endif
 243         msync
 244
 245 /* 6. Setup KERNELBASE mapping in TLB1[0] */
 246         lis     r6,0x1000               /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
 247         mtspr   SPRN_MAS0,r6
 248         lis     r6,(MAS1_VALID|MAS1_IPROT)@h
 249         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
 250         mtspr   SPRN_MAS1,r6
 251         li      r7,0
 252         lis     r6,PAGE_OFFSET@h
 253         ori     r6,r6,PAGE_OFFSET@l
 254         rlwimi  r6,r7,0,20,31
 255         mtspr   SPRN_MAS2,r6
 256         mtspr   SPRN_MAS3,r8
 257         tlbwe
 258
 259 /* 7. Jump to KERNELBASE mapping */
 260         lis     r6,KERNELBASE@h
 261         ori     r6,r6,KERNELBASE@l
 262         rlwimi  r6,r7,0,20,31
 263         lis     r7,MSR_KERNEL@h
 264         ori     r7,r7,MSR_KERNEL@l
 265         bl      1f                      /* Find our address */
 266 1:      mflr    r9
 267         rlwimi  r6,r9,0,20,31
 268         addi    r6,r6,24
 269         mtspr   SPRN_SRR0,r6
 270         mtspr   SPRN_SRR1,r7
 271         rfi                             /* start execution out of TLB1[0] entry */
 272
 273 /* 8. Clear out the temp mapping */
 274         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 275         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 276         mtspr   SPRN_MAS0,r7
 277         tlbre
 278         mfspr   r8,SPRN_MAS1
 279         rlwinm  r8,r8,0,2,0     /* clear IPROT */
 280         mtspr   SPRN_MAS1,r8
 281         tlbwe
 282         /* Invalidate TLB1 */
 283         li      r9,0x0c
 284         tlbivax 0,r9
 285 #ifdef CONFIG_SMP
 286         tlbsync
 287 #endif
 288         msync
 289
 290         /* Establish the interrupt vector offsets */
 291         SET_IVOR(0,  CriticalInput);
 292         SET_IVOR(1,  MachineCheck);
 293         SET_IVOR(2,  DataStorage);
 294         SET_IVOR(3,  InstructionStorage);
 295         SET_IVOR(4,  ExternalInput);
 296         SET_IVOR(5,  Alignment);
 297         SET_IVOR(6,  Program);
 298         SET_IVOR(7,  FloatingPointUnavailable);
 299         SET_IVOR(8,  SystemCall);
 300         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 301         SET_IVOR(10, Decrementer);
 302         SET_IVOR(11, FixedIntervalTimer);
 303         SET_IVOR(12, WatchdogTimer);
 304         SET_IVOR(13, DataTLBError);
 305         SET_IVOR(14, InstructionTLBError);
 306         SET_IVOR(15, DebugDebug);
 307 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
 308         SET_IVOR(15, DebugCrit);
 309 #endif
 310         SET_IVOR(32, SPEUnavailable);
 311         SET_IVOR(33, SPEFloatingPointData);
 312         SET_IVOR(34, SPEFloatingPointRound);
 313 #ifndef CONFIG_E200
 314         SET_IVOR(35, PerformanceMonitor);
 315 #endif
 316 #ifdef CONFIG_PPC_E500MC
 317         SET_IVOR(36, Doorbell);
 318 #endif
 319
 320         /* Establish the interrupt vector base */
 321         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 322         mtspr   SPRN_IVPR,r4
 323
 324         /* Setup the defaults for TLB entries */
 325         li      r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
 326 #ifdef CONFIG_E200
 327         oris    r2,r2,MAS4_TLBSELD(1)@h
 328 #endif
 329         mtspr   SPRN_MAS4, r2
 330
 331 #if 0
 332         /* Enable DOZE */
 333         mfspr   r2,SPRN_HID0
 334         oris    r2,r2,HID0_DOZE@h
 335         mtspr   SPRN_HID0, r2
 336 #endif
 337 #ifdef CONFIG_E200
 338         /* enable dedicated debug exception handling resources (Debug APU) */
 339         mfspr   r2,SPRN_HID0
 340         ori     r2,r2,HID0_DAPUEN@l
 341         mtspr   SPRN_HID0,r2
 342 #endif
 343
 344 #if !defined(CONFIG_BDI_SWITCH)
 345         /*
 346          * The Abatron BDI JTAG debugger does not tolerate others
 347          * mucking with the debug registers.
 348          */
 349         lis     r2,DBCR0_IDM@h
 350         mtspr   SPRN_DBCR0,r2
 351         isync
 352         /* clear any residual debug events */
 353         li      r2,-1
 354         mtspr   SPRN_DBSR,r2
 355 #endif
 356
 357         /*
 358          * This is where the main kernel code starts.
 359          */
 360
 361         /* ptr to current */
 362         lis     r2,init_task@h
 363         ori     r2,r2,init_task@l
 364
 365         /* ptr to current thread */
 366         addi    r4,r2,THREAD    /* init task's THREAD */
 367         mtspr   SPRN_SPRG3,r4
 368
 369         /* stack */
 370         lis     r1,init_thread_union@h
 371         ori     r1,r1,init_thread_union@l
 372         li      r0,0
 373         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 374
 375         bl      early_init
 376
 377 #ifdef CONFIG_RELOCATABLE
 378         lis     r3,kernstart_addr@ha
 379         la      r3,kernstart_addr@l(r3)
 380 #ifdef CONFIG_PHYS_64BIT
 381         stw     r23,0(r3)
 382         stw     r25,4(r3)
 383 #else
 384         stw     r25,0(r3)
 385 #endif
 386 #endif
 387
 388         mfspr   r3,SPRN_TLB1CFG
 389         andi.   r3,r3,0xfff
 390         lis     r4,num_tlbcam_entries@ha
 391         stw     r3,num_tlbcam_entries@l(r4)
 392 /*
 393  * Decide what sort of machine this is and initialize the MMU.
 394  */
 395         mr      r3,r31
 396         mr      r4,r30
 397         mr      r5,r29
 398         mr      r6,r28
 399         mr      r7,r27
 400         bl      machine_init
 401         bl      MMU_init
 402
 403         /* Setup PTE pointers for the Abatron bdiGDB */
 404         lis     r6, swapper_pg_dir@h
 405         ori     r6, r6, swapper_pg_dir@l
 406         lis     r5, abatron_pteptrs@h
 407         ori     r5, r5, abatron_pteptrs@l
 408         lis     r4, KERNELBASE@h
 409         ori     r4, r4, KERNELBASE@l
 410         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 411         stw     r6, 0(r5)
 412
 413         /* Let's move on */
 414         lis     r4,start_kernel@h
 415         ori     r4,r4,start_kernel@l
 416         lis     r3,MSR_KERNEL@h
 417         ori     r3,r3,MSR_KERNEL@l
 418         mtspr   SPRN_SRR0,r4
 419         mtspr   SPRN_SRR1,r3
 420         rfi                     /* change context and jump to start_kernel */
 421
 422 /* Macros to hide the PTE size differences
 423  *
 424  * FIND_PTE -- walks the page tables given EA & pgdir pointer
 425  *   r10 -- EA of fault
 426  *   r11 -- PGDIR pointer
 427  *   r12 -- free
 428  *   label 2: is the bailout case
 429  *
 430  * if we find the pte (fall through):
 431  *   r11 is low pte word
 432  *   r12 is pointer to the pte
 433  */
 434 #ifdef CONFIG_PTE_64BIT
 435 #define PTE_FLAGS_OFFSET        4
 436 #define FIND_PTE        \
 437         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 438         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 439         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 440         beq     2f;                     /* Bail if no table */          \
 441         rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 442         lwz     r11, 4(r12);            /* Get pte entry */
 443 #else
 444 #define PTE_FLAGS_OFFSET        0
 445 #define FIND_PTE        \
 446         rlwimi  r11, r10, 12, 20, 29;   /* Create L1 (pgdir/pmd) address */     \
 447         lwz     r11, 0(r11);            /* Get L1 entry */                      \
 448         rlwinm. r12, r11, 0, 0, 19;     /* Extract L2 (pte) base address */     \
 449         beq     2f;                     /* Bail if no table */                  \
 450         rlwimi  r12, r10, 22, 20, 29;   /* Compute PTE address */               \
 451         lwz     r11, 0(r12);            /* Get Linux PTE */
 452 #endif
 453
 454 /*
 455  * Interrupt vector entry code
 456  *
 457  * The Book E MMUs are always on so we don't need to handle
 458  * interrupts in real mode as with previous PPC processors. In
 459  * this case we handle interrupts in the kernel virtual address
 460  * space.
 461  *
 462  * Interrupt vectors are dynamically placed relative to the
 463  * interrupt prefix as determined by the address of interrupt_base.
 464  * The interrupt vectors offsets are programmed using the labels
 465  * for each interrupt vector entry.
 466  *
 467  * Interrupt vectors must be aligned on a 16 byte boundary.
 468  * We align on a 32 byte cache line boundary for good measure.
 469  */
 470
 471 interrupt_base:
 472         /* Critical Input Interrupt */
 473         CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
 474
 475         /* Machine Check Interrupt */
 476 #ifdef CONFIG_E200
 477         /* no RFMCI, MCSRRs on E200 */
 478         CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 479 #else
 480         MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 481 #endif
 482
 483         /* Data Storage Interrupt */
 484         START_EXCEPTION(DataStorage)
 485         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 486         mtspr   SPRN_SPRG1, r11
 487         mtspr   SPRN_SPRG4W, r12
 488         mtspr   SPRN_SPRG5W, r13
 489         mfcr    r11
 490         mtspr   SPRN_SPRG7W, r11
 491
 492         /*
 493          * Check if it was a store fault, if not then bail
 494          * because a user tried to access a kernel or
 495          * read-protected page.  Otherwise, get the
 496          * offending address and handle it.
 497          */
 498         mfspr   r10, SPRN_ESR
 499         andis.  r10, r10, ESR_ST@h
 500         beq     2f
 501
 502         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 503
 504         /* If we are faulting a kernel address, we have to use the
 505          * kernel page tables.
 506          */
 507         lis     r11, PAGE_OFFSET@h
 508         cmplw   0, r10, r11
 509         bge     2f
 510
 511         /* Get the PGD for the current thread */
 512 3:
 513         mfspr   r11,SPRN_SPRG3
 514         lwz     r11,PGDIR(r11)
 515 4:
 516         FIND_PTE
 517
 518         /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
 519         andi.   r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
 520         cmpwi   0, r13, _PAGE_RW|_PAGE_USER
 521         bne     2f                      /* Bail if not */
 522
 523         /* Update 'changed'. */
 524         ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 525         stw     r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
 526
 527         /* MAS2 not updated as the entry does exist in the tlb, this
 528            fault taken to detect state transition (eg: COW -> DIRTY)
 529          */
 530         andi.   r11, r11, _PAGE_HWEXEC
 531         rlwimi  r11, r11, 31, 27, 27    /* SX <- _PAGE_HWEXEC */
 532         ori     r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
 533
 534         /* update search PID in MAS6, AS = 0 */
 535         mfspr   r12, SPRN_PID0
 536         slwi    r12, r12, 16
 537         mtspr   SPRN_MAS6, r12
 538
 539         /* find the TLB index that caused the fault.  It has to be here. */
 540         tlbsx   0, r10
 541
 542         /* only update the perm bits, assume the RPN is fine */
 543         mfspr   r12, SPRN_MAS3
 544         rlwimi  r12, r11, 0, 20, 31
 545         mtspr   SPRN_MAS3,r12
 546         tlbwe
 547
 548         /* Done...restore registers and get out of here.  */
 549         mfspr   r11, SPRN_SPRG7R
 550         mtcr    r11
 551         mfspr   r13, SPRN_SPRG5R
 552         mfspr   r12, SPRN_SPRG4R
 553         mfspr   r11, SPRN_SPRG1
 554         mfspr   r10, SPRN_SPRG0
 555         rfi                     /* Force context change */
 556
 557 2:
 558         /*
 559          * The bailout.  Restore registers to pre-exception conditions
 560          * and call the heavyweights to help us out.
 561          */
 562         mfspr   r11, SPRN_SPRG7R
 563         mtcr    r11
 564         mfspr   r13, SPRN_SPRG5R
 565         mfspr   r12, SPRN_SPRG4R
 566         mfspr   r11, SPRN_SPRG1
 567         mfspr   r10, SPRN_SPRG0
 568         b       data_access
 569
 570         /* Instruction Storage Interrupt */
 571         INSTRUCTION_STORAGE_EXCEPTION
 572
 573         /* External Input Interrupt */
 574         EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
 575
 576         /* Alignment Interrupt */
 577         ALIGNMENT_EXCEPTION
 578
 579         /* Program Interrupt */
 580         PROGRAM_EXCEPTION
 581
 582         /* Floating Point Unavailable Interrupt */
 583 #ifdef CONFIG_PPC_FPU
 584         FP_UNAVAILABLE_EXCEPTION
 585 #else
 586 #ifdef CONFIG_E200
 587         /* E200 treats 'normal' floating point instructions as FP Unavail exception */
 588         EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
 589 #else
 590         EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
 591 #endif
 592 #endif
 593
 594         /* System Call Interrupt */
 595         START_EXCEPTION(SystemCall)
 596         NORMAL_EXCEPTION_PROLOG
 597         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 598
 599         /* Auxillary Processor Unavailable Interrupt */
 600         EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
 601
 602         /* Decrementer Interrupt */
 603         DECREMENTER_EXCEPTION
 604
 605         /* Fixed Internal Timer Interrupt */
 606         /* TODO: Add FIT support */
 607         EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
 608
 609         /* Watchdog Timer Interrupt */
 610 #ifdef CONFIG_BOOKE_WDT
 611         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
 612 #else
 613         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
 614 #endif
 615
 616         /* Data TLB Error Interrupt */
 617         START_EXCEPTION(DataTLBError)
 618         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 619         mtspr   SPRN_SPRG1, r11
 620         mtspr   SPRN_SPRG4W, r12
 621         mtspr   SPRN_SPRG5W, r13
 622         mfcr    r11
 623         mtspr   SPRN_SPRG7W, r11
 624         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 625
 626         /* If we are faulting a kernel address, we have to use the
 627          * kernel page tables.
 628          */
 629         lis     r11, PAGE_OFFSET@h
 630         cmplw   5, r10, r11
 631         blt     5, 3f
 632         lis     r11, swapper_pg_dir@h
 633         ori     r11, r11, swapper_pg_dir@l
 634
 635         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 636         rlwinm  r12,r12,0,16,1
 637         mtspr   SPRN_MAS1,r12
 638
 639         b       4f
 640
 641         /* Get the PGD for the current thread */
 642 3:
 643         mfspr   r11,SPRN_SPRG3
 644         lwz     r11,PGDIR(r11)
 645
 646 4:
 647         FIND_PTE
 648         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 649         beq     2f                      /* Bail if not present */
 650
 651 #ifdef CONFIG_PTE_64BIT
 652         lwz     r13, 0(r12)
 653 #endif
 654         ori     r11, r11, _PAGE_ACCESSED
 655         stw     r11, PTE_FLAGS_OFFSET(r12)
 656
 657          /* Jump to common tlb load */
 658         b       finish_tlb_load
 659 2:
 660         /* The bailout.  Restore registers to pre-exception conditions
 661          * and call the heavyweights to help us out.
 662          */
 663         mfspr   r11, SPRN_SPRG7R
 664         mtcr    r11
 665         mfspr   r13, SPRN_SPRG5R
 666         mfspr   r12, SPRN_SPRG4R
 667         mfspr   r11, SPRN_SPRG1
 668         mfspr   r10, SPRN_SPRG0
 669         b       data_access
 670
 671         /* Instruction TLB Error Interrupt */
 672         /*
 673          * Nearly the same as above, except we get our
 674          * information from different registers and bailout
 675          * to a different point.
 676          */
 677         START_EXCEPTION(InstructionTLBError)
 678         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 679         mtspr   SPRN_SPRG1, r11
 680         mtspr   SPRN_SPRG4W, r12
 681         mtspr   SPRN_SPRG5W, r13
 682         mfcr    r11
 683         mtspr   SPRN_SPRG7W, r11
 684         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 685
 686         /* If we are faulting a kernel address, we have to use the
 687          * kernel page tables.
 688          */
 689         lis     r11, PAGE_OFFSET@h
 690         cmplw   5, r10, r11
 691         blt     5, 3f
 692         lis     r11, swapper_pg_dir@h
 693         ori     r11, r11, swapper_pg_dir@l
 694
 695         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 696         rlwinm  r12,r12,0,16,1
 697         mtspr   SPRN_MAS1,r12
 698
 699         b       4f
 700
 701         /* Get the PGD for the current thread */
 702 3:
 703         mfspr   r11,SPRN_SPRG3
 704         lwz     r11,PGDIR(r11)
 705
 706 4:
 707         FIND_PTE
 708         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 709         beq     2f                      /* Bail if not present */
 710
 711 #ifdef CONFIG_PTE_64BIT
 712         lwz     r13, 0(r12)
 713 #endif
 714         ori     r11, r11, _PAGE_ACCESSED
 715         stw     r11, PTE_FLAGS_OFFSET(r12)
 716
 717         /* Jump to common TLB load point */
 718         b       finish_tlb_load
 719
 720 2:
 721         /* The bailout.  Restore registers to pre-exception conditions
 722          * and call the heavyweights to help us out.
 723          */
 724         mfspr   r11, SPRN_SPRG7R
 725         mtcr    r11
 726         mfspr   r13, SPRN_SPRG5R
 727         mfspr   r12, SPRN_SPRG4R
 728         mfspr   r11, SPRN_SPRG1
 729         mfspr   r10, SPRN_SPRG0
 730         b       InstructionStorage
 731
 732 #ifdef CONFIG_SPE
 733         /* SPE Unavailable */
 734         START_EXCEPTION(SPEUnavailable)
 735         NORMAL_EXCEPTION_PROLOG
 736         bne     load_up_spe
 737         addi    r3,r1,STACK_FRAME_OVERHEAD
 738         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 739 #else
 740         EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
 741 #endif /* CONFIG_SPE */
 742
 743         /* SPE Floating Point Data */
 744 #ifdef CONFIG_SPE
 745         EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
 746 #else
 747         EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
 748 #endif /* CONFIG_SPE */
 749
 750         /* SPE Floating Point Round */
 751         EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
 752
 753         /* Performance Monitor */
 754         EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
 755
 756 #ifdef CONFIG_PPC_E500MC
 757         EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE)
 758 #endif
 759
 760         /* Debug Interrupt */
 761         DEBUG_DEBUG_EXCEPTION
 762 #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
 763         DEBUG_CRIT_EXCEPTION
 764 #endif
 765
 766 /*
 767  * Local functions
 768  */
 769
 770         /*
 771          * Data TLB exceptions will bail out to this point
 772          * if they can't resolve the lightweight TLB fault.
 773          */
 774 data_access:
 775         NORMAL_EXCEPTION_PROLOG
 776         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 777         stw     r5,_ESR(r11)
 778         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 779         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
 780         bne     1f
 781         EXC_XFER_EE_LITE(0x0300, handle_page_fault)
 782 1:
 783         addi    r3,r1,STACK_FRAME_OVERHEAD
 784         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
 785
 786 /*
 787
 788  * Both the instruction and data TLB miss get to this
 789  * point to load the TLB.
 790  *      r10 - EA of fault
 791  *      r11 - TLB (info from Linux PTE)
 792  *      r12, r13 - available to use
 793  *      CR5 - results of addr >= PAGE_OFFSET
 794  *      MAS0, MAS1 - loaded with proper value when we get here
 795  *      MAS2, MAS3 - will need additional info from Linux PTE
 796  *      Upon exit, we reload everything and RFI.
 797  */
 798 finish_tlb_load:
 799         /*
 800          * We set execute, because we don't have the granularity to
 801          * properly set this at the page level (Linux problem).
 802          * Many of these bits are software only.  Bits we don't set
 803          * here we (properly should) assume have the appropriate value.
 804          */
 805
 806         mfspr   r12, SPRN_MAS2
 807 #ifdef CONFIG_PTE_64BIT
 808         rlwimi  r12, r11, 26, 24, 31    /* extract ...WIMGE from pte */
 809 #else
 810         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 811 #endif
 812         mtspr   SPRN_MAS2, r12
 813
 814         bge     5, 1f
 815
 816         /* is user addr */
 817         andi.   r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
 818         andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
 819         srwi    r10, r12, 1
 820         or      r12, r12, r10   /* Copy user perms into supervisor */
 821         iseleq  r12, 0, r12
 822         b       2f
 823
 824         /* is kernel addr */
 825 1:      rlwinm  r12, r11, 31, 29, 29    /* Extract _PAGE_HWWRITE into SW */
 826         ori     r12, r12, (MAS3_SX | MAS3_SR)
 827
 828 #ifdef CONFIG_PTE_64BIT
 829 2:      rlwimi  r12, r13, 24, 0, 7      /* grab RPN[32:39] */
 830         rlwimi  r12, r11, 24, 8, 19     /* grab RPN[40:51] */
 831         mtspr   SPRN_MAS3, r12
 832 BEGIN_FTR_SECTION
 833         srwi    r10, r13, 8             /* grab RPN[8:31] */
 834         mtspr   SPRN_MAS7, r10
 835 END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
 836 #else
 837 2:      rlwimi  r11, r12, 0, 20, 31     /* Extract RPN from PTE and merge with perms */
 838         mtspr   SPRN_MAS3, r11
 839 #endif
 840 #ifdef CONFIG_E200
 841         /* Round robin TLB1 entries assignment */
 842         mfspr   r12, SPRN_MAS0
 843
 844         /* Extract TLB1CFG(NENTRY) */
 845         mfspr   r11, SPRN_TLB1CFG
 846         andi.   r11, r11, 0xfff
 847
 848         /* Extract MAS0(NV) */
 849         andi.   r13, r12, 0xfff
 850         addi    r13, r13, 1
 851         cmpw    0, r13, r11
 852         addi    r12, r12, 1
 853
 854         /* check if we need to wrap */
 855         blt     7f
 856
 857         /* wrap back to first free tlbcam entry */
 858         lis     r13, tlbcam_index@ha
 859         lwz     r13, tlbcam_index@l(r13)
 860         rlwimi  r12, r13, 0, 20, 31
 861 7:
 862         mtspr   SPRN_MAS0,r12
 863 #endif /* CONFIG_E200 */
 864
 865         tlbwe
 866
 867         /* Done...restore registers and get out of here.  */
 868         mfspr   r11, SPRN_SPRG7R
 869         mtcr    r11
 870         mfspr   r13, SPRN_SPRG5R
 871         mfspr   r12, SPRN_SPRG4R
 872         mfspr   r11, SPRN_SPRG1
 873         mfspr   r10, SPRN_SPRG0
 874         rfi                                     /* Force context change */
 875
 876 #ifdef CONFIG_SPE
 877 /* Note that the SPE support is closely modeled after the AltiVec
 878  * support.  Changes to one are likely to be applicable to the
 879  * other!  */
 880 load_up_spe:
 881 /*
 882  * Disable SPE for the task which had SPE previously,
 883  * and save its SPE registers in its thread_struct.
 884  * Enables SPE for use in the kernel on return.
 885  * On SMP we know the SPE units are free, since we give it up every
 886  * switch.  -- Kumar
 887  */
 888         mfmsr   r5
 889         oris    r5,r5,MSR_SPE@h
 890         mtmsr   r5                      /* enable use of SPE now */
 891         isync
 892 /*
 893  * For SMP, we don't do lazy SPE switching because it just gets too
 894  * horrendously complex, especially when a task switches from one CPU
 895  * to another.  Instead we call giveup_spe in switch_to.
 896  */
 897 #ifndef CONFIG_SMP
 898         lis     r3,last_task_used_spe@ha
 899         lwz     r4,last_task_used_spe@l(r3)
 900         cmpi    0,r4,0
 901         beq     1f
 902         addi    r4,r4,THREAD    /* want THREAD of last_task_used_spe */
 903         SAVE_32EVRS(0,r10,r4)
 904         evxor   evr10, evr10, evr10     /* clear out evr10 */
 905         evmwumiaa evr10, evr10, evr10   /* evr10 <- ACC = 0 * 0 + ACC */
 906         li      r5,THREAD_ACC
 907         evstddx evr10, r4, r5           /* save off accumulator */
 908         lwz     r5,PT_REGS(r4)
 909         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 910         lis     r10,MSR_SPE@h
 911         andc    r4,r4,r10       /* disable SPE for previous task */
 912         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 913 1:
 914 #endif /* !CONFIG_SMP */
 915         /* enable use of SPE after return */
 916         oris    r9,r9,MSR_SPE@h
 917         mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
 918         li      r4,1
 919         li      r10,THREAD_ACC
 920         stw     r4,THREAD_USED_SPE(r5)
 921         evlddx  evr4,r10,r5
 922         evmra   evr4,evr4
 923         REST_32EVRS(0,r10,r5)
 924 #ifndef CONFIG_SMP
 925         subi    r4,r5,THREAD
 926         stw     r4,last_task_used_spe@l(r3)
 927 #endif /* !CONFIG_SMP */
 928         /* restore registers and return */
 929 2:      REST_4GPRS(3, r11)
 930         lwz     r10,_CCR(r11)
 931         REST_GPR(1, r11)
 932         mtcr    r10
 933         lwz     r10,_LINK(r11)
 934         mtlr    r10
 935         REST_GPR(10, r11)
 936         mtspr   SPRN_SRR1,r9
 937         mtspr   SPRN_SRR0,r12
 938         REST_GPR(9, r11)
 939         REST_GPR(12, r11)
 940         lwz     r11,GPR11(r11)
 941         rfi
 942
 943 /*
 944  * SPE unavailable trap from kernel - print a message, but let
 945  * the task use SPE in the kernel until it returns to user mode.
 946  */
 947 KernelSPE:
 948         lwz     r3,_MSR(r1)
 949         oris    r3,r3,MSR_SPE@h
 950         stw     r3,_MSR(r1)     /* enable use of SPE after return */
 951         lis     r3,87f@h
 952         ori     r3,r3,87f@l
 953         mr      r4,r2           /* current */
 954         lwz     r5,_NIP(r1)
 955         bl      printk
 956         b       ret_from_except
 957 87:     .string "SPE used in kernel  (task=%p, pc=%x)  \n"
 958         .align  4,0
 959
 960 #endif /* CONFIG_SPE */
 961
 962 /*
 963  * Global functions
 964  */
 965
 966 /*
 967  * extern void loadcam_entry(unsigned int index)
 968  *
 969  * Load TLBCAM[index] entry in to the L2 CAM MMU
 970  */
 971 _GLOBAL(loadcam_entry)
 972         lis     r4,TLBCAM@ha
 973         addi    r4,r4,TLBCAM@l
 974         mulli   r5,r3,20
 975         add     r3,r5,r4
 976         lwz     r4,0(r3)
 977         mtspr   SPRN_MAS0,r4
 978         lwz     r4,4(r3)
 979         mtspr   SPRN_MAS1,r4
 980         lwz     r4,8(r3)
 981         mtspr   SPRN_MAS2,r4
 982         lwz     r4,12(r3)
 983         mtspr   SPRN_MAS3,r4
 984         tlbwe
 985         isync
 986         blr
 987
 988 /*
 989  * extern void giveup_altivec(struct task_struct *prev)
 990  *
 991  * The e500 core does not have an AltiVec unit.
 992  */
 993 _GLOBAL(giveup_altivec)
 994         blr
 995
 996 #ifdef CONFIG_SPE
 997 /*
 998  * extern void giveup_spe(struct task_struct *prev)
 999  *
1000  */
1001 _GLOBAL(giveup_spe)
1002         mfmsr   r5
1003         oris    r5,r5,MSR_SPE@h
1004         mtmsr   r5                      /* enable use of SPE now */
1005         isync
1006         cmpi    0,r3,0
1007         beqlr-                          /* if no previous owner, done */
1008         addi    r3,r3,THREAD            /* want THREAD of task */
1009         lwz     r5,PT_REGS(r3)
1010         cmpi    0,r5,0
1011         SAVE_32EVRS(0, r4, r3)
1012         evxor   evr6, evr6, evr6        /* clear out evr6 */
1013         evmwumiaa evr6, evr6, evr6      /* evr6 <- ACC = 0 * 0 + ACC */
1014         li      r4,THREAD_ACC
1015         evstddx evr6, r4, r3            /* save off accumulator */
1016         mfspr   r6,SPRN_SPEFSCR
1017         stw     r6,THREAD_SPEFSCR(r3)   /* save spefscr register value */
1018         beq     1f
1019         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1020         lis     r3,MSR_SPE@h
1021         andc    r4,r4,r3                /* disable SPE for previous task */
1022         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1023 1:
1024 #ifndef CONFIG_SMP
1025         li      r5,0
1026         lis     r4,last_task_used_spe@ha
1027         stw     r5,last_task_used_spe@l(r4)
1028 #endif /* !CONFIG_SMP */
1029         blr
1030 #endif /* CONFIG_SPE */
1031
1032 /*
1033  * extern void giveup_fpu(struct task_struct *prev)
1034  *
1035  * Not all FSL Book-E cores have an FPU
1036  */
1037 #ifndef CONFIG_PPC_FPU
1038 _GLOBAL(giveup_fpu)
1039         blr
1040 #endif
1041
1042 /*
1043  * extern void abort(void)
1044  *
1045  * At present, this routine just applies a system reset.
1046  */
1047 _GLOBAL(abort)
1048         li      r13,0
1049         mtspr   SPRN_DBCR0,r13          /* disable all debug events */
1050         isync
1051         mfmsr   r13
1052         ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
1053         mtmsr   r13
1054         isync
1055         mfspr   r13,SPRN_DBCR0
1056         lis     r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1057         mtspr   SPRN_DBCR0,r13
1058         isync
1059
1060 _GLOBAL(set_context)
1061
1062 #ifdef CONFIG_BDI_SWITCH
1063         /* Context switch the PTE pointer for the Abatron BDI2000.
1064          * The PGDIR is the second parameter.
1065          */
1066         lis     r5, abatron_pteptrs@h
1067         ori     r5, r5, abatron_pteptrs@l
1068         stw     r4, 0x4(r5)
1069 #endif
1070         mtspr   SPRN_PID,r3
1071         isync                   /* Force context change */
1072         blr
1073
1074 /*
1075  * We put a few things here that have to be page-aligned. This stuff
1076  * goes at the beginning of the data segment, which is page-aligned.
1077  */
1078         .data
1079         .align  12
1080         .globl  sdata
1081 sdata:
1082         .globl  empty_zero_page
1083 empty_zero_page:
1084         .space  4096
1085         .globl  swapper_pg_dir
1086 swapper_pg_dir:
1087         .space  PGD_TABLE_SIZE
1088
1089 /*
1090  * Room for two PTE pointers, usually the kernel and current user pointers
1091  * to their respective root page table.
1092  */
1093 abatron_pteptrs:
1094         .space  8