arch/powerpc/kernel/head_fsl_booke.S

   1 /*
   2  * Kernel execution entry point code.
   3  *
   4  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   5  *      Initial PowerPC version.
   6  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *      Rewritten for PReP
   8  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   9  *      Low-level exception handers, MMU support, and rewrite.
  10  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  11  *      PowerPC 8xx modifications.
  12  *    Copyright (c) 1998-1999 TiVo, Inc.
  13  *      PowerPC 403GCX modifications.
  14  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  15  *      PowerPC 403GCX/405GP modifications.
  16  *    Copyright 2000 MontaVista Software Inc.
  17  *      PPC405 modifications
  18  *      PowerPC 403GCX/405GP modifications.
  19  *      Author: MontaVista Software, Inc.
  20  *              frank_rowand@mvista.com or source@mvista.com
  21  *              debbie_chu@mvista.com
  22  *    Copyright 2002-2004 MontaVista Software, Inc.
  23  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  24  *    Copyright 2004 Freescale Semiconductor, Inc
  25  *      PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
  26  *
  27  * This program is free software; you can redistribute  it and/or modify it
  28  * under  the terms of  the GNU General  Public License as published by the
  29  * Free Software Foundation;  either version 2 of the  License, or (at your
  30  * option) any later version.
  31  */
  32
  33 #include <linux/threads.h>
  34 #include <asm/processor.h>
  35 #include <asm/page.h>
  36 #include <asm/mmu.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/cputable.h>
  39 #include <asm/thread_info.h>
  40 #include <asm/ppc_asm.h>
  41 #include <asm/asm-offsets.h>
  42 #include "head_booke.h"
  43
  44 /* As with the other PowerPC ports, it is expected that when code
  45  * execution begins here, the following registers contain valid, yet
  46  * optional, information:
  47  *
  48  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  49  *   r4 - Starting address of the init RAM disk
  50  *   r5 - Ending address of the init RAM disk
  51  *   r6 - Start of kernel command line string (e.g. "mem=128")
  52  *   r7 - End of kernel command line string
  53  *
  54  */
  55         .section        .text.head, "ax"
  56 _ENTRY(_stext);
  57 _ENTRY(_start);
  58         /*
  59          * Reserve a word at a fixed location to store the address
  60          * of abatron_pteptrs
  61          */
  62         nop
  63 /*
  64  * Save parameters we are passed
  65  */
  66         mr      r31,r3
  67         mr      r30,r4
  68         mr      r29,r5
  69         mr      r28,r6
  70         mr      r27,r7
  71         li      r24,0           /* CPU number */
  72
  73 /* We try to not make any assumptions about how the boot loader
  74  * setup or used the TLBs.  We invalidate all mappings from the
  75  * boot loader and load a single entry in TLB1[0] to map the
  76  * first 64M of kernel memory.  Any boot info passed from the
  77  * bootloader needs to live in this first 64M.
  78  *
  79  * Requirement on bootloader:
  80  *  - The page we're executing in needs to reside in TLB1 and
  81  *    have IPROT=1.  If not an invalidate broadcast could
  82  *    evict the entry we're currently executing in.
  83  *
  84  *  r3 = Index of TLB1 were executing in
  85  *  r4 = Current MSR[IS]
  86  *  r5 = Index of TLB1 temp mapping
  87  *
  88  * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
  89  * if needed
  90  */
  91
  92 /* 1. Find the index of the entry we're executing in */
  93         bl      invstr                          /* Find our address */
  94 invstr: mflr    r6                              /* Make it accessible */
  95         mfmsr   r7
  96         rlwinm  r4,r7,27,31,31                  /* extract MSR[IS] */
  97         mfspr   r7, SPRN_PID0
  98         slwi    r7,r7,16
  99         or      r7,r7,r4
 100         mtspr   SPRN_MAS6,r7
 101         tlbsx   0,r6                            /* search MSR[IS], SPID=PID0 */
 102 #ifndef CONFIG_E200
 103         mfspr   r7,SPRN_MAS1
 104         andis.  r7,r7,MAS1_VALID@h
 105         bne     match_TLB
 106         mfspr   r7,SPRN_PID1
 107         slwi    r7,r7,16
 108         or      r7,r7,r4
 109         mtspr   SPRN_MAS6,r7
 110         tlbsx   0,r6                            /* search MSR[IS], SPID=PID1 */
 111         mfspr   r7,SPRN_MAS1
 112         andis.  r7,r7,MAS1_VALID@h
 113         bne     match_TLB
 114         mfspr   r7, SPRN_PID2
 115         slwi    r7,r7,16
 116         or      r7,r7,r4
 117         mtspr   SPRN_MAS6,r7
 118         tlbsx   0,r6                            /* Fall through, we had to match */
 119 #endif
 120 match_TLB:
 121         mfspr   r7,SPRN_MAS0
 122         rlwinm  r3,r7,16,20,31                  /* Extract MAS0(Entry) */
 123
 124         mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
 125         oris    r7,r7,MAS1_IPROT@h
 126         mtspr   SPRN_MAS1,r7
 127         tlbwe
 128
 129 /* 2. Invalidate all entries except the entry we're executing in */
 130         mfspr   r9,SPRN_TLB1CFG
 131         andi.   r9,r9,0xfff
 132         li      r6,0                            /* Set Entry counter to 0 */
 133 1:      lis     r7,0x1000                       /* Set MAS0(TLBSEL) = 1 */
 134         rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
 135         mtspr   SPRN_MAS0,r7
 136         tlbre
 137         mfspr   r7,SPRN_MAS1
 138         rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
 139         cmpw    r3,r6
 140         beq     skpinv                          /* Dont update the current execution TLB */
 141         mtspr   SPRN_MAS1,r7
 142         tlbwe
 143         isync
 144 skpinv: addi    r6,r6,1                         /* Increment */
 145         cmpw    r6,r9                           /* Are we done? */
 146         bne     1b                              /* If not, repeat */
 147
 148         /* Invalidate TLB0 */
 149         li      r6,0x04
 150         tlbivax 0,r6
 151 #ifdef CONFIG_SMP
 152         tlbsync
 153 #endif
 154         /* Invalidate TLB1 */
 155         li      r6,0x0c
 156         tlbivax 0,r6
 157 #ifdef CONFIG_SMP
 158         tlbsync
 159 #endif
 160         msync
 161
 162 /* 3. Setup a temp mapping and jump to it */
 163         andi.   r5, r3, 0x1     /* Find an entry not used and is non-zero */
 164         addi    r5, r5, 0x1
 165         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 166         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 167         mtspr   SPRN_MAS0,r7
 168         tlbre
 169
 170         /* Just modify the entry ID, EPN and RPN for the temp mapping */
 171         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 172         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 173         mtspr   SPRN_MAS0,r7
 174         xori    r6,r4,1         /* Setup TMP mapping in the other Address space */
 175         slwi    r6,r6,12
 176         oris    r6,r6,(MAS1_VALID|MAS1_IPROT)@h
 177         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 178         mtspr   SPRN_MAS1,r6
 179         mfspr   r6,SPRN_MAS2
 180         lis     r7,PHYSICAL_START@h
 181         rlwimi  r7,r6,0,20,31
 182         mtspr   SPRN_MAS2,r7
 183         mfspr   r6,SPRN_MAS3
 184         rlwimi  r7,r6,0,20,31
 185         mtspr   SPRN_MAS3,r7
 186         tlbwe
 187
 188         xori    r6,r4,1
 189         slwi    r6,r6,5         /* setup new context with other address space */
 190         bl      1f              /* Find our address */
 191 1:      mflr    r9
 192         rlwimi  r7,r9,0,20,31
 193         addi    r7,r7,24
 194         mtspr   SPRN_SRR0,r7
 195         mtspr   SPRN_SRR1,r6
 196         rfi
 197
 198 /* 4. Clear out PIDs & Search info */
 199         li      r6,0
 200         mtspr   SPRN_PID0,r6
 201 #ifndef CONFIG_E200
 202         mtspr   SPRN_PID1,r6
 203         mtspr   SPRN_PID2,r6
 204 #endif
 205         mtspr   SPRN_MAS6,r6
 206
 207 /* 5. Invalidate mapping we started in */
 208         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 209         rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
 210         mtspr   SPRN_MAS0,r7
 211         tlbre
 212         mfspr   r6,SPRN_MAS1
 213         rlwinm  r6,r6,0,2,0     /* clear IPROT */
 214         mtspr   SPRN_MAS1,r6
 215         tlbwe
 216         /* Invalidate TLB1 */
 217         li      r9,0x0c
 218         tlbivax 0,r9
 219 #ifdef CONFIG_SMP
 220         tlbsync
 221 #endif
 222         msync
 223
 224 /* 6. Setup KERNELBASE mapping in TLB1[0] */
 225         lis     r6,0x1000               /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
 226         mtspr   SPRN_MAS0,r6
 227         lis     r6,(MAS1_VALID|MAS1_IPROT)@h
 228         ori     r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
 229         mtspr   SPRN_MAS1,r6
 230         li      r7,0
 231         lis     r6,PAGE_OFFSET@h
 232         ori     r6,r6,PAGE_OFFSET@l
 233         rlwimi  r6,r7,0,20,31
 234         mtspr   SPRN_MAS2,r6
 235         li      r7,(MAS3_SX|MAS3_SW|MAS3_SR)
 236         mtspr   SPRN_MAS3,r7
 237         tlbwe
 238
 239 /* 7. Jump to KERNELBASE mapping */
 240         lis     r6,KERNELBASE@h
 241         ori     r6,r6,KERNELBASE@l
 242         rlwimi  r6,r7,0,20,31
 243         lis     r7,MSR_KERNEL@h
 244         ori     r7,r7,MSR_KERNEL@l
 245         bl      1f                      /* Find our address */
 246 1:      mflr    r9
 247         rlwimi  r6,r9,0,20,31
 248         addi    r6,r6,24
 249         mtspr   SPRN_SRR0,r6
 250         mtspr   SPRN_SRR1,r7
 251         rfi                             /* start execution out of TLB1[0] entry */
 252
 253 /* 8. Clear out the temp mapping */
 254         lis     r7,0x1000       /* Set MAS0(TLBSEL) = 1 */
 255         rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
 256         mtspr   SPRN_MAS0,r7
 257         tlbre
 258         mfspr   r8,SPRN_MAS1
 259         rlwinm  r8,r8,0,2,0     /* clear IPROT */
 260         mtspr   SPRN_MAS1,r8
 261         tlbwe
 262         /* Invalidate TLB1 */
 263         li      r9,0x0c
 264         tlbivax 0,r9
 265 #ifdef CONFIG_SMP
 266         tlbsync
 267 #endif
 268         msync
 269
 270         /* Establish the interrupt vector offsets */
 271         SET_IVOR(0,  CriticalInput);
 272         SET_IVOR(1,  MachineCheck);
 273         SET_IVOR(2,  DataStorage);
 274         SET_IVOR(3,  InstructionStorage);
 275         SET_IVOR(4,  ExternalInput);
 276         SET_IVOR(5,  Alignment);
 277         SET_IVOR(6,  Program);
 278         SET_IVOR(7,  FloatingPointUnavailable);
 279         SET_IVOR(8,  SystemCall);
 280         SET_IVOR(9,  AuxillaryProcessorUnavailable);
 281         SET_IVOR(10, Decrementer);
 282         SET_IVOR(11, FixedIntervalTimer);
 283         SET_IVOR(12, WatchdogTimer);
 284         SET_IVOR(13, DataTLBError);
 285         SET_IVOR(14, InstructionTLBError);
 286         SET_IVOR(15, Debug);
 287         SET_IVOR(32, SPEUnavailable);
 288         SET_IVOR(33, SPEFloatingPointData);
 289         SET_IVOR(34, SPEFloatingPointRound);
 290 #ifndef CONFIG_E200
 291         SET_IVOR(35, PerformanceMonitor);
 292 #endif
 293
 294         /* Establish the interrupt vector base */
 295         lis     r4,interrupt_base@h     /* IVPR only uses the high 16-bits */
 296         mtspr   SPRN_IVPR,r4
 297
 298         /* Setup the defaults for TLB entries */
 299         li      r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
 300 #ifdef CONFIG_E200
 301         oris    r2,r2,MAS4_TLBSELD(1)@h
 302 #endif
 303         mtspr   SPRN_MAS4, r2
 304
 305 #if 0
 306         /* Enable DOZE */
 307         mfspr   r2,SPRN_HID0
 308         oris    r2,r2,HID0_DOZE@h
 309         mtspr   SPRN_HID0, r2
 310 #endif
 311 #ifdef CONFIG_E200
 312         /* enable dedicated debug exception handling resources (Debug APU) */
 313         mfspr   r2,SPRN_HID0
 314         ori     r2,r2,HID0_DAPUEN@l
 315         mtspr   SPRN_HID0,r2
 316 #endif
 317
 318 #if !defined(CONFIG_BDI_SWITCH)
 319         /*
 320          * The Abatron BDI JTAG debugger does not tolerate others
 321          * mucking with the debug registers.
 322          */
 323         lis     r2,DBCR0_IDM@h
 324         mtspr   SPRN_DBCR0,r2
 325         isync
 326         /* clear any residual debug events */
 327         li      r2,-1
 328         mtspr   SPRN_DBSR,r2
 329 #endif
 330
 331         /*
 332          * This is where the main kernel code starts.
 333          */
 334
 335         /* ptr to current */
 336         lis     r2,init_task@h
 337         ori     r2,r2,init_task@l
 338
 339         /* ptr to current thread */
 340         addi    r4,r2,THREAD    /* init task's THREAD */
 341         mtspr   SPRN_SPRG3,r4
 342
 343         /* stack */
 344         lis     r1,init_thread_union@h
 345         ori     r1,r1,init_thread_union@l
 346         li      r0,0
 347         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 348
 349         bl      early_init
 350
 351         mfspr   r3,SPRN_TLB1CFG
 352         andi.   r3,r3,0xfff
 353         lis     r4,num_tlbcam_entries@ha
 354         stw     r3,num_tlbcam_entries@l(r4)
 355 /*
 356  * Decide what sort of machine this is and initialize the MMU.
 357  */
 358         mr      r3,r31
 359         mr      r4,r30
 360         mr      r5,r29
 361         mr      r6,r28
 362         mr      r7,r27
 363         bl      machine_init
 364         bl      MMU_init
 365
 366         /* Setup PTE pointers for the Abatron bdiGDB */
 367         lis     r6, swapper_pg_dir@h
 368         ori     r6, r6, swapper_pg_dir@l
 369         lis     r5, abatron_pteptrs@h
 370         ori     r5, r5, abatron_pteptrs@l
 371         lis     r4, KERNELBASE@h
 372         ori     r4, r4, KERNELBASE@l
 373         stw     r5, 0(r4)       /* Save abatron_pteptrs at a fixed location */
 374         stw     r6, 0(r5)
 375
 376         /* Let's move on */
 377         lis     r4,start_kernel@h
 378         ori     r4,r4,start_kernel@l
 379         lis     r3,MSR_KERNEL@h
 380         ori     r3,r3,MSR_KERNEL@l
 381         mtspr   SPRN_SRR0,r4
 382         mtspr   SPRN_SRR1,r3
 383         rfi                     /* change context and jump to start_kernel */
 384
 385 /* Macros to hide the PTE size differences
 386  *
 387  * FIND_PTE -- walks the page tables given EA & pgdir pointer
 388  *   r10 -- EA of fault
 389  *   r11 -- PGDIR pointer
 390  *   r12 -- free
 391  *   label 2: is the bailout case
 392  *
 393  * if we find the pte (fall through):
 394  *   r11 is low pte word
 395  *   r12 is pointer to the pte
 396  */
 397 #ifdef CONFIG_PTE_64BIT
 398 #define PTE_FLAGS_OFFSET        4
 399 #define FIND_PTE        \
 400         rlwinm  r12, r10, 13, 19, 29;   /* Compute pgdir/pmd offset */  \
 401         lwzx    r11, r12, r11;          /* Get pgd/pmd entry */         \
 402         rlwinm. r12, r11, 0, 0, 20;     /* Extract pt base address */   \
 403         beq     2f;                     /* Bail if no table */          \
 404         rlwimi  r12, r10, 23, 20, 28;   /* Compute pte address */       \
 405         lwz     r11, 4(r12);            /* Get pte entry */
 406 #else
 407 #define PTE_FLAGS_OFFSET        0
 408 #define FIND_PTE        \
 409         rlwimi  r11, r10, 12, 20, 29;   /* Create L1 (pgdir/pmd) address */     \
 410         lwz     r11, 0(r11);            /* Get L1 entry */                      \
 411         rlwinm. r12, r11, 0, 0, 19;     /* Extract L2 (pte) base address */     \
 412         beq     2f;                     /* Bail if no table */                  \
 413         rlwimi  r12, r10, 22, 20, 29;   /* Compute PTE address */               \
 414         lwz     r11, 0(r12);            /* Get Linux PTE */
 415 #endif
 416
 417 /*
 418  * Interrupt vector entry code
 419  *
 420  * The Book E MMUs are always on so we don't need to handle
 421  * interrupts in real mode as with previous PPC processors. In
 422  * this case we handle interrupts in the kernel virtual address
 423  * space.
 424  *
 425  * Interrupt vectors are dynamically placed relative to the
 426  * interrupt prefix as determined by the address of interrupt_base.
 427  * The interrupt vectors offsets are programmed using the labels
 428  * for each interrupt vector entry.
 429  *
 430  * Interrupt vectors must be aligned on a 16 byte boundary.
 431  * We align on a 32 byte cache line boundary for good measure.
 432  */
 433
 434 interrupt_base:
 435         /* Critical Input Interrupt */
 436         CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
 437
 438         /* Machine Check Interrupt */
 439 #ifdef CONFIG_E200
 440         /* no RFMCI, MCSRRs on E200 */
 441         CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 442 #else
 443         MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 444 #endif
 445
 446         /* Data Storage Interrupt */
 447         START_EXCEPTION(DataStorage)
 448         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 449         mtspr   SPRN_SPRG1, r11
 450         mtspr   SPRN_SPRG4W, r12
 451         mtspr   SPRN_SPRG5W, r13
 452         mfcr    r11
 453         mtspr   SPRN_SPRG7W, r11
 454
 455         /*
 456          * Check if it was a store fault, if not then bail
 457          * because a user tried to access a kernel or
 458          * read-protected page.  Otherwise, get the
 459          * offending address and handle it.
 460          */
 461         mfspr   r10, SPRN_ESR
 462         andis.  r10, r10, ESR_ST@h
 463         beq     2f
 464
 465         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 466
 467         /* If we are faulting a kernel address, we have to use the
 468          * kernel page tables.
 469          */
 470         lis     r11, PAGE_OFFSET@h
 471         cmplw   0, r10, r11
 472         bge     2f
 473
 474         /* Get the PGD for the current thread */
 475 3:
 476         mfspr   r11,SPRN_SPRG3
 477         lwz     r11,PGDIR(r11)
 478 4:
 479         FIND_PTE
 480
 481         /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
 482         andi.   r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
 483         cmpwi   0, r13, _PAGE_RW|_PAGE_USER
 484         bne     2f                      /* Bail if not */
 485
 486         /* Update 'changed'. */
 487         ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 488         stw     r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
 489
 490         /* MAS2 not updated as the entry does exist in the tlb, this
 491            fault taken to detect state transition (eg: COW -> DIRTY)
 492          */
 493         andi.   r11, r11, _PAGE_HWEXEC
 494         rlwimi  r11, r11, 31, 27, 27    /* SX <- _PAGE_HWEXEC */
 495         ori     r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
 496
 497         /* update search PID in MAS6, AS = 0 */
 498         mfspr   r12, SPRN_PID0
 499         slwi    r12, r12, 16
 500         mtspr   SPRN_MAS6, r12
 501
 502         /* find the TLB index that caused the fault.  It has to be here. */
 503         tlbsx   0, r10
 504
 505         /* only update the perm bits, assume the RPN is fine */
 506         mfspr   r12, SPRN_MAS3
 507         rlwimi  r12, r11, 0, 20, 31
 508         mtspr   SPRN_MAS3,r12
 509         tlbwe
 510
 511         /* Done...restore registers and get out of here.  */
 512         mfspr   r11, SPRN_SPRG7R
 513         mtcr    r11
 514         mfspr   r13, SPRN_SPRG5R
 515         mfspr   r12, SPRN_SPRG4R
 516         mfspr   r11, SPRN_SPRG1
 517         mfspr   r10, SPRN_SPRG0
 518         rfi                     /* Force context change */
 519
 520 2:
 521         /*
 522          * The bailout.  Restore registers to pre-exception conditions
 523          * and call the heavyweights to help us out.
 524          */
 525         mfspr   r11, SPRN_SPRG7R
 526         mtcr    r11
 527         mfspr   r13, SPRN_SPRG5R
 528         mfspr   r12, SPRN_SPRG4R
 529         mfspr   r11, SPRN_SPRG1
 530         mfspr   r10, SPRN_SPRG0
 531         b       data_access
 532
 533         /* Instruction Storage Interrupt */
 534         INSTRUCTION_STORAGE_EXCEPTION
 535
 536         /* External Input Interrupt */
 537         EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
 538
 539         /* Alignment Interrupt */
 540         ALIGNMENT_EXCEPTION
 541
 542         /* Program Interrupt */
 543         PROGRAM_EXCEPTION
 544
 545         /* Floating Point Unavailable Interrupt */
 546 #ifdef CONFIG_PPC_FPU
 547         FP_UNAVAILABLE_EXCEPTION
 548 #else
 549 #ifdef CONFIG_E200
 550         /* E200 treats 'normal' floating point instructions as FP Unavail exception */
 551         EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
 552 #else
 553         EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
 554 #endif
 555 #endif
 556
 557         /* System Call Interrupt */
 558         START_EXCEPTION(SystemCall)
 559         NORMAL_EXCEPTION_PROLOG
 560         EXC_XFER_EE_LITE(0x0c00, DoSyscall)
 561
 562         /* Auxillary Processor Unavailable Interrupt */
 563         EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
 564
 565         /* Decrementer Interrupt */
 566         DECREMENTER_EXCEPTION
 567
 568         /* Fixed Internal Timer Interrupt */
 569         /* TODO: Add FIT support */
 570         EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
 571
 572         /* Watchdog Timer Interrupt */
 573 #ifdef CONFIG_BOOKE_WDT
 574         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
 575 #else
 576         CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
 577 #endif
 578
 579         /* Data TLB Error Interrupt */
 580         START_EXCEPTION(DataTLBError)
 581         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 582         mtspr   SPRN_SPRG1, r11
 583         mtspr   SPRN_SPRG4W, r12
 584         mtspr   SPRN_SPRG5W, r13
 585         mfcr    r11
 586         mtspr   SPRN_SPRG7W, r11
 587         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 588
 589         /* If we are faulting a kernel address, we have to use the
 590          * kernel page tables.
 591          */
 592         lis     r11, PAGE_OFFSET@h
 593         cmplw   5, r10, r11
 594         blt     5, 3f
 595         lis     r11, swapper_pg_dir@h
 596         ori     r11, r11, swapper_pg_dir@l
 597
 598         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 599         rlwinm  r12,r12,0,16,1
 600         mtspr   SPRN_MAS1,r12
 601
 602         b       4f
 603
 604         /* Get the PGD for the current thread */
 605 3:
 606         mfspr   r11,SPRN_SPRG3
 607         lwz     r11,PGDIR(r11)
 608
 609 4:
 610         FIND_PTE
 611         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 612         beq     2f                      /* Bail if not present */
 613
 614 #ifdef CONFIG_PTE_64BIT
 615         lwz     r13, 0(r12)
 616 #endif
 617         ori     r11, r11, _PAGE_ACCESSED
 618         stw     r11, PTE_FLAGS_OFFSET(r12)
 619
 620          /* Jump to common tlb load */
 621         b       finish_tlb_load
 622 2:
 623         /* The bailout.  Restore registers to pre-exception conditions
 624          * and call the heavyweights to help us out.
 625          */
 626         mfspr   r11, SPRN_SPRG7R
 627         mtcr    r11
 628         mfspr   r13, SPRN_SPRG5R
 629         mfspr   r12, SPRN_SPRG4R
 630         mfspr   r11, SPRN_SPRG1
 631         mfspr   r10, SPRN_SPRG0
 632         b       data_access
 633
 634         /* Instruction TLB Error Interrupt */
 635         /*
 636          * Nearly the same as above, except we get our
 637          * information from different registers and bailout
 638          * to a different point.
 639          */
 640         START_EXCEPTION(InstructionTLBError)
 641         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 642         mtspr   SPRN_SPRG1, r11
 643         mtspr   SPRN_SPRG4W, r12
 644         mtspr   SPRN_SPRG5W, r13
 645         mfcr    r11
 646         mtspr   SPRN_SPRG7W, r11
 647         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 648
 649         /* If we are faulting a kernel address, we have to use the
 650          * kernel page tables.
 651          */
 652         lis     r11, PAGE_OFFSET@h
 653         cmplw   5, r10, r11
 654         blt     5, 3f
 655         lis     r11, swapper_pg_dir@h
 656         ori     r11, r11, swapper_pg_dir@l
 657
 658         mfspr   r12,SPRN_MAS1           /* Set TID to 0 */
 659         rlwinm  r12,r12,0,16,1
 660         mtspr   SPRN_MAS1,r12
 661
 662         b       4f
 663
 664         /* Get the PGD for the current thread */
 665 3:
 666         mfspr   r11,SPRN_SPRG3
 667         lwz     r11,PGDIR(r11)
 668
 669 4:
 670         FIND_PTE
 671         andi.   r13, r11, _PAGE_PRESENT /* Is the page present? */
 672         beq     2f                      /* Bail if not present */
 673
 674 #ifdef CONFIG_PTE_64BIT
 675         lwz     r13, 0(r12)
 676 #endif
 677         ori     r11, r11, _PAGE_ACCESSED
 678         stw     r11, PTE_FLAGS_OFFSET(r12)
 679
 680         /* Jump to common TLB load point */
 681         b       finish_tlb_load
 682
 683 2:
 684         /* The bailout.  Restore registers to pre-exception conditions
 685          * and call the heavyweights to help us out.
 686          */
 687         mfspr   r11, SPRN_SPRG7R
 688         mtcr    r11
 689         mfspr   r13, SPRN_SPRG5R
 690         mfspr   r12, SPRN_SPRG4R
 691         mfspr   r11, SPRN_SPRG1
 692         mfspr   r10, SPRN_SPRG0
 693         b       InstructionStorage
 694
 695 #ifdef CONFIG_SPE
 696         /* SPE Unavailable */
 697         START_EXCEPTION(SPEUnavailable)
 698         NORMAL_EXCEPTION_PROLOG
 699         bne     load_up_spe
 700         addi    r3,r1,STACK_FRAME_OVERHEAD
 701         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 702 #else
 703         EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
 704 #endif /* CONFIG_SPE */
 705
 706         /* SPE Floating Point Data */
 707 #ifdef CONFIG_SPE
 708         EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
 709 #else
 710         EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
 711 #endif /* CONFIG_SPE */
 712
 713         /* SPE Floating Point Round */
 714         EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
 715
 716         /* Performance Monitor */
 717         EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
 718
 719
 720         /* Debug Interrupt */
 721         DEBUG_EXCEPTION
 722
 723 /*
 724  * Local functions
 725  */
 726
 727         /*
 728          * Data TLB exceptions will bail out to this point
 729          * if they can't resolve the lightweight TLB fault.
 730          */
 731 data_access:
 732         NORMAL_EXCEPTION_PROLOG
 733         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 734         stw     r5,_ESR(r11)
 735         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 736         andis.  r10,r5,(ESR_ILK|ESR_DLK)@h
 737         bne     1f
 738         EXC_XFER_EE_LITE(0x0300, handle_page_fault)
 739 1:
 740         addi    r3,r1,STACK_FRAME_OVERHEAD
 741         EXC_XFER_EE_LITE(0x0300, CacheLockingException)
 742
 743 /*
 744
 745  * Both the instruction and data TLB miss get to this
 746  * point to load the TLB.
 747  *      r10 - EA of fault
 748  *      r11 - TLB (info from Linux PTE)
 749  *      r12, r13 - available to use
 750  *      CR5 - results of addr >= PAGE_OFFSET
 751  *      MAS0, MAS1 - loaded with proper value when we get here
 752  *      MAS2, MAS3 - will need additional info from Linux PTE
 753  *      Upon exit, we reload everything and RFI.
 754  */
 755 finish_tlb_load:
 756         /*
 757          * We set execute, because we don't have the granularity to
 758          * properly set this at the page level (Linux problem).
 759          * Many of these bits are software only.  Bits we don't set
 760          * here we (properly should) assume have the appropriate value.
 761          */
 762
 763         mfspr   r12, SPRN_MAS2
 764 #ifdef CONFIG_PTE_64BIT
 765         rlwimi  r12, r11, 26, 24, 31    /* extract ...WIMGE from pte */
 766 #else
 767         rlwimi  r12, r11, 26, 27, 31    /* extract WIMGE from pte */
 768 #endif
 769         mtspr   SPRN_MAS2, r12
 770
 771         bge     5, 1f
 772
 773         /* is user addr */
 774         andi.   r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
 775         andi.   r10, r11, _PAGE_USER    /* Test for _PAGE_USER */
 776         srwi    r10, r12, 1
 777         or      r12, r12, r10   /* Copy user perms into supervisor */
 778         iseleq  r12, 0, r12
 779         b       2f
 780
 781         /* is kernel addr */
 782 1:      rlwinm  r12, r11, 31, 29, 29    /* Extract _PAGE_HWWRITE into SW */
 783         ori     r12, r12, (MAS3_SX | MAS3_SR)
 784
 785 #ifdef CONFIG_PTE_64BIT
 786 2:      rlwimi  r12, r13, 24, 0, 7      /* grab RPN[32:39] */
 787         rlwimi  r12, r11, 24, 8, 19     /* grab RPN[40:51] */
 788         mtspr   SPRN_MAS3, r12
 789 BEGIN_FTR_SECTION
 790         srwi    r10, r13, 8             /* grab RPN[8:31] */
 791         mtspr   SPRN_MAS7, r10
 792 END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
 793 #else
 794 2:      rlwimi  r11, r12, 0, 20, 31     /* Extract RPN from PTE and merge with perms */
 795         mtspr   SPRN_MAS3, r11
 796 #endif
 797 #ifdef CONFIG_E200
 798         /* Round robin TLB1 entries assignment */
 799         mfspr   r12, SPRN_MAS0
 800
 801         /* Extract TLB1CFG(NENTRY) */
 802         mfspr   r11, SPRN_TLB1CFG
 803         andi.   r11, r11, 0xfff
 804
 805         /* Extract MAS0(NV) */
 806         andi.   r13, r12, 0xfff
 807         addi    r13, r13, 1
 808         cmpw    0, r13, r11
 809         addi    r12, r12, 1
 810
 811         /* check if we need to wrap */
 812         blt     7f
 813
 814         /* wrap back to first free tlbcam entry */
 815         lis     r13, tlbcam_index@ha
 816         lwz     r13, tlbcam_index@l(r13)
 817         rlwimi  r12, r13, 0, 20, 31
 818 7:
 819         mtspr   SPRN_MAS0,r12
 820 #endif /* CONFIG_E200 */
 821
 822         tlbwe
 823
 824         /* Done...restore registers and get out of here.  */
 825         mfspr   r11, SPRN_SPRG7R
 826         mtcr    r11
 827         mfspr   r13, SPRN_SPRG5R
 828         mfspr   r12, SPRN_SPRG4R
 829         mfspr   r11, SPRN_SPRG1
 830         mfspr   r10, SPRN_SPRG0
 831         rfi                                     /* Force context change */
 832
 833 #ifdef CONFIG_SPE
 834 /* Note that the SPE support is closely modeled after the AltiVec
 835  * support.  Changes to one are likely to be applicable to the
 836  * other!  */
 837 load_up_spe:
 838 /*
 839  * Disable SPE for the task which had SPE previously,
 840  * and save its SPE registers in its thread_struct.
 841  * Enables SPE for use in the kernel on return.
 842  * On SMP we know the SPE units are free, since we give it up every
 843  * switch.  -- Kumar
 844  */
 845         mfmsr   r5
 846         oris    r5,r5,MSR_SPE@h
 847         mtmsr   r5                      /* enable use of SPE now */
 848         isync
 849 /*
 850  * For SMP, we don't do lazy SPE switching because it just gets too
 851  * horrendously complex, especially when a task switches from one CPU
 852  * to another.  Instead we call giveup_spe in switch_to.
 853  */
 854 #ifndef CONFIG_SMP
 855         lis     r3,last_task_used_spe@ha
 856         lwz     r4,last_task_used_spe@l(r3)
 857         cmpi    0,r4,0
 858         beq     1f
 859         addi    r4,r4,THREAD    /* want THREAD of last_task_used_spe */
 860         SAVE_32EVRS(0,r10,r4)
 861         evxor   evr10, evr10, evr10     /* clear out evr10 */
 862         evmwumiaa evr10, evr10, evr10   /* evr10 <- ACC = 0 * 0 + ACC */
 863         li      r5,THREAD_ACC
 864         evstddx evr10, r4, r5           /* save off accumulator */
 865         lwz     r5,PT_REGS(r4)
 866         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 867         lis     r10,MSR_SPE@h
 868         andc    r4,r4,r10       /* disable SPE for previous task */
 869         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 870 1:
 871 #endif /* !CONFIG_SMP */
 872         /* enable use of SPE after return */
 873         oris    r9,r9,MSR_SPE@h
 874         mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
 875         li      r4,1
 876         li      r10,THREAD_ACC
 877         stw     r4,THREAD_USED_SPE(r5)
 878         evlddx  evr4,r10,r5
 879         evmra   evr4,evr4
 880         REST_32EVRS(0,r10,r5)
 881 #ifndef CONFIG_SMP
 882         subi    r4,r5,THREAD
 883         stw     r4,last_task_used_spe@l(r3)
 884 #endif /* !CONFIG_SMP */
 885         /* restore registers and return */
 886 2:      REST_4GPRS(3, r11)
 887         lwz     r10,_CCR(r11)
 888         REST_GPR(1, r11)
 889         mtcr    r10
 890         lwz     r10,_LINK(r11)
 891         mtlr    r10
 892         REST_GPR(10, r11)
 893         mtspr   SPRN_SRR1,r9
 894         mtspr   SPRN_SRR0,r12
 895         REST_GPR(9, r11)
 896         REST_GPR(12, r11)
 897         lwz     r11,GPR11(r11)
 898         rfi
 899
 900 /*
 901  * SPE unavailable trap from kernel - print a message, but let
 902  * the task use SPE in the kernel until it returns to user mode.
 903  */
 904 KernelSPE:
 905         lwz     r3,_MSR(r1)
 906         oris    r3,r3,MSR_SPE@h
 907         stw     r3,_MSR(r1)     /* enable use of SPE after return */
 908         lis     r3,87f@h
 909         ori     r3,r3,87f@l
 910         mr      r4,r2           /* current */
 911         lwz     r5,_NIP(r1)
 912         bl      printk
 913         b       ret_from_except
 914 87:     .string "SPE used in kernel  (task=%p, pc=%x)  \n"
 915         .align  4,0
 916
 917 #endif /* CONFIG_SPE */
 918
 919 /*
 920  * Global functions
 921  */
 922
 923 /*
 924  * extern void loadcam_entry(unsigned int index)
 925  *
 926  * Load TLBCAM[index] entry in to the L2 CAM MMU
 927  */
 928 _GLOBAL(loadcam_entry)
 929         lis     r4,TLBCAM@ha
 930         addi    r4,r4,TLBCAM@l
 931         mulli   r5,r3,20
 932         add     r3,r5,r4
 933         lwz     r4,0(r3)
 934         mtspr   SPRN_MAS0,r4
 935         lwz     r4,4(r3)
 936         mtspr   SPRN_MAS1,r4
 937         lwz     r4,8(r3)
 938         mtspr   SPRN_MAS2,r4
 939         lwz     r4,12(r3)
 940         mtspr   SPRN_MAS3,r4
 941         tlbwe
 942         isync
 943         blr
 944
 945 /*
 946  * extern void giveup_altivec(struct task_struct *prev)
 947  *
 948  * The e500 core does not have an AltiVec unit.
 949  */
 950 _GLOBAL(giveup_altivec)
 951         blr
 952
 953 #ifdef CONFIG_SPE
 954 /*
 955  * extern void giveup_spe(struct task_struct *prev)
 956  *
 957  */
 958 _GLOBAL(giveup_spe)
 959         mfmsr   r5
 960         oris    r5,r5,MSR_SPE@h
 961         mtmsr   r5                      /* enable use of SPE now */
 962         isync
 963         cmpi    0,r3,0
 964         beqlr-                          /* if no previous owner, done */
 965         addi    r3,r3,THREAD            /* want THREAD of task */
 966         lwz     r5,PT_REGS(r3)
 967         cmpi    0,r5,0
 968         SAVE_32EVRS(0, r4, r3)
 969         evxor   evr6, evr6, evr6        /* clear out evr6 */
 970         evmwumiaa evr6, evr6, evr6      /* evr6 <- ACC = 0 * 0 + ACC */
 971         li      r4,THREAD_ACC
 972         evstddx evr6, r4, r3            /* save off accumulator */
 973         mfspr   r6,SPRN_SPEFSCR
 974         stw     r6,THREAD_SPEFSCR(r3)   /* save spefscr register value */
 975         beq     1f
 976         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 977         lis     r3,MSR_SPE@h
 978         andc    r4,r4,r3                /* disable SPE for previous task */
 979         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 980 1:
 981 #ifndef CONFIG_SMP
 982         li      r5,0
 983         lis     r4,last_task_used_spe@ha
 984         stw     r5,last_task_used_spe@l(r4)
 985 #endif /* !CONFIG_SMP */
 986         blr
 987 #endif /* CONFIG_SPE */
 988
 989 /*
 990  * extern void giveup_fpu(struct task_struct *prev)
 991  *
 992  * Not all FSL Book-E cores have an FPU
 993  */
 994 #ifndef CONFIG_PPC_FPU
 995 _GLOBAL(giveup_fpu)
 996         blr
 997 #endif
 998
 999 /*
1000  * extern void abort(void)
1001  *
1002  * At present, this routine just applies a system reset.
1003  */
1004 _GLOBAL(abort)
1005         li      r13,0
1006         mtspr   SPRN_DBCR0,r13          /* disable all debug events */
1007         isync
1008         mfmsr   r13
1009         ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
1010         mtmsr   r13
1011         isync
1012         mfspr   r13,SPRN_DBCR0
1013         lis     r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1014         mtspr   SPRN_DBCR0,r13
1015         isync
1016
1017 _GLOBAL(set_context)
1018
1019 #ifdef CONFIG_BDI_SWITCH
1020         /* Context switch the PTE pointer for the Abatron BDI2000.
1021          * The PGDIR is the second parameter.
1022          */
1023         lis     r5, abatron_pteptrs@h
1024         ori     r5, r5, abatron_pteptrs@l
1025         stw     r4, 0x4(r5)
1026 #endif
1027         mtspr   SPRN_PID,r3
1028         isync                   /* Force context change */
1029         blr
1030
1031 /*
1032  * We put a few things here that have to be page-aligned. This stuff
1033  * goes at the beginning of the data segment, which is page-aligned.
1034  */
1035         .data
1036         .align  12
1037         .globl  sdata
1038 sdata:
1039         .globl  empty_zero_page
1040 empty_zero_page:
1041         .space  4096
1042         .globl  swapper_pg_dir
1043 swapper_pg_dir:
1044         .space  PGD_TABLE_SIZE
1045
1046 /* Reserved 4k for the critical exception stack & 4k for the machine
1047  * check stack per CPU for kernel mode exceptions */
1048         .section .bss
1049         .align 12
1050 exception_stack_bottom:
1051         .space  BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
1052         .globl  exception_stack_top
1053 exception_stack_top:
1054
1055 /*
1056  * Room for two PTE pointers, usually the kernel and current user pointers
1057  * to their respective root page table.
1058  */
1059 abatron_pteptrs:
1060         .space  8