arch/powerpc/kernel/misc_32.S

   1 /*
   2  * This file contains miscellaneous low-level functions.
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
   6  * and Paul Mackerras.
   7  *
   8  * kexec bits:
   9  * Copyright (C) 2002-2003 Eric Biederman  <ebiederm@xmission.com>
  10  * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version
  15  * 2 of the License, or (at your option) any later version.
  16  *
  17  */
  18
  19 #include <linux/sys.h>
  20 #include <asm/unistd.h>
  21 #include <asm/errno.h>
  22 #include <asm/reg.h>
  23 #include <asm/page.h>
  24 #include <asm/cache.h>
  25 #include <asm/cputable.h>
  26 #include <asm/mmu.h>
  27 #include <asm/ppc_asm.h>
  28 #include <asm/thread_info.h>
  29 #include <asm/asm-offsets.h>
  30 #include <asm/processor.h>
  31 #include <asm/kexec.h>
  32
  33         .text
  34
  35 /*
  36  * This returns the high 64 bits of the product of two 64-bit numbers.
  37  */
  38 _GLOBAL(mulhdu)
  39         cmpwi   r6,0
  40         cmpwi   cr1,r3,0
  41         mr      r10,r4
  42         mulhwu  r4,r4,r5
  43         beq     1f
  44         mulhwu  r0,r10,r6
  45         mullw   r7,r10,r5
  46         addc    r7,r0,r7
  47         addze   r4,r4
  48 1:      beqlr   cr1             /* all done if high part of A is 0 */
  49         mr      r10,r3
  50         mullw   r9,r3,r5
  51         mulhwu  r3,r3,r5
  52         beq     2f
  53         mullw   r0,r10,r6
  54         mulhwu  r8,r10,r6
  55         addc    r7,r0,r7
  56         adde    r4,r4,r8
  57         addze   r3,r3
  58 2:      addc    r4,r4,r9
  59         addze   r3,r3
  60         blr
  61
  62 /*
  63  * sub_reloc_offset(x) returns x - reloc_offset().
  64  */
  65 _GLOBAL(sub_reloc_offset)
  66         mflr    r0
  67         bl      1f
  68 1:      mflr    r5
  69         lis     r4,1b@ha
  70         addi    r4,r4,1b@l
  71         subf    r5,r4,r5
  72         subf    r3,r5,r3
  73         mtlr    r0
  74         blr
  75
  76 /*
  77  * reloc_got2 runs through the .got2 section adding an offset
  78  * to each entry.
  79  */
  80 _GLOBAL(reloc_got2)
  81         mflr    r11
  82         lis     r7,__got2_start@ha
  83         addi    r7,r7,__got2_start@l
  84         lis     r8,__got2_end@ha
  85         addi    r8,r8,__got2_end@l
  86         subf    r8,r7,r8
  87         srwi.   r8,r8,2
  88         beqlr
  89         mtctr   r8
  90         bl      1f
  91 1:      mflr    r0
  92         lis     r4,1b@ha
  93         addi    r4,r4,1b@l
  94         subf    r0,r4,r0
  95         add     r7,r0,r7
  96 2:      lwz     r0,0(r7)
  97         add     r0,r0,r3
  98         stw     r0,0(r7)
  99         addi    r7,r7,4
 100         bdnz    2b
 101         mtlr    r11
 102         blr
 103
 104 /*
 105  * call_setup_cpu - call the setup_cpu function for this cpu
 106  * r3 = data offset, r24 = cpu number
 107  *
 108  * Setup function is called with:
 109  *   r3 = data offset
 110  *   r4 = ptr to CPU spec (relocated)
 111  */
 112 _GLOBAL(call_setup_cpu)
 113         addis   r4,r3,cur_cpu_spec@ha
 114         addi    r4,r4,cur_cpu_spec@l
 115         lwz     r4,0(r4)
 116         add     r4,r4,r3
 117         lwz     r5,CPU_SPEC_SETUP(r4)
 118         cmpwi   0,r5,0
 119         add     r5,r5,r3
 120         beqlr
 121         mtctr   r5
 122         bctr
 123
 124 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
 125
 126 /* This gets called by via-pmu.c to switch the PLL selection
 127  * on 750fx CPU. This function should really be moved to some
 128  * other place (as most of the cpufreq code in via-pmu
 129  */
 130 _GLOBAL(low_choose_750fx_pll)
 131         /* Clear MSR:EE */
 132         mfmsr   r7
 133         rlwinm  r0,r7,0,17,15
 134         mtmsr   r0
 135
 136         /* If switching to PLL1, disable HID0:BTIC */
 137         cmplwi  cr0,r3,0
 138         beq     1f
 139         mfspr   r5,SPRN_HID0
 140         rlwinm  r5,r5,0,27,25
 141         sync
 142         mtspr   SPRN_HID0,r5
 143         isync
 144         sync
 145
 146 1:
 147         /* Calc new HID1 value */
 148         mfspr   r4,SPRN_HID1    /* Build a HID1:PS bit from parameter */
 149         rlwinm  r5,r3,16,15,15  /* Clear out HID1:PS from value read */
 150         rlwinm  r4,r4,0,16,14   /* Could have I used rlwimi here ? */
 151         or      r4,r4,r5
 152         mtspr   SPRN_HID1,r4
 153
 154         /* Store new HID1 image */
 155         rlwinm  r6,r1,0,0,18
 156         lwz     r6,TI_CPU(r6)
 157         slwi    r6,r6,2
 158         addis   r6,r6,nap_save_hid1@ha
 159         stw     r4,nap_save_hid1@l(r6)
 160
 161         /* If switching to PLL0, enable HID0:BTIC */
 162         cmplwi  cr0,r3,0
 163         bne     1f
 164         mfspr   r5,SPRN_HID0
 165         ori     r5,r5,HID0_BTIC
 166         sync
 167         mtspr   SPRN_HID0,r5
 168         isync
 169         sync
 170
 171 1:
 172         /* Return */
 173         mtmsr   r7
 174         blr
 175
 176 _GLOBAL(low_choose_7447a_dfs)
 177         /* Clear MSR:EE */
 178         mfmsr   r7
 179         rlwinm  r0,r7,0,17,15
 180         mtmsr   r0
 181
 182         /* Calc new HID1 value */
 183         mfspr   r4,SPRN_HID1
 184         insrwi  r4,r3,1,9       /* insert parameter into bit 9 */
 185         sync
 186         mtspr   SPRN_HID1,r4
 187         sync
 188         isync
 189
 190         /* Return */
 191         mtmsr   r7
 192         blr
 193
 194 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
 195
 196 /*
 197  * complement mask on the msr then "or" some values on.
 198  *     _nmask_and_or_msr(nmask, value_to_or)
 199  */
 200 _GLOBAL(_nmask_and_or_msr)
 201         mfmsr   r0              /* Get current msr */
 202         andc    r0,r0,r3        /* And off the bits set in r3 (first parm) */
 203         or      r0,r0,r4        /* Or on the bits in r4 (second parm) */
 204         SYNC                    /* Some chip revs have problems here... */
 205         mtmsr   r0              /* Update machine state */
 206         isync
 207         blr                     /* Done */
 208
 209 #ifdef CONFIG_40x
 210
 211 /*
 212  * Do an IO access in real mode
 213  */
 214 _GLOBAL(real_readb)
 215         mfmsr   r7
 216         ori     r0,r7,MSR_DR
 217         xori    r0,r0,MSR_DR
 218         sync
 219         mtmsr   r0
 220         sync
 221         isync
 222         lbz     r3,0(r3)
 223         sync
 224         mtmsr   r7
 225         sync
 226         isync
 227         blr
 228
 229         /*
 230  * Do an IO access in real mode
 231  */
 232 _GLOBAL(real_writeb)
 233         mfmsr   r7
 234         ori     r0,r7,MSR_DR
 235         xori    r0,r0,MSR_DR
 236         sync
 237         mtmsr   r0
 238         sync
 239         isync
 240         stb     r3,0(r4)
 241         sync
 242         mtmsr   r7
 243         sync
 244         isync
 245         blr
 246
 247 #endif /* CONFIG_40x */
 248
 249 /*
 250  * Flush MMU TLB
 251  */
 252 _GLOBAL(_tlbia)
 253 #if defined(CONFIG_40x)
 254         sync                    /* Flush to memory before changing mapping */
 255         tlbia
 256         isync                   /* Flush shadow TLB */
 257 #elif defined(CONFIG_44x)
 258         li      r3,0
 259         sync
 260
 261         /* Load high watermark */
 262         lis     r4,tlb_44x_hwater@ha
 263         lwz     r5,tlb_44x_hwater@l(r4)
 264
 265 1:      tlbwe   r3,r3,PPC44x_TLB_PAGEID
 266         addi    r3,r3,1
 267         cmpw    0,r3,r5
 268         ble     1b
 269
 270         isync
 271 #elif defined(CONFIG_FSL_BOOKE)
 272         /* Invalidate all entries in TLB0 */
 273         li      r3, 0x04
 274         tlbivax 0,3
 275         /* Invalidate all entries in TLB1 */
 276         li      r3, 0x0c
 277         tlbivax 0,3
 278         msync
 279 #ifdef CONFIG_SMP
 280         tlbsync
 281 #endif /* CONFIG_SMP */
 282 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
 283 #if defined(CONFIG_SMP)
 284         rlwinm  r8,r1,0,0,18
 285         lwz     r8,TI_CPU(r8)
 286         oris    r8,r8,10
 287         mfmsr   r10
 288         SYNC
 289         rlwinm  r0,r10,0,17,15          /* clear bit 16 (MSR_EE) */
 290         rlwinm  r0,r0,0,28,26           /* clear DR */
 291         mtmsr   r0
 292         SYNC_601
 293         isync
 294         lis     r9,mmu_hash_lock@h
 295         ori     r9,r9,mmu_hash_lock@l
 296         tophys(r9,r9)
 297 10:     lwarx   r7,0,r9
 298         cmpwi   0,r7,0
 299         bne-    10b
 300         stwcx.  r8,0,r9
 301         bne-    10b
 302         sync
 303         tlbia
 304         sync
 305         TLBSYNC
 306         li      r0,0
 307         stw     r0,0(r9)                /* clear mmu_hash_lock */
 308         mtmsr   r10
 309         SYNC_601
 310         isync
 311 #else /* CONFIG_SMP */
 312         sync
 313         tlbia
 314         sync
 315 #endif /* CONFIG_SMP */
 316 #endif /* ! defined(CONFIG_40x) */
 317         blr
 318
 319 /*
 320  * Flush MMU TLB for a particular address
 321  */
 322 _GLOBAL(_tlbie)
 323 #if defined(CONFIG_40x)
 324         /* We run the search with interrupts disabled because we have to change
 325          * the PID and I don't want to preempt when that happens.
 326          */
 327         mfmsr   r5
 328         mfspr   r6,SPRN_PID
 329         wrteei  0
 330         mtspr   SPRN_PID,r4
 331         tlbsx.  r3, 0, r3
 332         mtspr   SPRN_PID,r6
 333         wrtee   r5
 334         bne     10f
 335         sync
 336         /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
 337          * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
 338          * the TLB entry. */
 339         tlbwe   r3, r3, TLB_TAG
 340         isync
 341 10:
 342
 343 #elif defined(CONFIG_44x)
 344         mfspr   r5,SPRN_MMUCR
 345         rlwimi  r5,r4,0,24,31                   /* Set TID */
 346
 347         /* We have to run the search with interrupts disabled, even critical
 348          * and debug interrupts (in fact the only critical exceptions we have
 349          * are debug and machine check).  Otherwise  an interrupt which causes
 350          * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
 351         mfmsr   r4
 352         lis     r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
 353         addi    r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
 354         andc    r6,r4,r6
 355         mtmsr   r6
 356         mtspr   SPRN_MMUCR,r5
 357         tlbsx.  r3, 0, r3
 358         mtmsr   r4
 359         bne     10f
 360         sync
 361         /* There are only 64 TLB entries, so r3 < 64,
 362          * which means bit 22, is clear.  Since 22 is
 363          * the V bit in the TLB_PAGEID, loading this
 364          * value will invalidate the TLB entry.
 365          */
 366         tlbwe   r3, r3, PPC44x_TLB_PAGEID
 367         isync
 368 10:
 369 #elif defined(CONFIG_FSL_BOOKE)
 370         rlwinm  r4, r3, 0, 0, 19
 371         ori     r5, r4, 0x08    /* TLBSEL = 1 */
 372         tlbivax 0, r4
 373         tlbivax 0, r5
 374         msync
 375 #if defined(CONFIG_SMP)
 376         tlbsync
 377 #endif /* CONFIG_SMP */
 378 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
 379 #if defined(CONFIG_SMP)
 380         rlwinm  r8,r1,0,0,18
 381         lwz     r8,TI_CPU(r8)
 382         oris    r8,r8,11
 383         mfmsr   r10
 384         SYNC
 385         rlwinm  r0,r10,0,17,15          /* clear bit 16 (MSR_EE) */
 386         rlwinm  r0,r0,0,28,26           /* clear DR */
 387         mtmsr   r0
 388         SYNC_601
 389         isync
 390         lis     r9,mmu_hash_lock@h
 391         ori     r9,r9,mmu_hash_lock@l
 392         tophys(r9,r9)
 393 10:     lwarx   r7,0,r9
 394         cmpwi   0,r7,0
 395         bne-    10b
 396         stwcx.  r8,0,r9
 397         bne-    10b
 398         eieio
 399         tlbie   r3
 400         sync
 401         TLBSYNC
 402         li      r0,0
 403         stw     r0,0(r9)                /* clear mmu_hash_lock */
 404         mtmsr   r10
 405         SYNC_601
 406         isync
 407 #else /* CONFIG_SMP */
 408         tlbie   r3
 409         sync
 410 #endif /* CONFIG_SMP */
 411 #endif /* ! CONFIG_40x */
 412         blr
 413
 414 /*
 415  * Flush instruction cache.
 416  * This is a no-op on the 601.
 417  */
 418 _GLOBAL(flush_instruction_cache)
 419 #if defined(CONFIG_8xx)
 420         isync
 421         lis     r5, IDC_INVALL@h
 422         mtspr   SPRN_IC_CST, r5
 423 #elif defined(CONFIG_4xx)
 424 #ifdef CONFIG_403GCX
 425         li      r3, 512
 426         mtctr   r3
 427         lis     r4, KERNELBASE@h
 428 1:      iccci   0, r4
 429         addi    r4, r4, 16
 430         bdnz    1b
 431 #else
 432         lis     r3, KERNELBASE@h
 433         iccci   0,r3
 434 #endif
 435 #elif CONFIG_FSL_BOOKE
 436 BEGIN_FTR_SECTION
 437         mfspr   r3,SPRN_L1CSR0
 438         ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC
 439         /* msync; isync recommended here */
 440         mtspr   SPRN_L1CSR0,r3
 441         isync
 442         blr
 443 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
 444         mfspr   r3,SPRN_L1CSR1
 445         ori     r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
 446         mtspr   SPRN_L1CSR1,r3
 447 #else
 448         mfspr   r3,SPRN_PVR
 449         rlwinm  r3,r3,16,16,31
 450         cmpwi   0,r3,1
 451         beqlr                   /* for 601, do nothing */
 452         /* 603/604 processor - use invalidate-all bit in HID0 */
 453         mfspr   r3,SPRN_HID0
 454         ori     r3,r3,HID0_ICFI
 455         mtspr   SPRN_HID0,r3
 456 #endif /* CONFIG_8xx/4xx */
 457         isync
 458         blr
 459
 460 /*
 461  * Write any modified data cache blocks out to memory
 462  * and invalidate the corresponding instruction cache blocks.
 463  * This is a no-op on the 601.
 464  *
 465  * flush_icache_range(unsigned long start, unsigned long stop)
 466  */
 467 _GLOBAL(__flush_icache_range)
 468 BEGIN_FTR_SECTION
 469         blr                             /* for 601, do nothing */
 470 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 471         li      r5,L1_CACHE_BYTES-1
 472         andc    r3,r3,r5
 473         subf    r4,r3,r4
 474         add     r4,r4,r5
 475         srwi.   r4,r4,L1_CACHE_SHIFT
 476         beqlr
 477         mtctr   r4
 478         mr      r6,r3
 479 1:      dcbst   0,r3
 480         addi    r3,r3,L1_CACHE_BYTES
 481         bdnz    1b
 482         sync                            /* wait for dcbst's to get to ram */
 483         mtctr   r4
 484 2:      icbi    0,r6
 485         addi    r6,r6,L1_CACHE_BYTES
 486         bdnz    2b
 487         sync                            /* additional sync needed on g4 */
 488         isync
 489         blr
 490 /*
 491  * Write any modified data cache blocks out to memory.
 492  * Does not invalidate the corresponding cache lines (especially for
 493  * any corresponding instruction cache).
 494  *
 495  * clean_dcache_range(unsigned long start, unsigned long stop)
 496  */
 497 _GLOBAL(clean_dcache_range)
 498         li      r5,L1_CACHE_BYTES-1
 499         andc    r3,r3,r5
 500         subf    r4,r3,r4
 501         add     r4,r4,r5
 502         srwi.   r4,r4,L1_CACHE_SHIFT
 503         beqlr
 504         mtctr   r4
 505
 506 1:      dcbst   0,r3
 507         addi    r3,r3,L1_CACHE_BYTES
 508         bdnz    1b
 509         sync                            /* wait for dcbst's to get to ram */
 510         blr
 511
 512 /*
 513  * Write any modified data cache blocks out to memory and invalidate them.
 514  * Does not invalidate the corresponding instruction cache blocks.
 515  *
 516  * flush_dcache_range(unsigned long start, unsigned long stop)
 517  */
 518 _GLOBAL(flush_dcache_range)
 519         li      r5,L1_CACHE_BYTES-1
 520         andc    r3,r3,r5
 521         subf    r4,r3,r4
 522         add     r4,r4,r5
 523         srwi.   r4,r4,L1_CACHE_SHIFT
 524         beqlr
 525         mtctr   r4
 526
 527 1:      dcbf    0,r3
 528         addi    r3,r3,L1_CACHE_BYTES
 529         bdnz    1b
 530         sync                            /* wait for dcbst's to get to ram */
 531         blr
 532
 533 /*
 534  * Like above, but invalidate the D-cache.  This is used by the 8xx
 535  * to invalidate the cache so the PPC core doesn't get stale data
 536  * from the CPM (no cache snooping here :-).
 537  *
 538  * invalidate_dcache_range(unsigned long start, unsigned long stop)
 539  */
 540 _GLOBAL(invalidate_dcache_range)
 541         li      r5,L1_CACHE_BYTES-1
 542         andc    r3,r3,r5
 543         subf    r4,r3,r4
 544         add     r4,r4,r5
 545         srwi.   r4,r4,L1_CACHE_SHIFT
 546         beqlr
 547         mtctr   r4
 548
 549 1:      dcbi    0,r3
 550         addi    r3,r3,L1_CACHE_BYTES
 551         bdnz    1b
 552         sync                            /* wait for dcbi's to get to ram */
 553         blr
 554
 555 /*
 556  * Flush a particular page from the data cache to RAM.
 557  * Note: this is necessary because the instruction cache does *not*
 558  * snoop from the data cache.
 559  * This is a no-op on the 601 which has a unified cache.
 560  *
 561  *      void __flush_dcache_icache(void *page)
 562  */
 563 _GLOBAL(__flush_dcache_icache)
 564 BEGIN_FTR_SECTION
 565         blr
 566 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 567         rlwinm  r3,r3,0,0,19                    /* Get page base address */
 568         li      r4,4096/L1_CACHE_BYTES  /* Number of lines in a page */
 569         mtctr   r4
 570         mr      r6,r3
 571 0:      dcbst   0,r3                            /* Write line to ram */
 572         addi    r3,r3,L1_CACHE_BYTES
 573         bdnz    0b
 574         sync
 575 #ifndef CONFIG_44x
 576         /* We don't flush the icache on 44x. Those have a virtual icache
 577          * and we don't have access to the virtual address here (it's
 578          * not the page vaddr but where it's mapped in user space). The
 579          * flushing of the icache on these is handled elsewhere, when
 580          * a change in the address space occurs, before returning to
 581          * user space
 582          */
 583         mtctr   r4
 584 1:      icbi    0,r6
 585         addi    r6,r6,L1_CACHE_BYTES
 586         bdnz    1b
 587         sync
 588         isync
 589 #endif /* CONFIG_44x */
 590         blr
 591
 592 /*
 593  * Flush a particular page from the data cache to RAM, identified
 594  * by its physical address.  We turn off the MMU so we can just use
 595  * the physical address (this may be a highmem page without a kernel
 596  * mapping).
 597  *
 598  *      void __flush_dcache_icache_phys(unsigned long physaddr)
 599  */
 600 _GLOBAL(__flush_dcache_icache_phys)
 601 BEGIN_FTR_SECTION
 602         blr                                     /* for 601, do nothing */
 603 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 604         mfmsr   r10
 605         rlwinm  r0,r10,0,28,26                  /* clear DR */
 606         mtmsr   r0
 607         isync
 608         rlwinm  r3,r3,0,0,19                    /* Get page base address */
 609         li      r4,4096/L1_CACHE_BYTES  /* Number of lines in a page */
 610         mtctr   r4
 611         mr      r6,r3
 612 0:      dcbst   0,r3                            /* Write line to ram */
 613         addi    r3,r3,L1_CACHE_BYTES
 614         bdnz    0b
 615         sync
 616         mtctr   r4
 617 1:      icbi    0,r6
 618         addi    r6,r6,L1_CACHE_BYTES
 619         bdnz    1b
 620         sync
 621         mtmsr   r10                             /* restore DR */
 622         isync
 623         blr
 624
 625 /*
 626  * Clear pages using the dcbz instruction, which doesn't cause any
 627  * memory traffic (except to write out any cache lines which get
 628  * displaced).  This only works on cacheable memory.
 629  *
 630  * void clear_pages(void *page, int order) ;
 631  */
 632 _GLOBAL(clear_pages)
 633         li      r0,4096/L1_CACHE_BYTES
 634         slw     r0,r0,r4
 635         mtctr   r0
 636 #ifdef CONFIG_8xx
 637         li      r4, 0
 638 1:      stw     r4, 0(r3)
 639         stw     r4, 4(r3)
 640         stw     r4, 8(r3)
 641         stw     r4, 12(r3)
 642 #else
 643 1:      dcbz    0,r3
 644 #endif
 645         addi    r3,r3,L1_CACHE_BYTES
 646         bdnz    1b
 647         blr
 648
 649 /*
 650  * Copy a whole page.  We use the dcbz instruction on the destination
 651  * to reduce memory traffic (it eliminates the unnecessary reads of
 652  * the destination into cache).  This requires that the destination
 653  * is cacheable.
 654  */
 655 #define COPY_16_BYTES           \
 656         lwz     r6,4(r4);       \
 657         lwz     r7,8(r4);       \
 658         lwz     r8,12(r4);      \
 659         lwzu    r9,16(r4);      \
 660         stw     r6,4(r3);       \
 661         stw     r7,8(r3);       \
 662         stw     r8,12(r3);      \
 663         stwu    r9,16(r3)
 664
 665 _GLOBAL(copy_page)
 666         addi    r3,r3,-4
 667         addi    r4,r4,-4
 668
 669 #ifdef CONFIG_8xx
 670         /* don't use prefetch on 8xx */
 671         li      r0,4096/L1_CACHE_BYTES
 672         mtctr   r0
 673 1:      COPY_16_BYTES
 674         bdnz    1b
 675         blr
 676
 677 #else   /* not 8xx, we can prefetch */
 678         li      r5,4
 679
 680 #if MAX_COPY_PREFETCH > 1
 681         li      r0,MAX_COPY_PREFETCH
 682         li      r11,4
 683         mtctr   r0
 684 11:     dcbt    r11,r4
 685         addi    r11,r11,L1_CACHE_BYTES
 686         bdnz    11b
 687 #else /* MAX_COPY_PREFETCH == 1 */
 688         dcbt    r5,r4
 689         li      r11,L1_CACHE_BYTES+4
 690 #endif /* MAX_COPY_PREFETCH */
 691         li      r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
 692         crclr   4*cr0+eq
 693 2:
 694         mtctr   r0
 695 1:
 696         dcbt    r11,r4
 697         dcbz    r5,r3
 698         COPY_16_BYTES
 699 #if L1_CACHE_BYTES >= 32
 700         COPY_16_BYTES
 701 #if L1_CACHE_BYTES >= 64
 702         COPY_16_BYTES
 703         COPY_16_BYTES
 704 #if L1_CACHE_BYTES >= 128
 705         COPY_16_BYTES
 706         COPY_16_BYTES
 707         COPY_16_BYTES
 708         COPY_16_BYTES
 709 #endif
 710 #endif
 711 #endif
 712         bdnz    1b
 713         beqlr
 714         crnot   4*cr0+eq,4*cr0+eq
 715         li      r0,MAX_COPY_PREFETCH
 716         li      r11,4
 717         b       2b
 718 #endif  /* CONFIG_8xx */
 719
 720 /*
 721  * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
 722  * void atomic_set_mask(atomic_t mask, atomic_t *addr);
 723  */
 724 _GLOBAL(atomic_clear_mask)
 725 10:     lwarx   r5,0,r4
 726         andc    r5,r5,r3
 727         PPC405_ERR77(0,r4)
 728         stwcx.  r5,0,r4
 729         bne-    10b
 730         blr
 731 _GLOBAL(atomic_set_mask)
 732 10:     lwarx   r5,0,r4
 733         or      r5,r5,r3
 734         PPC405_ERR77(0,r4)
 735         stwcx.  r5,0,r4
 736         bne-    10b
 737         blr
 738
 739 /*
 740  * Extended precision shifts.
 741  *
 742  * Updated to be valid for shift counts from 0 to 63 inclusive.
 743  * -- Gabriel
 744  *
 745  * R3/R4 has 64 bit value
 746  * R5    has shift count
 747  * result in R3/R4
 748  *
 749  *  ashrdi3: arithmetic right shift (sign propagation)
 750  *  lshrdi3: logical right shift
 751  *  ashldi3: left shift
 752  */
 753 _GLOBAL(__ashrdi3)
 754         subfic  r6,r5,32
 755         srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
 756         addi    r7,r5,32        # could be xori, or addi with -32
 757         slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
 758         rlwinm  r8,r7,0,32      # t3 = (count < 32) ? 32 : 0
 759         sraw    r7,r3,r7        # t2 = MSW >> (count-32)
 760         or      r4,r4,r6        # LSW |= t1
 761         slw     r7,r7,r8        # t2 = (count < 32) ? 0 : t2
 762         sraw    r3,r3,r5        # MSW = MSW >> count
 763         or      r4,r4,r7        # LSW |= t2
 764         blr
 765
 766 _GLOBAL(__ashldi3)
 767         subfic  r6,r5,32
 768         slw     r3,r3,r5        # MSW = count > 31 ? 0 : MSW << count
 769         addi    r7,r5,32        # could be xori, or addi with -32
 770         srw     r6,r4,r6        # t1 = count > 31 ? 0 : LSW >> (32-count)
 771         slw     r7,r4,r7        # t2 = count < 32 ? 0 : LSW << (count-32)
 772         or      r3,r3,r6        # MSW |= t1
 773         slw     r4,r4,r5        # LSW = LSW << count
 774         or      r3,r3,r7        # MSW |= t2
 775         blr
 776
 777 _GLOBAL(__lshrdi3)
 778         subfic  r6,r5,32
 779         srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
 780         addi    r7,r5,32        # could be xori, or addi with -32
 781         slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
 782         srw     r7,r3,r7        # t2 = count < 32 ? 0 : MSW >> (count-32)
 783         or      r4,r4,r6        # LSW |= t1
 784         srw     r3,r3,r5        # MSW = MSW >> count
 785         or      r4,r4,r7        # LSW |= t2
 786         blr
 787
 788 _GLOBAL(abs)
 789         srawi   r4,r3,31
 790         xor     r3,r3,r4
 791         sub     r3,r3,r4
 792         blr
 793
 794 /*
 795  * Create a kernel thread
 796  *   kernel_thread(fn, arg, flags)
 797  */
 798 _GLOBAL(kernel_thread)
 799         stwu    r1,-16(r1)
 800         stw     r30,8(r1)
 801         stw     r31,12(r1)
 802         mr      r30,r3          /* function */
 803         mr      r31,r4          /* argument */
 804         ori     r3,r5,CLONE_VM  /* flags */
 805         oris    r3,r3,CLONE_UNTRACED>>16
 806         li      r4,0            /* new sp (unused) */
 807         li      r0,__NR_clone
 808         sc
 809         cmpwi   0,r3,0          /* parent or child? */
 810         bne     1f              /* return if parent */
 811         li      r0,0            /* make top-level stack frame */
 812         stwu    r0,-16(r1)
 813         mtlr    r30             /* fn addr in lr */
 814         mr      r3,r31          /* load arg and call fn */
 815         PPC440EP_ERR42
 816         blrl
 817         li      r0,__NR_exit    /* exit if function returns */
 818         li      r3,0
 819         sc
 820 1:      lwz     r30,8(r1)
 821         lwz     r31,12(r1)
 822         addi    r1,r1,16
 823         blr
 824
 825 /*
 826  * This routine is just here to keep GCC happy - sigh...
 827  */
 828 _GLOBAL(__main)
 829         blr
 830
 831 #ifdef CONFIG_KEXEC
 832         /*
 833          * Must be relocatable PIC code callable as a C function.
 834          */
 835         .globl relocate_new_kernel
 836 relocate_new_kernel:
 837         /* r3 = page_list   */
 838         /* r4 = reboot_code_buffer */
 839         /* r5 = start_address      */
 840
 841         li      r0, 0
 842
 843         /*
 844          * Set Machine Status Register to a known status,
 845          * switch the MMU off and jump to 1: in a single step.
 846          */
 847
 848         mr      r8, r0
 849         ori     r8, r8, MSR_RI|MSR_ME
 850         mtspr   SPRN_SRR1, r8
 851         addi    r8, r4, 1f - relocate_new_kernel
 852         mtspr   SPRN_SRR0, r8
 853         sync
 854         rfi
 855
 856 1:
 857         /* from this point address translation is turned off */
 858         /* and interrupts are disabled */
 859
 860         /* set a new stack at the bottom of our page... */
 861         /* (not really needed now) */
 862         addi    r1, r4, KEXEC_CONTROL_CODE_SIZE - 8 /* for LR Save+Back Chain */
 863         stw     r0, 0(r1)
 864
 865         /* Do the copies */
 866         li      r6, 0 /* checksum */
 867         mr      r0, r3
 868         b       1f
 869
 870 0:      /* top, read another word for the indirection page */
 871         lwzu    r0, 4(r3)
 872
 873 1:
 874         /* is it a destination page? (r8) */
 875         rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
 876         beq     2f
 877
 878         rlwinm  r8, r0, 0, 0, 19 /* clear kexec flags, page align */
 879         b       0b
 880
 881 2:      /* is it an indirection page? (r3) */
 882         rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
 883         beq     2f
 884
 885         rlwinm  r3, r0, 0, 0, 19 /* clear kexec flags, page align */
 886         subi    r3, r3, 4
 887         b       0b
 888
 889 2:      /* are we done? */
 890         rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
 891         beq     2f
 892         b       3f
 893
 894 2:      /* is it a source page? (r9) */
 895         rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
 896         beq     0b
 897
 898         rlwinm  r9, r0, 0, 0, 19 /* clear kexec flags, page align */
 899
 900         li      r7, PAGE_SIZE / 4
 901         mtctr   r7
 902         subi    r9, r9, 4
 903         subi    r8, r8, 4
 904 9:
 905         lwzu    r0, 4(r9)  /* do the copy */
 906         xor     r6, r6, r0
 907         stwu    r0, 4(r8)
 908         dcbst   0, r8
 909         sync
 910         icbi    0, r8
 911         bdnz    9b
 912
 913         addi    r9, r9, 4
 914         addi    r8, r8, 4
 915         b       0b
 916
 917 3:
 918
 919         /* To be certain of avoiding problems with self-modifying code
 920          * execute a serializing instruction here.
 921          */
 922         isync
 923         sync
 924
 925         /* jump to the entry point, usually the setup routine */
 926         mtlr    r5
 927         blrl
 928
 929 1:      b       1b
 930
 931 relocate_new_kernel_end:
 932
 933         .globl relocate_new_kernel_size
 934 relocate_new_kernel_size:
 935         .long relocate_new_kernel_end - relocate_new_kernel
 936 #endif