arch/powerpc/kernel/misc_32.S

   1 /*
   2  * This file contains miscellaneous low-level functions.
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
   6  * and Paul Mackerras.
   7  *
   8  * kexec bits:
   9  * Copyright (C) 2002-2003 Eric Biederman  <ebiederm@xmission.com>
  10  * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
  11  * PPC44x port. Copyright (C) 2011,  IBM Corporation
  12  *              Author: Suzuki Poulose <suzuki@in.ibm.com>
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version
  17  * 2 of the License, or (at your option) any later version.
  18  *
  19  */
  20
  21 #include <linux/sys.h>
  22 #include <asm/unistd.h>
  23 #include <asm/errno.h>
  24 #include <asm/reg.h>
  25 #include <asm/page.h>
  26 #include <asm/cache.h>
  27 #include <asm/cputable.h>
  28 #include <asm/mmu.h>
  29 #include <asm/ppc_asm.h>
  30 #include <asm/thread_info.h>
  31 #include <asm/asm-offsets.h>
  32 #include <asm/processor.h>
  33 #include <asm/kexec.h>
  34 #include <asm/bug.h>
  35 #include <asm/ptrace.h>
  36
  37         .text
  38
  39 /*
  40  * We store the saved ksp_limit in the unused part
  41  * of the STACK_FRAME_OVERHEAD
  42  */
  43 _GLOBAL(call_do_softirq)
  44         mflr    r0
  45         stw     r0,4(r1)
  46         lwz     r10,THREAD+KSP_LIMIT(r2)
  47         addi    r11,r3,THREAD_INFO_GAP
  48         stwu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
  49         mr      r1,r3
  50         stw     r10,8(r1)
  51         stw     r11,THREAD+KSP_LIMIT(r2)
  52         bl      __do_softirq
  53         lwz     r10,8(r1)
  54         lwz     r1,0(r1)
  55         lwz     r0,4(r1)
  56         stw     r10,THREAD+KSP_LIMIT(r2)
  57         mtlr    r0
  58         blr
  59
  60 _GLOBAL(call_do_irq)
  61         mflr    r0
  62         stw     r0,4(r1)
  63         lwz     r10,THREAD+KSP_LIMIT(r2)
  64         addi    r11,r3,THREAD_INFO_GAP
  65         stwu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
  66         mr      r1,r4
  67         stw     r10,8(r1)
  68         stw     r11,THREAD+KSP_LIMIT(r2)
  69         bl      __do_irq
  70         lwz     r10,8(r1)
  71         lwz     r1,0(r1)
  72         lwz     r0,4(r1)
  73         stw     r10,THREAD+KSP_LIMIT(r2)
  74         mtlr    r0
  75         blr
  76
  77 /*
  78  * This returns the high 64 bits of the product of two 64-bit numbers.
  79  */
  80 _GLOBAL(mulhdu)
  81         cmpwi   r6,0
  82         cmpwi   cr1,r3,0
  83         mr      r10,r4
  84         mulhwu  r4,r4,r5
  85         beq     1f
  86         mulhwu  r0,r10,r6
  87         mullw   r7,r10,r5
  88         addc    r7,r0,r7
  89         addze   r4,r4
  90 1:      beqlr   cr1             /* all done if high part of A is 0 */
  91         mr      r10,r3
  92         mullw   r9,r3,r5
  93         mulhwu  r3,r3,r5
  94         beq     2f
  95         mullw   r0,r10,r6
  96         mulhwu  r8,r10,r6
  97         addc    r7,r0,r7
  98         adde    r4,r4,r8
  99         addze   r3,r3
 100 2:      addc    r4,r4,r9
 101         addze   r3,r3
 102         blr
 103
 104 /*
 105  * sub_reloc_offset(x) returns x - reloc_offset().
 106  */
 107 _GLOBAL(sub_reloc_offset)
 108         mflr    r0
 109         bl      1f
 110 1:      mflr    r5
 111         lis     r4,1b@ha
 112         addi    r4,r4,1b@l
 113         subf    r5,r4,r5
 114         subf    r3,r5,r3
 115         mtlr    r0
 116         blr
 117
 118 /*
 119  * reloc_got2 runs through the .got2 section adding an offset
 120  * to each entry.
 121  */
 122 _GLOBAL(reloc_got2)
 123         mflr    r11
 124         lis     r7,__got2_start@ha
 125         addi    r7,r7,__got2_start@l
 126         lis     r8,__got2_end@ha
 127         addi    r8,r8,__got2_end@l
 128         subf    r8,r7,r8
 129         srwi.   r8,r8,2
 130         beqlr
 131         mtctr   r8
 132         bl      1f
 133 1:      mflr    r0
 134         lis     r4,1b@ha
 135         addi    r4,r4,1b@l
 136         subf    r0,r4,r0
 137         add     r7,r0,r7
 138 2:      lwz     r0,0(r7)
 139         add     r0,r0,r3
 140         stw     r0,0(r7)
 141         addi    r7,r7,4
 142         bdnz    2b
 143         mtlr    r11
 144         blr
 145
 146 /*
 147  * call_setup_cpu - call the setup_cpu function for this cpu
 148  * r3 = data offset, r24 = cpu number
 149  *
 150  * Setup function is called with:
 151  *   r3 = data offset
 152  *   r4 = ptr to CPU spec (relocated)
 153  */
 154 _GLOBAL(call_setup_cpu)
 155         addis   r4,r3,cur_cpu_spec@ha
 156         addi    r4,r4,cur_cpu_spec@l
 157         lwz     r4,0(r4)
 158         add     r4,r4,r3
 159         lwz     r5,CPU_SPEC_SETUP(r4)
 160         cmpwi   0,r5,0
 161         add     r5,r5,r3
 162         beqlr
 163         mtctr   r5
 164         bctr
 165
 166 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
 167
 168 /* This gets called by via-pmu.c to switch the PLL selection
 169  * on 750fx CPU. This function should really be moved to some
 170  * other place (as most of the cpufreq code in via-pmu
 171  */
 172 _GLOBAL(low_choose_750fx_pll)
 173         /* Clear MSR:EE */
 174         mfmsr   r7
 175         rlwinm  r0,r7,0,17,15
 176         mtmsr   r0
 177
 178         /* If switching to PLL1, disable HID0:BTIC */
 179         cmplwi  cr0,r3,0
 180         beq     1f
 181         mfspr   r5,SPRN_HID0
 182         rlwinm  r5,r5,0,27,25
 183         sync
 184         mtspr   SPRN_HID0,r5
 185         isync
 186         sync
 187
 188 1:
 189         /* Calc new HID1 value */
 190         mfspr   r4,SPRN_HID1    /* Build a HID1:PS bit from parameter */
 191         rlwinm  r5,r3,16,15,15  /* Clear out HID1:PS from value read */
 192         rlwinm  r4,r4,0,16,14   /* Could have I used rlwimi here ? */
 193         or      r4,r4,r5
 194         mtspr   SPRN_HID1,r4
 195
 196         /* Store new HID1 image */
 197         CURRENT_THREAD_INFO(r6, r1)
 198         lwz     r6,TI_CPU(r6)
 199         slwi    r6,r6,2
 200         addis   r6,r6,nap_save_hid1@ha
 201         stw     r4,nap_save_hid1@l(r6)
 202
 203         /* If switching to PLL0, enable HID0:BTIC */
 204         cmplwi  cr0,r3,0
 205         bne     1f
 206         mfspr   r5,SPRN_HID0
 207         ori     r5,r5,HID0_BTIC
 208         sync
 209         mtspr   SPRN_HID0,r5
 210         isync
 211         sync
 212
 213 1:
 214         /* Return */
 215         mtmsr   r7
 216         blr
 217
 218 _GLOBAL(low_choose_7447a_dfs)
 219         /* Clear MSR:EE */
 220         mfmsr   r7
 221         rlwinm  r0,r7,0,17,15
 222         mtmsr   r0
 223
 224         /* Calc new HID1 value */
 225         mfspr   r4,SPRN_HID1
 226         insrwi  r4,r3,1,9       /* insert parameter into bit 9 */
 227         sync
 228         mtspr   SPRN_HID1,r4
 229         sync
 230         isync
 231
 232         /* Return */
 233         mtmsr   r7
 234         blr
 235
 236 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
 237
 238 /*
 239  * complement mask on the msr then "or" some values on.
 240  *     _nmask_and_or_msr(nmask, value_to_or)
 241  */
 242 _GLOBAL(_nmask_and_or_msr)
 243         mfmsr   r0              /* Get current msr */
 244         andc    r0,r0,r3        /* And off the bits set in r3 (first parm) */
 245         or      r0,r0,r4        /* Or on the bits in r4 (second parm) */
 246         SYNC                    /* Some chip revs have problems here... */
 247         mtmsr   r0              /* Update machine state */
 248         isync
 249         blr                     /* Done */
 250
 251 #ifdef CONFIG_40x
 252
 253 /*
 254  * Do an IO access in real mode
 255  */
 256 _GLOBAL(real_readb)
 257         mfmsr   r7
 258         ori     r0,r7,MSR_DR
 259         xori    r0,r0,MSR_DR
 260         sync
 261         mtmsr   r0
 262         sync
 263         isync
 264         lbz     r3,0(r3)
 265         sync
 266         mtmsr   r7
 267         sync
 268         isync
 269         blr
 270
 271         /*
 272  * Do an IO access in real mode
 273  */
 274 _GLOBAL(real_writeb)
 275         mfmsr   r7
 276         ori     r0,r7,MSR_DR
 277         xori    r0,r0,MSR_DR
 278         sync
 279         mtmsr   r0
 280         sync
 281         isync
 282         stb     r3,0(r4)
 283         sync
 284         mtmsr   r7
 285         sync
 286         isync
 287         blr
 288
 289 #endif /* CONFIG_40x */
 290
 291
 292 /*
 293  * Flush instruction cache.
 294  * This is a no-op on the 601.
 295  */
 296 _GLOBAL(flush_instruction_cache)
 297 #if defined(CONFIG_8xx)
 298         isync
 299         lis     r5, IDC_INVALL@h
 300         mtspr   SPRN_IC_CST, r5
 301 #elif defined(CONFIG_4xx)
 302 #ifdef CONFIG_403GCX
 303         li      r3, 512
 304         mtctr   r3
 305         lis     r4, KERNELBASE@h
 306 1:      iccci   0, r4
 307         addi    r4, r4, 16
 308         bdnz    1b
 309 #else
 310         lis     r3, KERNELBASE@h
 311         iccci   0,r3
 312 #endif
 313 #elif CONFIG_FSL_BOOKE
 314 BEGIN_FTR_SECTION
 315         mfspr   r3,SPRN_L1CSR0
 316         ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC
 317         /* msync; isync recommended here */
 318         mtspr   SPRN_L1CSR0,r3
 319         isync
 320         blr
 321 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
 322         mfspr   r3,SPRN_L1CSR1
 323         ori     r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
 324         mtspr   SPRN_L1CSR1,r3
 325 #else
 326         mfspr   r3,SPRN_PVR
 327         rlwinm  r3,r3,16,16,31
 328         cmpwi   0,r3,1
 329         beqlr                   /* for 601, do nothing */
 330         /* 603/604 processor - use invalidate-all bit in HID0 */
 331         mfspr   r3,SPRN_HID0
 332         ori     r3,r3,HID0_ICFI
 333         mtspr   SPRN_HID0,r3
 334 #endif /* CONFIG_8xx/4xx */
 335         isync
 336         blr
 337
 338 /*
 339  * Write any modified data cache blocks out to memory
 340  * and invalidate the corresponding instruction cache blocks.
 341  * This is a no-op on the 601.
 342  *
 343  * flush_icache_range(unsigned long start, unsigned long stop)
 344  */
 345 _KPROBE(flush_icache_range)
 346 BEGIN_FTR_SECTION
 347         isync
 348         blr                             /* for 601, do nothing */
 349 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 350         li      r5,L1_CACHE_BYTES-1
 351         andc    r3,r3,r5
 352         subf    r4,r3,r4
 353         add     r4,r4,r5
 354         srwi.   r4,r4,L1_CACHE_SHIFT
 355         beqlr
 356         mtctr   r4
 357         mr      r6,r3
 358 1:      dcbst   0,r3
 359         addi    r3,r3,L1_CACHE_BYTES
 360         bdnz    1b
 361         sync                            /* wait for dcbst's to get to ram */
 362 #ifndef CONFIG_44x
 363         mtctr   r4
 364 2:      icbi    0,r6
 365         addi    r6,r6,L1_CACHE_BYTES
 366         bdnz    2b
 367 #else
 368         /* Flash invalidate on 44x because we are passed kmapped addresses and
 369            this doesn't work for userspace pages due to the virtually tagged
 370            icache.  Sigh. */
 371         iccci   0, r0
 372 #endif
 373         sync                            /* additional sync needed on g4 */
 374         isync
 375         blr
 376 /*
 377  * Write any modified data cache blocks out to memory.
 378  * Does not invalidate the corresponding cache lines (especially for
 379  * any corresponding instruction cache).
 380  *
 381  * clean_dcache_range(unsigned long start, unsigned long stop)
 382  */
 383 _GLOBAL(clean_dcache_range)
 384         li      r5,L1_CACHE_BYTES-1
 385         andc    r3,r3,r5
 386         subf    r4,r3,r4
 387         add     r4,r4,r5
 388         srwi.   r4,r4,L1_CACHE_SHIFT
 389         beqlr
 390         mtctr   r4
 391
 392 1:      dcbst   0,r3
 393         addi    r3,r3,L1_CACHE_BYTES
 394         bdnz    1b
 395         sync                            /* wait for dcbst's to get to ram */
 396         blr
 397
 398 /*
 399  * Write any modified data cache blocks out to memory and invalidate them.
 400  * Does not invalidate the corresponding instruction cache blocks.
 401  *
 402  * flush_dcache_range(unsigned long start, unsigned long stop)
 403  */
 404 _GLOBAL(flush_dcache_range)
 405         li      r5,L1_CACHE_BYTES-1
 406         andc    r3,r3,r5
 407         subf    r4,r3,r4
 408         add     r4,r4,r5
 409         srwi.   r4,r4,L1_CACHE_SHIFT
 410         beqlr
 411         mtctr   r4
 412
 413 1:      dcbf    0,r3
 414         addi    r3,r3,L1_CACHE_BYTES
 415         bdnz    1b
 416         sync                            /* wait for dcbst's to get to ram */
 417         blr
 418
 419 /*
 420  * Like above, but invalidate the D-cache.  This is used by the 8xx
 421  * to invalidate the cache so the PPC core doesn't get stale data
 422  * from the CPM (no cache snooping here :-).
 423  *
 424  * invalidate_dcache_range(unsigned long start, unsigned long stop)
 425  */
 426 _GLOBAL(invalidate_dcache_range)
 427         li      r5,L1_CACHE_BYTES-1
 428         andc    r3,r3,r5
 429         subf    r4,r3,r4
 430         add     r4,r4,r5
 431         srwi.   r4,r4,L1_CACHE_SHIFT
 432         beqlr
 433         mtctr   r4
 434
 435 1:      dcbi    0,r3
 436         addi    r3,r3,L1_CACHE_BYTES
 437         bdnz    1b
 438         sync                            /* wait for dcbi's to get to ram */
 439         blr
 440
 441 /*
 442  * Flush a particular page from the data cache to RAM.
 443  * Note: this is necessary because the instruction cache does *not*
 444  * snoop from the data cache.
 445  * This is a no-op on the 601 which has a unified cache.
 446  *
 447  *      void __flush_dcache_icache(void *page)
 448  */
 449 _GLOBAL(__flush_dcache_icache)
 450 BEGIN_FTR_SECTION
 451         blr
 452 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 453         rlwinm  r3,r3,0,0,31-PAGE_SHIFT         /* Get page base address */
 454         li      r4,PAGE_SIZE/L1_CACHE_BYTES     /* Number of lines in a page */
 455         mtctr   r4
 456         mr      r6,r3
 457 0:      dcbst   0,r3                            /* Write line to ram */
 458         addi    r3,r3,L1_CACHE_BYTES
 459         bdnz    0b
 460         sync
 461 #ifdef CONFIG_44x
 462         /* We don't flush the icache on 44x. Those have a virtual icache
 463          * and we don't have access to the virtual address here (it's
 464          * not the page vaddr but where it's mapped in user space). The
 465          * flushing of the icache on these is handled elsewhere, when
 466          * a change in the address space occurs, before returning to
 467          * user space
 468          */
 469 BEGIN_MMU_FTR_SECTION
 470         blr
 471 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
 472 #endif /* CONFIG_44x */
 473         mtctr   r4
 474 1:      icbi    0,r6
 475         addi    r6,r6,L1_CACHE_BYTES
 476         bdnz    1b
 477         sync
 478         isync
 479         blr
 480
 481 #ifndef CONFIG_BOOKE
 482 /*
 483  * Flush a particular page from the data cache to RAM, identified
 484  * by its physical address.  We turn off the MMU so we can just use
 485  * the physical address (this may be a highmem page without a kernel
 486  * mapping).
 487  *
 488  *      void __flush_dcache_icache_phys(unsigned long physaddr)
 489  */
 490 _GLOBAL(__flush_dcache_icache_phys)
 491 BEGIN_FTR_SECTION
 492         blr                                     /* for 601, do nothing */
 493 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 494         mfmsr   r10
 495         rlwinm  r0,r10,0,28,26                  /* clear DR */
 496         mtmsr   r0
 497         isync
 498         rlwinm  r3,r3,0,0,31-PAGE_SHIFT         /* Get page base address */
 499         li      r4,PAGE_SIZE/L1_CACHE_BYTES     /* Number of lines in a page */
 500         mtctr   r4
 501         mr      r6,r3
 502 0:      dcbst   0,r3                            /* Write line to ram */
 503         addi    r3,r3,L1_CACHE_BYTES
 504         bdnz    0b
 505         sync
 506         mtctr   r4
 507 1:      icbi    0,r6
 508         addi    r6,r6,L1_CACHE_BYTES
 509         bdnz    1b
 510         sync
 511         mtmsr   r10                             /* restore DR */
 512         isync
 513         blr
 514 #endif /* CONFIG_BOOKE */
 515
 516 /*
 517  * Clear pages using the dcbz instruction, which doesn't cause any
 518  * memory traffic (except to write out any cache lines which get
 519  * displaced).  This only works on cacheable memory.
 520  *
 521  * void clear_pages(void *page, int order) ;
 522  */
 523 _GLOBAL(clear_pages)
 524         li      r0,PAGE_SIZE/L1_CACHE_BYTES
 525         slw     r0,r0,r4
 526         mtctr   r0
 527 1:      dcbz    0,r3
 528         addi    r3,r3,L1_CACHE_BYTES
 529         bdnz    1b
 530         blr
 531
 532 /*
 533  * Copy a whole page.  We use the dcbz instruction on the destination
 534  * to reduce memory traffic (it eliminates the unnecessary reads of
 535  * the destination into cache).  This requires that the destination
 536  * is cacheable.
 537  */
 538 #define COPY_16_BYTES           \
 539         lwz     r6,4(r4);       \
 540         lwz     r7,8(r4);       \
 541         lwz     r8,12(r4);      \
 542         lwzu    r9,16(r4);      \
 543         stw     r6,4(r3);       \
 544         stw     r7,8(r3);       \
 545         stw     r8,12(r3);      \
 546         stwu    r9,16(r3)
 547
 548 _GLOBAL(copy_page)
 549         addi    r3,r3,-4
 550         addi    r4,r4,-4
 551
 552         li      r5,4
 553
 554 #if MAX_COPY_PREFETCH > 1
 555         li      r0,MAX_COPY_PREFETCH
 556         li      r11,4
 557         mtctr   r0
 558 11:     dcbt    r11,r4
 559         addi    r11,r11,L1_CACHE_BYTES
 560         bdnz    11b
 561 #else /* MAX_COPY_PREFETCH == 1 */
 562         dcbt    r5,r4
 563         li      r11,L1_CACHE_BYTES+4
 564 #endif /* MAX_COPY_PREFETCH */
 565         li      r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
 566         crclr   4*cr0+eq
 567 2:
 568         mtctr   r0
 569 1:
 570         dcbt    r11,r4
 571         dcbz    r5,r3
 572         COPY_16_BYTES
 573 #if L1_CACHE_BYTES >= 32
 574         COPY_16_BYTES
 575 #if L1_CACHE_BYTES >= 64
 576         COPY_16_BYTES
 577         COPY_16_BYTES
 578 #if L1_CACHE_BYTES >= 128
 579         COPY_16_BYTES
 580         COPY_16_BYTES
 581         COPY_16_BYTES
 582         COPY_16_BYTES
 583 #endif
 584 #endif
 585 #endif
 586         bdnz    1b
 587         beqlr
 588         crnot   4*cr0+eq,4*cr0+eq
 589         li      r0,MAX_COPY_PREFETCH
 590         li      r11,4
 591         b       2b
 592
 593 /*
 594  * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
 595  * void atomic_set_mask(atomic_t mask, atomic_t *addr);
 596  */
 597 _GLOBAL(atomic_clear_mask)
 598 10:     lwarx   r5,0,r4
 599         andc    r5,r5,r3
 600         PPC405_ERR77(0,r4)
 601         stwcx.  r5,0,r4
 602         bne-    10b
 603         blr
 604 _GLOBAL(atomic_set_mask)
 605 10:     lwarx   r5,0,r4
 606         or      r5,r5,r3
 607         PPC405_ERR77(0,r4)
 608         stwcx.  r5,0,r4
 609         bne-    10b
 610         blr
 611
 612 /*
 613  * Extended precision shifts.
 614  *
 615  * Updated to be valid for shift counts from 0 to 63 inclusive.
 616  * -- Gabriel
 617  *
 618  * R3/R4 has 64 bit value
 619  * R5    has shift count
 620  * result in R3/R4
 621  *
 622  *  ashrdi3: arithmetic right shift (sign propagation)
 623  *  lshrdi3: logical right shift
 624  *  ashldi3: left shift
 625  */
 626 _GLOBAL(__ashrdi3)
 627         subfic  r6,r5,32
 628         srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
 629         addi    r7,r5,32        # could be xori, or addi with -32
 630         slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
 631         rlwinm  r8,r7,0,32      # t3 = (count < 32) ? 32 : 0
 632         sraw    r7,r3,r7        # t2 = MSW >> (count-32)
 633         or      r4,r4,r6        # LSW |= t1
 634         slw     r7,r7,r8        # t2 = (count < 32) ? 0 : t2
 635         sraw    r3,r3,r5        # MSW = MSW >> count
 636         or      r4,r4,r7        # LSW |= t2
 637         blr
 638
 639 _GLOBAL(__ashldi3)
 640         subfic  r6,r5,32
 641         slw     r3,r3,r5        # MSW = count > 31 ? 0 : MSW << count
 642         addi    r7,r5,32        # could be xori, or addi with -32
 643         srw     r6,r4,r6        # t1 = count > 31 ? 0 : LSW >> (32-count)
 644         slw     r7,r4,r7        # t2 = count < 32 ? 0 : LSW << (count-32)
 645         or      r3,r3,r6        # MSW |= t1
 646         slw     r4,r4,r5        # LSW = LSW << count
 647         or      r3,r3,r7        # MSW |= t2
 648         blr
 649
 650 _GLOBAL(__lshrdi3)
 651         subfic  r6,r5,32
 652         srw     r4,r4,r5        # LSW = count > 31 ? 0 : LSW >> count
 653         addi    r7,r5,32        # could be xori, or addi with -32
 654         slw     r6,r3,r6        # t1 = count > 31 ? 0 : MSW << (32-count)
 655         srw     r7,r3,r7        # t2 = count < 32 ? 0 : MSW >> (count-32)
 656         or      r4,r4,r6        # LSW |= t1
 657         srw     r3,r3,r5        # MSW = MSW >> count
 658         or      r4,r4,r7        # LSW |= t2
 659         blr
 660
 661 /*
 662  * 64-bit comparison: __cmpdi2(s64 a, s64 b)
 663  * Returns 0 if a < b, 1 if a == b, 2 if a > b.
 664  */
 665 _GLOBAL(__cmpdi2)
 666         cmpw    r3,r5
 667         li      r3,1
 668         bne     1f
 669         cmplw   r4,r6
 670         beqlr
 671 1:      li      r3,0
 672         bltlr
 673         li      r3,2
 674         blr
 675 /*
 676  * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
 677  * Returns 0 if a < b, 1 if a == b, 2 if a > b.
 678  */
 679 _GLOBAL(__ucmpdi2)
 680         cmplw   r3,r5
 681         li      r3,1
 682         bne     1f
 683         cmplw   r4,r6
 684         beqlr
 685 1:      li      r3,0
 686         bltlr
 687         li      r3,2
 688         blr
 689
 690 _GLOBAL(__bswapdi2)
 691         rotlwi  r9,r4,8
 692         rotlwi  r10,r3,8
 693         rlwimi  r9,r4,24,0,7
 694         rlwimi  r10,r3,24,0,7
 695         rlwimi  r9,r4,24,16,23
 696         rlwimi  r10,r3,24,16,23
 697         mr      r3,r9
 698         mr      r4,r10
 699         blr
 700
 701 _GLOBAL(abs)
 702         srawi   r4,r3,31
 703         xor     r3,r3,r4
 704         sub     r3,r3,r4
 705         blr
 706
 707 #ifdef CONFIG_SMP
 708 _GLOBAL(start_secondary_resume)
 709         /* Reset stack */
 710         CURRENT_THREAD_INFO(r1, r1)
 711         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
 712         li      r3,0
 713         stw     r3,0(r1)                /* Zero the stack frame pointer */
 714         bl      start_secondary
 715         b       .
 716 #endif /* CONFIG_SMP */
 717
 718 /*
 719  * This routine is just here to keep GCC happy - sigh...
 720  */
 721 _GLOBAL(__main)
 722         blr
 723
 724 #ifdef CONFIG_KEXEC
 725         /*
 726          * Must be relocatable PIC code callable as a C function.
 727          */
 728         .globl relocate_new_kernel
 729 relocate_new_kernel:
 730         /* r3 = page_list   */
 731         /* r4 = reboot_code_buffer */
 732         /* r5 = start_address      */
 733
 734 #ifdef CONFIG_FSL_BOOKE
 735
 736         mr      r29, r3
 737         mr      r30, r4
 738         mr      r31, r5
 739
 740 #define ENTRY_MAPPING_KEXEC_SETUP
 741 #include "fsl_booke_entry_mapping.S"
 742 #undef ENTRY_MAPPING_KEXEC_SETUP
 743
 744         mr      r3, r29
 745         mr      r4, r30
 746         mr      r5, r31
 747
 748         li      r0, 0
 749 #elif defined(CONFIG_44x)
 750
 751         /* Save our parameters */
 752         mr      r29, r3
 753         mr      r30, r4
 754         mr      r31, r5
 755
 756 #ifdef CONFIG_PPC_47x
 757         /* Check for 47x cores */
 758         mfspr   r3,SPRN_PVR
 759         srwi    r3,r3,16
 760         cmplwi  cr0,r3,PVR_476@h
 761         beq     setup_map_47x
 762         cmplwi  cr0,r3,PVR_476_ISS@h
 763         beq     setup_map_47x
 764 #endif /* CONFIG_PPC_47x */
 765
 766 /*
 767  * Code for setting up 1:1 mapping for PPC440x for KEXEC
 768  *
 769  * We cannot switch off the MMU on PPC44x.
 770  * So we:
 771  * 1) Invalidate all the mappings except the one we are running from.
 772  * 2) Create a tmp mapping for our code in the other address space(TS) and
 773  *    jump to it. Invalidate the entry we started in.
 774  * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
 775  * 4) Jump to the 1:1 mapping in original TS.
 776  * 5) Invalidate the tmp mapping.
 777  *
 778  * - Based on the kexec support code for FSL BookE
 779  *
 780  */
 781
 782         /*
 783          * Load the PID with kernel PID (0).
 784          * Also load our MSR_IS and TID to MMUCR for TLB search.
 785          */
 786         li      r3, 0
 787         mtspr   SPRN_PID, r3
 788         mfmsr   r4
 789         andi.   r4,r4,MSR_IS@l
 790         beq     wmmucr
 791         oris    r3,r3,PPC44x_MMUCR_STS@h
 792 wmmucr:
 793         mtspr   SPRN_MMUCR,r3
 794         sync
 795
 796         /*
 797          * Invalidate all the TLB entries except the current entry
 798          * where we are running from
 799          */
 800         bl      0f                              /* Find our address */
 801 0:      mflr    r5                              /* Make it accessible */
 802         tlbsx   r23,0,r5                        /* Find entry we are in */
 803         li      r4,0                            /* Start at TLB entry 0 */
 804         li      r3,0                            /* Set PAGEID inval value */
 805 1:      cmpw    r23,r4                          /* Is this our entry? */
 806         beq     skip                            /* If so, skip the inval */
 807         tlbwe   r3,r4,PPC44x_TLB_PAGEID         /* If not, inval the entry */
 808 skip:
 809         addi    r4,r4,1                         /* Increment */
 810         cmpwi   r4,64                           /* Are we done? */
 811         bne     1b                              /* If not, repeat */
 812         isync
 813
 814         /* Create a temp mapping and jump to it */
 815         andi.   r6, r23, 1              /* Find the index to use */
 816         addi    r24, r6, 1              /* r24 will contain 1 or 2 */
 817
 818         mfmsr   r9                      /* get the MSR */
 819         rlwinm  r5, r9, 27, 31, 31      /* Extract the MSR[IS] */
 820         xori    r7, r5, 1               /* Use the other address space */
 821
 822         /* Read the current mapping entries */
 823         tlbre   r3, r23, PPC44x_TLB_PAGEID
 824         tlbre   r4, r23, PPC44x_TLB_XLAT
 825         tlbre   r5, r23, PPC44x_TLB_ATTRIB
 826
 827         /* Save our current XLAT entry */
 828         mr      r25, r4
 829
 830         /* Extract the TLB PageSize */
 831         li      r10, 1                  /* r10 will hold PageSize */
 832         rlwinm  r11, r3, 0, 24, 27      /* bits 24-27 */
 833
 834         /* XXX: As of now we use 256M, 4K pages */
 835         cmpwi   r11, PPC44x_TLB_256M
 836         bne     tlb_4k
 837         rotlwi  r10, r10, 28            /* r10 = 256M */
 838         b       write_out
 839 tlb_4k:
 840         cmpwi   r11, PPC44x_TLB_4K
 841         bne     default
 842         rotlwi  r10, r10, 12            /* r10 = 4K */
 843         b       write_out
 844 default:
 845         rotlwi  r10, r10, 10            /* r10 = 1K */
 846
 847 write_out:
 848         /*
 849          * Write out the tmp 1:1 mapping for this code in other address space
 850          * Fixup  EPN = RPN , TS=other address space
 851          */
 852         insrwi  r3, r7, 1, 23           /* Bit 23 is TS for PAGEID field */
 853
 854         /* Write out the tmp mapping entries */
 855         tlbwe   r3, r24, PPC44x_TLB_PAGEID
 856         tlbwe   r4, r24, PPC44x_TLB_XLAT
 857         tlbwe   r5, r24, PPC44x_TLB_ATTRIB
 858
 859         subi    r11, r10, 1             /* PageOffset Mask = PageSize - 1 */
 860         not     r10, r11                /* Mask for PageNum */
 861
 862         /* Switch to other address space in MSR */
 863         insrwi  r9, r7, 1, 26           /* Set MSR[IS] = r7 */
 864
 865         bl      1f
 866 1:      mflr    r8
 867         addi    r8, r8, (2f-1b)         /* Find the target offset */
 868
 869         /* Jump to the tmp mapping */
 870         mtspr   SPRN_SRR0, r8
 871         mtspr   SPRN_SRR1, r9
 872         rfi
 873
 874 2:
 875         /* Invalidate the entry we were executing from */
 876         li      r3, 0
 877         tlbwe   r3, r23, PPC44x_TLB_PAGEID
 878
 879         /* attribute fields. rwx for SUPERVISOR mode */
 880         li      r5, 0
 881         ori     r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
 882
 883         /* Create 1:1 mapping in 256M pages */
 884         xori    r7, r7, 1                       /* Revert back to Original TS */
 885
 886         li      r8, 0                           /* PageNumber */
 887         li      r6, 3                           /* TLB Index, start at 3  */
 888
 889 next_tlb:
 890         rotlwi  r3, r8, 28                      /* Create EPN (bits 0-3) */
 891         mr      r4, r3                          /* RPN = EPN  */
 892         ori     r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
 893         insrwi  r3, r7, 1, 23                   /* Set TS from r7 */
 894
 895         tlbwe   r3, r6, PPC44x_TLB_PAGEID       /* PageID field : EPN, V, SIZE */
 896         tlbwe   r4, r6, PPC44x_TLB_XLAT         /* Address translation : RPN   */
 897         tlbwe   r5, r6, PPC44x_TLB_ATTRIB       /* Attributes */
 898
 899         addi    r8, r8, 1                       /* Increment PN */
 900         addi    r6, r6, 1                       /* Increment TLB Index */
 901         cmpwi   r8, 8                           /* Are we done ? */
 902         bne     next_tlb
 903         isync
 904
 905         /* Jump to the new mapping 1:1 */
 906         li      r9,0
 907         insrwi  r9, r7, 1, 26                   /* Set MSR[IS] = r7 */
 908
 909         bl      1f
 910 1:      mflr    r8
 911         and     r8, r8, r11                     /* Get our offset within page */
 912         addi    r8, r8, (2f-1b)
 913
 914         and     r5, r25, r10                    /* Get our target PageNum */
 915         or      r8, r8, r5                      /* Target jump address */
 916
 917         mtspr   SPRN_SRR0, r8
 918         mtspr   SPRN_SRR1, r9
 919         rfi
 920 2:
 921         /* Invalidate the tmp entry we used */
 922         li      r3, 0
 923         tlbwe   r3, r24, PPC44x_TLB_PAGEID
 924         sync
 925         b       ppc44x_map_done
 926
 927 #ifdef CONFIG_PPC_47x
 928
 929         /* 1:1 mapping for 47x */
 930
 931 setup_map_47x:
 932
 933         /*
 934          * Load the kernel pid (0) to PID and also to MMUCR[TID].
 935          * Also set the MSR IS->MMUCR STS
 936          */
 937         li      r3, 0
 938         mtspr   SPRN_PID, r3                    /* Set PID */
 939         mfmsr   r4                              /* Get MSR */
 940         andi.   r4, r4, MSR_IS@l                /* TS=1? */
 941         beq     1f                              /* If not, leave STS=0 */
 942         oris    r3, r3, PPC47x_MMUCR_STS@h      /* Set STS=1 */
 943 1:      mtspr   SPRN_MMUCR, r3                  /* Put MMUCR */
 944         sync
 945
 946         /* Find the entry we are running from */
 947         bl      2f
 948 2:      mflr    r23
 949         tlbsx   r23, 0, r23
 950         tlbre   r24, r23, 0                     /* TLB Word 0 */
 951         tlbre   r25, r23, 1                     /* TLB Word 1 */
 952         tlbre   r26, r23, 2                     /* TLB Word 2 */
 953
 954
 955         /*
 956          * Invalidates all the tlb entries by writing to 256 RPNs(r4)
 957          * of 4k page size in all  4 ways (0-3 in r3).
 958          * This would invalidate the entire UTLB including the one we are
 959          * running from. However the shadow TLB entries would help us
 960          * to continue the execution, until we flush them (rfi/isync).
 961          */
 962         addis   r3, 0, 0x8000                   /* specify the way */
 963         addi    r4, 0, 0                        /* TLB Word0 = (EPN=0, VALID = 0) */
 964         addi    r5, 0, 0
 965         b       clear_utlb_entry
 966
 967         /* Align the loop to speed things up. from head_44x.S */
 968         .align  6
 969
 970 clear_utlb_entry:
 971
 972         tlbwe   r4, r3, 0
 973         tlbwe   r5, r3, 1
 974         tlbwe   r5, r3, 2
 975         addis   r3, r3, 0x2000                  /* Increment the way */
 976         cmpwi   r3, 0
 977         bne     clear_utlb_entry
 978         addis   r3, 0, 0x8000
 979         addis   r4, r4, 0x100                   /* Increment the EPN */
 980         cmpwi   r4, 0
 981         bne     clear_utlb_entry
 982
 983         /* Create the entries in the other address space */
 984         mfmsr   r5
 985         rlwinm  r7, r5, 27, 31, 31              /* Get the TS (Bit 26) from MSR */
 986         xori    r7, r7, 1                       /* r7 = !TS */
 987
 988         insrwi  r24, r7, 1, 21                  /* Change the TS in the saved TLB word 0 */
 989
 990         /*
 991          * write out the TLB entries for the tmp mapping
 992          * Use way '0' so that we could easily invalidate it later.
 993          */
 994         lis     r3, 0x8000                      /* Way '0' */
 995
 996         tlbwe   r24, r3, 0
 997         tlbwe   r25, r3, 1
 998         tlbwe   r26, r3, 2
 999
1000         /* Update the msr to the new TS */
1001         insrwi  r5, r7, 1, 26
1002
1003         bl      1f
1004 1:      mflr    r6
1005         addi    r6, r6, (2f-1b)
1006
1007         mtspr   SPRN_SRR0, r6
1008         mtspr   SPRN_SRR1, r5
1009         rfi
1010
1011         /*
1012          * Now we are in the tmp address space.
1013          * Create a 1:1 mapping for 0-2GiB in the original TS.
1014          */
1015 2:
1016         li      r3, 0
1017         li      r4, 0                           /* TLB Word 0 */
1018         li      r5, 0                           /* TLB Word 1 */
1019         li      r6, 0
1020         ori     r6, r6, PPC47x_TLB2_S_RWX       /* TLB word 2 */
1021
1022         li      r8, 0                           /* PageIndex */
1023
1024         xori    r7, r7, 1                       /* revert back to original TS */
1025
1026 write_utlb:
1027         rotlwi  r5, r8, 28                      /* RPN = PageIndex * 256M */
1028                                                 /* ERPN = 0 as we don't use memory above 2G */
1029
1030         mr      r4, r5                          /* EPN = RPN */
1031         ori     r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
1032         insrwi  r4, r7, 1, 21                   /* Insert the TS to Word 0 */
1033
1034         tlbwe   r4, r3, 0                       /* Write out the entries */
1035         tlbwe   r5, r3, 1
1036         tlbwe   r6, r3, 2
1037         addi    r8, r8, 1
1038         cmpwi   r8, 8                           /* Have we completed ? */
1039         bne     write_utlb
1040
1041         /* make sure we complete the TLB write up */
1042         isync
1043
1044         /*
1045          * Prepare to jump to the 1:1 mapping.
1046          * 1) Extract page size of the tmp mapping
1047          *    DSIZ = TLB_Word0[22:27]
1048          * 2) Calculate the physical address of the address
1049          *    to jump to.
1050          */
1051         rlwinm  r10, r24, 0, 22, 27
1052
1053         cmpwi   r10, PPC47x_TLB0_4K
1054         bne     0f
1055         li      r10, 0x1000                     /* r10 = 4k */
1056         bl      1f
1057
1058 0:
1059         /* Defaults to 256M */
1060         lis     r10, 0x1000
1061
1062         bl      1f
1063 1:      mflr    r4
1064         addi    r4, r4, (2f-1b)                 /* virtual address  of 2f */
1065
1066         subi    r11, r10, 1                     /* offsetmask = Pagesize - 1 */
1067         not     r10, r11                        /* Pagemask = ~(offsetmask) */
1068
1069         and     r5, r25, r10                    /* Physical page */
1070         and     r6, r4, r11                     /* offset within the current page */
1071
1072         or      r5, r5, r6                      /* Physical address for 2f */
1073
1074         /* Switch the TS in MSR to the original one */
1075         mfmsr   r8
1076         insrwi  r8, r7, 1, 26
1077
1078         mtspr   SPRN_SRR1, r8
1079         mtspr   SPRN_SRR0, r5
1080         rfi
1081
1082 2:
1083         /* Invalidate the tmp mapping */
1084         lis     r3, 0x8000                      /* Way '0' */
1085
1086         clrrwi  r24, r24, 12                    /* Clear the valid bit */
1087         tlbwe   r24, r3, 0
1088         tlbwe   r25, r3, 1
1089         tlbwe   r26, r3, 2
1090
1091         /* Make sure we complete the TLB write and flush the shadow TLB */
1092         isync
1093
1094 #endif
1095
1096 ppc44x_map_done:
1097
1098
1099         /* Restore the parameters */
1100         mr      r3, r29
1101         mr      r4, r30
1102         mr      r5, r31
1103
1104         li      r0, 0
1105 #else
1106         li      r0, 0
1107
1108         /*
1109          * Set Machine Status Register to a known status,
1110          * switch the MMU off and jump to 1: in a single step.
1111          */
1112
1113         mr      r8, r0
1114         ori     r8, r8, MSR_RI|MSR_ME
1115         mtspr   SPRN_SRR1, r8
1116         addi    r8, r4, 1f - relocate_new_kernel
1117         mtspr   SPRN_SRR0, r8
1118         sync
1119         rfi
1120
1121 1:
1122 #endif
1123         /* from this point address translation is turned off */
1124         /* and interrupts are disabled */
1125
1126         /* set a new stack at the bottom of our page... */
1127         /* (not really needed now) */
1128         addi    r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
1129         stw     r0, 0(r1)
1130
1131         /* Do the copies */
1132         li      r6, 0 /* checksum */
1133         mr      r0, r3
1134         b       1f
1135
1136 0:      /* top, read another word for the indirection page */
1137         lwzu    r0, 4(r3)
1138
1139 1:
1140         /* is it a destination page? (r8) */
1141         rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
1142         beq     2f
1143
1144         rlwinm  r8, r0, 0, 0, 19 /* clear kexec flags, page align */
1145         b       0b
1146
1147 2:      /* is it an indirection page? (r3) */
1148         rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
1149         beq     2f
1150
1151         rlwinm  r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1152         subi    r3, r3, 4
1153         b       0b
1154
1155 2:      /* are we done? */
1156         rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
1157         beq     2f
1158         b       3f
1159
1160 2:      /* is it a source page? (r9) */
1161         rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
1162         beq     0b
1163
1164         rlwinm  r9, r0, 0, 0, 19 /* clear kexec flags, page align */
1165
1166         li      r7, PAGE_SIZE / 4
1167         mtctr   r7
1168         subi    r9, r9, 4
1169         subi    r8, r8, 4
1170 9:
1171         lwzu    r0, 4(r9)  /* do the copy */
1172         xor     r6, r6, r0
1173         stwu    r0, 4(r8)
1174         dcbst   0, r8
1175         sync
1176         icbi    0, r8
1177         bdnz    9b
1178
1179         addi    r9, r9, 4
1180         addi    r8, r8, 4
1181         b       0b
1182
1183 3:
1184
1185         /* To be certain of avoiding problems with self-modifying code
1186          * execute a serializing instruction here.
1187          */
1188         isync
1189         sync
1190
1191         mfspr   r3, SPRN_PIR /* current core we are running on */
1192         mr      r4, r5 /* load physical address of chunk called */
1193
1194         /* jump to the entry point, usually the setup routine */
1195         mtlr    r5
1196         blrl
1197
1198 1:      b       1b
1199
1200 relocate_new_kernel_end:
1201
1202         .globl relocate_new_kernel_size
1203 relocate_new_kernel_size:
1204         .long relocate_new_kernel_end - relocate_new_kernel
1205 #endif