arch/powerpc/kernel/misc_64.S

   1 /*
   2  * This file contains miscellaneous low-level functions.
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
   6  * and Paul Mackerras.
   7  * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
   8  * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  *
  15  */
  16
  17 #include <linux/sys.h>
  18 #include <asm/unistd.h>
  19 #include <asm/errno.h>
  20 #include <asm/processor.h>
  21 #include <asm/page.h>
  22 #include <asm/cache.h>
  23 #include <asm/ppc_asm.h>
  24 #include <asm/asm-offsets.h>
  25 #include <asm/cputable.h>
  26 #include <asm/thread_info.h>
  27 #include <asm/kexec.h>
  28 #include <asm/ptrace.h>
  29
  30         .text
  31
  32 _GLOBAL(call_do_softirq)
  33         mflr    r0
  34         std     r0,16(r1)
  35         stdu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
  36         mr      r1,r3
  37         bl      .__do_softirq
  38         ld      r1,0(r1)
  39         ld      r0,16(r1)
  40         mtlr    r0
  41         blr
  42
  43 _GLOBAL(call_do_irq)
  44         mflr    r0
  45         std     r0,16(r1)
  46         stdu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
  47         mr      r1,r4
  48         bl      .__do_irq
  49         ld      r1,0(r1)
  50         ld      r0,16(r1)
  51         mtlr    r0
  52         blr
  53
  54         .section        ".toc","aw"
  55 PPC64_CACHES:
  56         .tc             ppc64_caches[TC],ppc64_caches
  57         .section        ".text"
  58
  59 /*
  60  * Write any modified data cache blocks out to memory
  61  * and invalidate the corresponding instruction cache blocks.
  62  *
  63  * flush_icache_range(unsigned long start, unsigned long stop)
  64  *
  65  *   flush all bytes from start through stop-1 inclusive
  66  */
  67
  68 _KPROBE(flush_icache_range)
  69 BEGIN_FTR_SECTION
  70         blr
  71 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
  72 /*
  73  * Flush the data cache to memory
  74  *
  75  * Different systems have different cache line sizes
  76  * and in some cases i-cache and d-cache line sizes differ from
  77  * each other.
  78  */
  79         ld      r10,PPC64_CACHES@toc(r2)
  80         lwz     r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
  81         addi    r5,r7,-1
  82         andc    r6,r3,r5                /* round low to line bdy */
  83         subf    r8,r6,r4                /* compute length */
  84         add     r8,r8,r5                /* ensure we get enough */
  85         lwz     r9,DCACHEL1LOGLINESIZE(r10)     /* Get log-2 of cache line size */
  86         srw.    r8,r8,r9                /* compute line count */
  87         beqlr                           /* nothing to do? */
  88         mtctr   r8
  89 1:      dcbst   0,r6
  90         add     r6,r6,r7
  91         bdnz    1b
  92         sync
  93
  94 /* Now invalidate the instruction cache */
  95
  96         lwz     r7,ICACHEL1LINESIZE(r10)        /* Get Icache line size */
  97         addi    r5,r7,-1
  98         andc    r6,r3,r5                /* round low to line bdy */
  99         subf    r8,r6,r4                /* compute length */
 100         add     r8,r8,r5
 101         lwz     r9,ICACHEL1LOGLINESIZE(r10)     /* Get log-2 of Icache line size */
 102         srw.    r8,r8,r9                /* compute line count */
 103         beqlr                           /* nothing to do? */
 104         mtctr   r8
 105 2:      icbi    0,r6
 106         add     r6,r6,r7
 107         bdnz    2b
 108         isync
 109         blr
 110         .previous .text
 111 /*
 112  * Like above, but only do the D-cache.
 113  *
 114  * flush_dcache_range(unsigned long start, unsigned long stop)
 115  *
 116  *    flush all bytes from start to stop-1 inclusive
 117  */
 118 _GLOBAL(flush_dcache_range)
 119
 120 /*
 121  * Flush the data cache to memory
 122  *
 123  * Different systems have different cache line sizes
 124  */
 125         ld      r10,PPC64_CACHES@toc(r2)
 126         lwz     r7,DCACHEL1LINESIZE(r10)        /* Get dcache line size */
 127         addi    r5,r7,-1
 128         andc    r6,r3,r5                /* round low to line bdy */
 129         subf    r8,r6,r4                /* compute length */
 130         add     r8,r8,r5                /* ensure we get enough */
 131         lwz     r9,DCACHEL1LOGLINESIZE(r10)     /* Get log-2 of dcache line size */
 132         srw.    r8,r8,r9                /* compute line count */
 133         beqlr                           /* nothing to do? */
 134         mtctr   r8
 135 0:      dcbst   0,r6
 136         add     r6,r6,r7
 137         bdnz    0b
 138         sync
 139         blr
 140
 141 /*
 142  * Like above, but works on non-mapped physical addresses.
 143  * Use only for non-LPAR setups ! It also assumes real mode
 144  * is cacheable. Used for flushing out the DART before using
 145  * it as uncacheable memory
 146  *
 147  * flush_dcache_phys_range(unsigned long start, unsigned long stop)
 148  *
 149  *    flush all bytes from start to stop-1 inclusive
 150  */
 151 _GLOBAL(flush_dcache_phys_range)
 152         ld      r10,PPC64_CACHES@toc(r2)
 153         lwz     r7,DCACHEL1LINESIZE(r10)        /* Get dcache line size */
 154         addi    r5,r7,-1
 155         andc    r6,r3,r5                /* round low to line bdy */
 156         subf    r8,r6,r4                /* compute length */
 157         add     r8,r8,r5                /* ensure we get enough */
 158         lwz     r9,DCACHEL1LOGLINESIZE(r10)     /* Get log-2 of dcache line size */
 159         srw.    r8,r8,r9                /* compute line count */
 160         beqlr                           /* nothing to do? */
 161         mfmsr   r5                      /* Disable MMU Data Relocation */
 162         ori     r0,r5,MSR_DR
 163         xori    r0,r0,MSR_DR
 164         sync
 165         mtmsr   r0
 166         sync
 167         isync
 168         mtctr   r8
 169 0:      dcbst   0,r6
 170         add     r6,r6,r7
 171         bdnz    0b
 172         sync
 173         isync
 174         mtmsr   r5                      /* Re-enable MMU Data Relocation */
 175         sync
 176         isync
 177         blr
 178
 179 _GLOBAL(flush_inval_dcache_range)
 180         ld      r10,PPC64_CACHES@toc(r2)
 181         lwz     r7,DCACHEL1LINESIZE(r10)        /* Get dcache line size */
 182         addi    r5,r7,-1
 183         andc    r6,r3,r5                /* round low to line bdy */
 184         subf    r8,r6,r4                /* compute length */
 185         add     r8,r8,r5                /* ensure we get enough */
 186         lwz     r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
 187         srw.    r8,r8,r9                /* compute line count */
 188         beqlr                           /* nothing to do? */
 189         sync
 190         isync
 191         mtctr   r8
 192 0:      dcbf    0,r6
 193         add     r6,r6,r7
 194         bdnz    0b
 195         sync
 196         isync
 197         blr
 198
 199
 200 /*
 201  * Flush a particular page from the data cache to RAM.
 202  * Note: this is necessary because the instruction cache does *not*
 203  * snoop from the data cache.
 204  *
 205  *      void __flush_dcache_icache(void *page)
 206  */
 207 _GLOBAL(__flush_dcache_icache)
 208 /*
 209  * Flush the data cache to memory
 210  *
 211  * Different systems have different cache line sizes
 212  */
 213
 214 /* Flush the dcache */
 215         ld      r7,PPC64_CACHES@toc(r2)
 216         clrrdi  r3,r3,PAGE_SHIFT                    /* Page align */
 217         lwz     r4,DCACHEL1LINESPERPAGE(r7)     /* Get # dcache lines per page */
 218         lwz     r5,DCACHEL1LINESIZE(r7)         /* Get dcache line size */
 219         mr      r6,r3
 220         mtctr   r4
 221 0:      dcbst   0,r6
 222         add     r6,r6,r5
 223         bdnz    0b
 224         sync
 225
 226 /* Now invalidate the icache */
 227
 228         lwz     r4,ICACHEL1LINESPERPAGE(r7)     /* Get # icache lines per page */
 229         lwz     r5,ICACHEL1LINESIZE(r7)         /* Get icache line size */
 230         mtctr   r4
 231 1:      icbi    0,r3
 232         add     r3,r3,r5
 233         bdnz    1b
 234         isync
 235         blr
 236
 237 _GLOBAL(__bswapdi2)
 238         srdi    r8,r3,32
 239         rlwinm  r7,r3,8,0xffffffff
 240         rlwimi  r7,r3,24,0,7
 241         rlwinm  r9,r8,8,0xffffffff
 242         rlwimi  r7,r3,24,16,23
 243         rlwimi  r9,r8,24,0,7
 244         rlwimi  r9,r8,24,16,23
 245         sldi    r7,r7,32
 246         or      r3,r7,r9
 247         blr
 248
 249 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
 250
 251 _GLOBAL(rmci_on)
 252         sync
 253         isync
 254         li      r3,0x100
 255         rldicl  r3,r3,32,0
 256         mfspr   r5,SPRN_HID4
 257         or      r5,r5,r3
 258         sync
 259         mtspr   SPRN_HID4,r5
 260         isync
 261         slbia
 262         isync
 263         sync
 264         blr
 265
 266 _GLOBAL(rmci_off)
 267         sync
 268         isync
 269         li      r3,0x100
 270         rldicl  r3,r3,32,0
 271         mfspr   r5,SPRN_HID4
 272         andc    r5,r5,r3
 273         sync
 274         mtspr   SPRN_HID4,r5
 275         isync
 276         slbia
 277         isync
 278         sync
 279         blr
 280
 281 /*
 282  * Do an IO access in real mode
 283  */
 284 _GLOBAL(real_readb)
 285         mfmsr   r7
 286         ori     r0,r7,MSR_DR
 287         xori    r0,r0,MSR_DR
 288         sync
 289         mtmsrd  r0
 290         sync
 291         isync
 292         mfspr   r6,SPRN_HID4
 293         rldicl  r5,r6,32,0
 294         ori     r5,r5,0x100
 295         rldicl  r5,r5,32,0
 296         sync
 297         mtspr   SPRN_HID4,r5
 298         isync
 299         slbia
 300         isync
 301         lbz     r3,0(r3)
 302         sync
 303         mtspr   SPRN_HID4,r6
 304         isync
 305         slbia
 306         isync
 307         mtmsrd  r7
 308         sync
 309         isync
 310         blr
 311
 312         /*
 313  * Do an IO access in real mode
 314  */
 315 _GLOBAL(real_writeb)
 316         mfmsr   r7
 317         ori     r0,r7,MSR_DR
 318         xori    r0,r0,MSR_DR
 319         sync
 320         mtmsrd  r0
 321         sync
 322         isync
 323         mfspr   r6,SPRN_HID4
 324         rldicl  r5,r6,32,0
 325         ori     r5,r5,0x100
 326         rldicl  r5,r5,32,0
 327         sync
 328         mtspr   SPRN_HID4,r5
 329         isync
 330         slbia
 331         isync
 332         stb     r3,0(r4)
 333         sync
 334         mtspr   SPRN_HID4,r6
 335         isync
 336         slbia
 337         isync
 338         mtmsrd  r7
 339         sync
 340         isync
 341         blr
 342 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
 343
 344 #ifdef CONFIG_PPC_PASEMI
 345
 346 _GLOBAL(real_205_readb)
 347         mfmsr   r7
 348         ori     r0,r7,MSR_DR
 349         xori    r0,r0,MSR_DR
 350         sync
 351         mtmsrd  r0
 352         sync
 353         isync
 354         LBZCIX(R3,R0,R3)
 355         isync
 356         mtmsrd  r7
 357         sync
 358         isync
 359         blr
 360
 361 _GLOBAL(real_205_writeb)
 362         mfmsr   r7
 363         ori     r0,r7,MSR_DR
 364         xori    r0,r0,MSR_DR
 365         sync
 366         mtmsrd  r0
 367         sync
 368         isync
 369         STBCIX(R3,R0,R4)
 370         isync
 371         mtmsrd  r7
 372         sync
 373         isync
 374         blr
 375
 376 #endif /* CONFIG_PPC_PASEMI */
 377
 378
 379 #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
 380 /*
 381  * SCOM access functions for 970 (FX only for now)
 382  *
 383  * unsigned long scom970_read(unsigned int address);
 384  * void scom970_write(unsigned int address, unsigned long value);
 385  *
 386  * The address passed in is the 24 bits register address. This code
 387  * is 970 specific and will not check the status bits, so you should
 388  * know what you are doing.
 389  */
 390 _GLOBAL(scom970_read)
 391         /* interrupts off */
 392         mfmsr   r4
 393         ori     r0,r4,MSR_EE
 394         xori    r0,r0,MSR_EE
 395         mtmsrd  r0,1
 396
 397         /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
 398          * (including parity). On current CPUs they must be 0'd,
 399          * and finally or in RW bit
 400          */
 401         rlwinm  r3,r3,8,0,15
 402         ori     r3,r3,0x8000
 403
 404         /* do the actual scom read */
 405         sync
 406         mtspr   SPRN_SCOMC,r3
 407         isync
 408         mfspr   r3,SPRN_SCOMD
 409         isync
 410         mfspr   r0,SPRN_SCOMC
 411         isync
 412
 413         /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
 414          * that's the best we can do). Not implemented yet as we don't use
 415          * the scom on any of the bogus CPUs yet, but may have to be done
 416          * ultimately
 417          */
 418
 419         /* restore interrupts */
 420         mtmsrd  r4,1
 421         blr
 422
 423
 424 _GLOBAL(scom970_write)
 425         /* interrupts off */
 426         mfmsr   r5
 427         ori     r0,r5,MSR_EE
 428         xori    r0,r0,MSR_EE
 429         mtmsrd  r0,1
 430
 431         /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
 432          * (including parity). On current CPUs they must be 0'd.
 433          */
 434
 435         rlwinm  r3,r3,8,0,15
 436
 437         sync
 438         mtspr   SPRN_SCOMD,r4      /* write data */
 439         isync
 440         mtspr   SPRN_SCOMC,r3      /* write command */
 441         isync
 442         mfspr   3,SPRN_SCOMC
 443         isync
 444
 445         /* restore interrupts */
 446         mtmsrd  r5,1
 447         blr
 448 #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
 449
 450 /* kexec_wait(phys_cpu)
 451  *
 452  * wait for the flag to change, indicating this kernel is going away but
 453  * the slave code for the next one is at addresses 0 to 100.
 454  *
 455  * This is used by all slaves, even those that did not find a matching
 456  * paca in the secondary startup code.
 457  *
 458  * Physical (hardware) cpu id should be in r3.
 459  */
 460 _GLOBAL(kexec_wait)
 461         bl      1f
 462 1:      mflr    r5
 463         addi    r5,r5,kexec_flag-1b
 464
 465 99:     HMT_LOW
 466 #ifdef CONFIG_KEXEC             /* use no memory without kexec */
 467         lwz     r4,0(r5)
 468         cmpwi   0,r4,0
 469         bnea    0x60
 470 #endif
 471         b       99b
 472
 473 /* this can be in text because we won't change it until we are
 474  * running in real anyways
 475  */
 476 kexec_flag:
 477         .long   0
 478
 479
 480 #ifdef CONFIG_KEXEC
 481
 482 /* kexec_smp_wait(void)
 483  *
 484  * call with interrupts off
 485  * note: this is a terminal routine, it does not save lr
 486  *
 487  * get phys id from paca
 488  * switch to real mode
 489  * mark the paca as no longer used
 490  * join other cpus in kexec_wait(phys_id)
 491  */
 492 _GLOBAL(kexec_smp_wait)
 493         lhz     r3,PACAHWCPUID(r13)
 494         bl      real_mode
 495
 496         li      r4,KEXEC_STATE_REAL_MODE
 497         stb     r4,PACAKEXECSTATE(r13)
 498         SYNC
 499
 500         b       .kexec_wait
 501
 502 /*
 503  * switch to real mode (turn mmu off)
 504  * we use the early kernel trick that the hardware ignores bits
 505  * 0 and 1 (big endian) of the effective address in real mode
 506  *
 507  * don't overwrite r3 here, it is live for kexec_wait above.
 508  */
 509 real_mode:      /* assume normal blr return */
 510 1:      li      r9,MSR_RI
 511         li      r10,MSR_DR|MSR_IR
 512         mflr    r11             /* return address to SRR0 */
 513         mfmsr   r12
 514         andc    r9,r12,r9
 515         andc    r10,r12,r10
 516
 517         mtmsrd  r9,1
 518         mtspr   SPRN_SRR1,r10
 519         mtspr   SPRN_SRR0,r11
 520         rfid
 521
 522
 523 /*
 524  * kexec_sequence(newstack, start, image, control, clear_all())
 525  *
 526  * does the grungy work with stack switching and real mode switches
 527  * also does simple calls to other code
 528  */
 529
 530 _GLOBAL(kexec_sequence)
 531         mflr    r0
 532         std     r0,16(r1)
 533
 534         /* switch stacks to newstack -- &kexec_stack.stack */
 535         stdu    r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
 536         mr      r1,r3
 537
 538         li      r0,0
 539         std     r0,16(r1)
 540
 541         /* save regs for local vars on new stack.
 542          * yes, we won't go back, but ...
 543          */
 544         std     r31,-8(r1)
 545         std     r30,-16(r1)
 546         std     r29,-24(r1)
 547         std     r28,-32(r1)
 548         std     r27,-40(r1)
 549         std     r26,-48(r1)
 550         std     r25,-56(r1)
 551
 552         stdu    r1,-STACK_FRAME_OVERHEAD-64(r1)
 553
 554         /* save args into preserved regs */
 555         mr      r31,r3                  /* newstack (both) */
 556         mr      r30,r4                  /* start (real) */
 557         mr      r29,r5                  /* image (virt) */
 558         mr      r28,r6                  /* control, unused */
 559         mr      r27,r7                  /* clear_all() fn desc */
 560         mr      r26,r8                  /* spare */
 561         lhz     r25,PACAHWCPUID(r13)    /* get our phys cpu from paca */
 562
 563         /* disable interrupts, we are overwriting kernel data next */
 564         mfmsr   r3
 565         rlwinm  r3,r3,0,17,15
 566         mtmsrd  r3,1
 567
 568         /* copy dest pages, flush whole dest image */
 569         mr      r3,r29
 570         bl      .kexec_copy_flush       /* (image) */
 571
 572         /* turn off mmu */
 573         bl      real_mode
 574
 575         /* copy  0x100 bytes starting at start to 0 */
 576         li      r3,0
 577         mr      r4,r30          /* start, aka phys mem offset */
 578         li      r5,0x100
 579         li      r6,0
 580         bl      .copy_and_flush /* (dest, src, copy limit, start offset) */
 581 1:      /* assume normal blr return */
 582
 583         /* release other cpus to the new kernel secondary start at 0x60 */
 584         mflr    r5
 585         li      r6,1
 586         stw     r6,kexec_flag-1b(5)
 587
 588         /* clear out hardware hash page table and tlb */
 589         ld      r5,0(r27)               /* deref function descriptor */
 590         mtctr   r5
 591         bctrl                           /* ppc_md.hpte_clear_all(void); */
 592
 593 /*
 594  *   kexec image calling is:
 595  *      the first 0x100 bytes of the entry point are copied to 0
 596  *
 597  *      all slaves branch to slave = 0x60 (absolute)
 598  *              slave(phys_cpu_id);
 599  *
 600  *      master goes to start = entry point
 601  *              start(phys_cpu_id, start, 0);
 602  *
 603  *
 604  *   a wrapper is needed to call existing kernels, here is an approximate
 605  *   description of one method:
 606  *
 607  * v2: (2.6.10)
 608  *   start will be near the boot_block (maybe 0x100 bytes before it?)
 609  *   it will have a 0x60, which will b to boot_block, where it will wait
 610  *   and 0 will store phys into struct boot-block and load r3 from there,
 611  *   copy kernel 0-0x100 and tell slaves to back down to 0x60 again
 612  *
 613  * v1: (2.6.9)
 614  *    boot block will have all cpus scanning device tree to see if they
 615  *    are the boot cpu ?????
 616  *    other device tree differences (prop sizes, va vs pa, etc)...
 617  */
 618         mr      r3,r25  # my phys cpu
 619         mr      r4,r30  # start, aka phys mem offset
 620         mtlr    4
 621         li      r5,0
 622         blr     /* image->start(physid, image->start, 0); */
 623 #endif /* CONFIG_KEXEC */