2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
30 #include <asm/processor.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/byteorder.h>
35 #include <asm/machdep.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/firmware.h>
40 static DEFINE_SPINLOCK(hose_spinlock
);
42 /* XXX kill that some day ... */
43 static int global_phb_number
; /* Global phb counter */
45 /* ISA Memory physical address */
46 resource_size_t isa_mem_base
;
48 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
49 unsigned int ppc_pci_flags
= 0;
52 static struct dma_mapping_ops
*pci_dma_ops
;
54 void set_pci_dma_ops(struct dma_mapping_ops
*dma_ops
)
56 pci_dma_ops
= dma_ops
;
59 struct dma_mapping_ops
*get_pci_dma_ops(void)
63 EXPORT_SYMBOL(get_pci_dma_ops
);
65 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
67 return dma_set_mask(&dev
->dev
, mask
);
70 int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
74 rc
= dma_set_mask(&dev
->dev
, mask
);
75 dev
->dev
.coherent_dma_mask
= dev
->dma_mask
;
80 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
82 struct pci_controller
*phb
;
84 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
87 spin_lock(&hose_spinlock
);
88 phb
->global_number
= global_phb_number
++;
89 list_add_tail(&phb
->list_node
, &hose_list
);
90 spin_unlock(&hose_spinlock
);
92 phb
->is_dynamic
= mem_init_done
;
95 int nid
= of_node_to_nid(dev
);
97 if (nid
< 0 || !node_online(nid
))
100 PHB_SET_NODE(phb
, nid
);
106 void pcibios_free_controller(struct pci_controller
*phb
)
108 spin_lock(&hose_spinlock
);
109 list_del(&phb
->list_node
);
110 spin_unlock(&hose_spinlock
);
116 int pcibios_vaddr_is_ioport(void __iomem
*address
)
119 struct pci_controller
*hose
;
122 spin_lock(&hose_spinlock
);
123 list_for_each_entry(hose
, &hose_list
, list_node
) {
125 size
= hose
->pci_io_size
;
127 size
= hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
129 if (address
>= hose
->io_base_virt
&&
130 address
< (hose
->io_base_virt
+ size
)) {
135 spin_unlock(&hose_spinlock
);
140 * Return the domain number for this bus.
142 int pci_domain_nr(struct pci_bus
*bus
)
144 struct pci_controller
*hose
= pci_bus_to_host(bus
);
146 return hose
->global_number
;
148 EXPORT_SYMBOL(pci_domain_nr
);
152 /* This routine is meant to be used early during boot, when the
153 * PCI bus numbers have not yet been assigned, and you need to
154 * issue PCI config cycles to an OF device.
155 * It could also be used to "fix" RTAS config cycles if you want
156 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
159 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
162 struct pci_controller
*hose
, *tmp
;
163 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
164 if (hose
->dn
== node
)
171 static ssize_t
pci_show_devspec(struct device
*dev
,
172 struct device_attribute
*attr
, char *buf
)
174 struct pci_dev
*pdev
;
175 struct device_node
*np
;
177 pdev
= to_pci_dev (dev
);
178 np
= pci_device_to_OF_node(pdev
);
179 if (np
== NULL
|| np
->full_name
== NULL
)
181 return sprintf(buf
, "%s", np
->full_name
);
183 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
184 #endif /* CONFIG_PPC_OF */
186 /* Add sysfs properties */
187 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
190 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
193 #endif /* CONFIG_PPC_OF */
197 char __devinit
*pcibios_setup(char *str
)
203 * Reads the interrupt pin to determine if interrupt is use by card.
204 * If the interrupt is used, then gets the interrupt line from the
205 * openfirmware and sets it in the pci_dev and pci_config line.
207 int pci_read_irq_line(struct pci_dev
*pci_dev
)
212 /* The current device-tree that iSeries generates from the HV
213 * PCI informations doesn't contain proper interrupt routing,
214 * and all the fallback would do is print out crap, so we
215 * don't attempt to resolve the interrupts here at all, some
216 * iSeries specific fixup does it.
218 * In the long run, we will hopefully fix the generated device-tree
221 #ifdef CONFIG_PPC_ISERIES
222 if (firmware_has_feature(FW_FEATURE_ISERIES
))
226 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
229 memset(&oirq
, 0xff, sizeof(oirq
));
231 /* Try to get a mapping from the device-tree */
232 if (of_irq_map_pci(pci_dev
, &oirq
)) {
235 /* If that fails, lets fallback to what is in the config
236 * space and map that through the default controller. We
237 * also set the type to level low since that's what PCI
238 * interrupts are. If your platform does differently, then
239 * either provide a proper interrupt tree or don't use this
242 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
246 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
247 line
== 0xff || line
== 0) {
250 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
253 virq
= irq_create_mapping(NULL
, line
);
255 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
257 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
258 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
259 oirq
.controller
? oirq
.controller
->full_name
:
262 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
266 pr_debug(" Failed to map !\n");
270 pr_debug(" Mapped to linux irq %d\n", virq
);
276 EXPORT_SYMBOL(pci_read_irq_line
);
279 * Platform support for /proc/bus/pci/X/Y mmap()s,
280 * modelled on the sparc64 implementation by Dave Miller.
285 * Adjust vm_pgoff of VMA such that it is the physical page offset
286 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
288 * Basically, the user finds the base address for his device which he wishes
289 * to mmap. They read the 32-bit value from the config space base register,
290 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
291 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
293 * Returns negative error code on failure, zero on success.
295 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
296 resource_size_t
*offset
,
297 enum pci_mmap_state mmap_state
)
299 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
300 unsigned long io_offset
= 0;
304 return NULL
; /* should never happen */
306 /* If memory, add on the PCI bridge address offset */
307 if (mmap_state
== pci_mmap_mem
) {
308 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
309 *offset
+= hose
->pci_mem_offset
;
311 res_bit
= IORESOURCE_MEM
;
313 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
314 *offset
+= io_offset
;
315 res_bit
= IORESOURCE_IO
;
319 * Check that the offset requested corresponds to one of the
320 * resources of the device.
322 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
323 struct resource
*rp
= &dev
->resource
[i
];
324 int flags
= rp
->flags
;
326 /* treat ROM as memory (should be already) */
327 if (i
== PCI_ROM_RESOURCE
)
328 flags
|= IORESOURCE_MEM
;
330 /* Active and same type? */
331 if ((flags
& res_bit
) == 0)
334 /* In the range of this resource? */
335 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
338 /* found it! construct the final physical address */
339 if (mmap_state
== pci_mmap_io
)
340 *offset
+= hose
->io_base_phys
- io_offset
;
348 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
351 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
353 enum pci_mmap_state mmap_state
,
356 unsigned long prot
= pgprot_val(protection
);
358 /* Write combine is always 0 on non-memory space mappings. On
359 * memory space, if the user didn't pass 1, we check for a
360 * "prefetchable" resource. This is a bit hackish, but we use
361 * this to workaround the inability of /sysfs to provide a write
364 if (mmap_state
!= pci_mmap_mem
)
366 else if (write_combine
== 0) {
367 if (rp
->flags
& IORESOURCE_PREFETCH
)
371 /* XXX would be nice to have a way to ask for write-through */
373 return pgprot_noncached_wc(prot
);
375 return pgprot_noncached(prot
);
379 * This one is used by /dev/mem and fbdev who have no clue about the
380 * PCI device, it tries to find the PCI device first and calls the
383 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
388 struct pci_dev
*pdev
= NULL
;
389 struct resource
*found
= NULL
;
390 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
393 if (page_is_ram(pfn
))
396 prot
= pgprot_noncached(prot
);
397 for_each_pci_dev(pdev
) {
398 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
399 struct resource
*rp
= &pdev
->resource
[i
];
400 int flags
= rp
->flags
;
402 /* Active and same type? */
403 if ((flags
& IORESOURCE_MEM
) == 0)
405 /* In the range of this resource? */
406 if (offset
< (rp
->start
& PAGE_MASK
) ||
416 if (found
->flags
& IORESOURCE_PREFETCH
)
417 prot
= pgprot_noncached_wc(prot
);
421 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
422 (unsigned long long)offset
, pgprot_val(prot
));
429 * Perform the actual remap of the pages for a PCI device mapping, as
430 * appropriate for this architecture. The region in the process to map
431 * is described by vm_start and vm_end members of VMA, the base physical
432 * address is found in vm_pgoff.
433 * The pci device structure is provided so that architectures may make mapping
434 * decisions on a per-device or per-bus basis.
436 * Returns a negative error code on failure, zero on success.
438 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
439 enum pci_mmap_state mmap_state
, int write_combine
)
441 resource_size_t offset
=
442 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
446 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
450 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
451 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
453 mmap_state
, write_combine
);
455 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
456 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
461 /* This provides legacy IO read access on a bus */
462 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
464 unsigned long offset
;
465 struct pci_controller
*hose
= pci_bus_to_host(bus
);
466 struct resource
*rp
= &hose
->io_resource
;
469 /* Check if port can be supported by that bus. We only check
470 * the ranges of the PHB though, not the bus itself as the rules
471 * for forwarding legacy cycles down bridges are not our problem
472 * here. So if the host bridge supports it, we do it.
474 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
477 if (!(rp
->flags
& IORESOURCE_IO
))
479 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
481 addr
= hose
->io_base_virt
+ port
;
485 *((u8
*)val
) = in_8(addr
);
490 *((u16
*)val
) = in_le16(addr
);
495 *((u32
*)val
) = in_le32(addr
);
501 /* This provides legacy IO write access on a bus */
502 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
504 unsigned long offset
;
505 struct pci_controller
*hose
= pci_bus_to_host(bus
);
506 struct resource
*rp
= &hose
->io_resource
;
509 /* Check if port can be supported by that bus. We only check
510 * the ranges of the PHB though, not the bus itself as the rules
511 * for forwarding legacy cycles down bridges are not our problem
512 * here. So if the host bridge supports it, we do it.
514 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
517 if (!(rp
->flags
& IORESOURCE_IO
))
519 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
521 addr
= hose
->io_base_virt
+ port
;
523 /* WARNING: The generic code is idiotic. It gets passed a pointer
524 * to what can be a 1, 2 or 4 byte quantity and always reads that
525 * as a u32, which means that we have to correct the location of
526 * the data read within those 32 bits for size 1 and 2
530 out_8(addr
, val
>> 24);
535 out_le16(addr
, val
>> 16);
546 /* This provides legacy IO or memory mmap access on a bus */
547 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
548 struct vm_area_struct
*vma
,
549 enum pci_mmap_state mmap_state
)
551 struct pci_controller
*hose
= pci_bus_to_host(bus
);
552 resource_size_t offset
=
553 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
554 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
557 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
558 pci_domain_nr(bus
), bus
->number
,
559 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
560 (unsigned long long)offset
,
561 (unsigned long long)(offset
+ size
- 1));
563 if (mmap_state
== pci_mmap_mem
) {
566 * Because X is lame and can fail starting if it gets an error trying
567 * to mmap legacy_mem (instead of just moving on without legacy memory
568 * access) we fake it here by giving it anonymous memory, effectively
569 * behaving just like /dev/zero
571 if ((offset
+ size
) > hose
->isa_mem_size
) {
573 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
574 current
->comm
, current
->pid
, pci_domain_nr(bus
), bus
->number
);
575 if (vma
->vm_flags
& VM_SHARED
)
576 return shmem_zero_setup(vma
);
579 offset
+= hose
->isa_mem_phys
;
581 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
582 unsigned long roffset
= offset
+ io_offset
;
583 rp
= &hose
->io_resource
;
584 if (!(rp
->flags
& IORESOURCE_IO
))
586 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
588 offset
+= hose
->io_base_phys
;
590 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
592 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
593 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
594 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
595 vma
->vm_end
- vma
->vm_start
,
599 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
600 const struct resource
*rsrc
,
601 resource_size_t
*start
, resource_size_t
*end
)
603 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
604 resource_size_t offset
= 0;
609 if (rsrc
->flags
& IORESOURCE_IO
)
610 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
612 /* We pass a fully fixed up address to userland for MMIO instead of
613 * a BAR value because X is lame and expects to be able to use that
614 * to pass to /dev/mem !
616 * That means that we'll have potentially 64 bits values where some
617 * userland apps only expect 32 (like X itself since it thinks only
618 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
621 * Hopefully, the sysfs insterface is immune to that gunk. Once X
622 * has been fixed (and the fix spread enough), we can re-enable the
623 * 2 lines below and pass down a BAR value to userland. In that case
624 * we'll also have to re-enable the matching code in
625 * __pci_mmap_make_offset().
630 else if (rsrc
->flags
& IORESOURCE_MEM
)
631 offset
= hose
->pci_mem_offset
;
634 *start
= rsrc
->start
- offset
;
635 *end
= rsrc
->end
- offset
;
639 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
640 * @hose: newly allocated pci_controller to be setup
641 * @dev: device node of the host bridge
642 * @primary: set if primary bus (32 bits only, soon to be deprecated)
644 * This function will parse the "ranges" property of a PCI host bridge device
645 * node and setup the resource mapping of a pci controller based on its
648 * Life would be boring if it wasn't for a few issues that we have to deal
651 * - We can only cope with one IO space range and up to 3 Memory space
652 * ranges. However, some machines (thanks Apple !) tend to split their
653 * space into lots of small contiguous ranges. So we have to coalesce.
655 * - We can only cope with all memory ranges having the same offset
656 * between CPU addresses and PCI addresses. Unfortunately, some bridges
657 * are setup for a large 1:1 mapping along with a small "window" which
658 * maps PCI address 0 to some arbitrary high address of the CPU space in
659 * order to give access to the ISA memory hole.
660 * The way out of here that I've chosen for now is to always set the
661 * offset based on the first resource found, then override it if we
662 * have a different offset and the previous was set by an ISA hole.
664 * - Some busses have IO space not starting at 0, which causes trouble with
665 * the way we do our IO resource renumbering. The code somewhat deals with
666 * it for 64 bits but I would expect problems on 32 bits.
668 * - Some 32 bits platforms such as 4xx can have physical space larger than
669 * 32 bits so we need to use 64 bits values for the parsing
671 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
672 struct device_node
*dev
,
677 int pna
= of_n_addr_cells(dev
);
679 int memno
= 0, isa_hole
= -1;
681 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
682 unsigned long long isa_mb
= 0;
683 struct resource
*res
;
685 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
686 dev
->full_name
, primary
? "(primary)" : "");
688 /* Get ranges property */
689 ranges
= of_get_property(dev
, "ranges", &rlen
);
694 while ((rlen
-= np
* 4) >= 0) {
695 /* Read next ranges element */
696 pci_space
= ranges
[0];
697 pci_addr
= of_read_number(ranges
+ 1, 2);
698 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
699 size
= of_read_number(ranges
+ pna
+ 3, 2);
702 /* If we failed translation or got a zero-sized region
703 * (some FW try to feed us with non sensical zero sized regions
704 * such as power3 which look like some kind of attempt at exposing
705 * the VGA memory hole)
707 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
710 /* Now consume following elements while they are contiguous */
711 for (; rlen
>= np
* sizeof(u32
);
712 ranges
+= np
, rlen
-= np
* 4) {
713 if (ranges
[0] != pci_space
)
715 pci_next
= of_read_number(ranges
+ 1, 2);
716 cpu_next
= of_translate_address(dev
, ranges
+ 3);
717 if (pci_next
!= pci_addr
+ size
||
718 cpu_next
!= cpu_addr
+ size
)
720 size
+= of_read_number(ranges
+ pna
+ 3, 2);
723 /* Act based on address space type */
725 switch ((pci_space
>> 24) & 0x3) {
726 case 1: /* PCI IO space */
728 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
729 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
731 /* We support only one IO range */
732 if (hose
->pci_io_size
) {
734 " \\--> Skipped (too many) !\n");
738 /* On 32 bits, limit I/O space to 16MB */
739 if (size
> 0x01000000)
742 /* 32 bits needs to map IOs here */
743 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
745 /* Expect trouble if pci_addr is not 0 */
748 (unsigned long)hose
->io_base_virt
;
749 #endif /* CONFIG_PPC32 */
750 /* pci_io_size and io_base_phys always represent IO
751 * space starting at 0 so we factor in pci_addr
753 hose
->pci_io_size
= pci_addr
+ size
;
754 hose
->io_base_phys
= cpu_addr
- pci_addr
;
757 res
= &hose
->io_resource
;
758 res
->flags
= IORESOURCE_IO
;
759 res
->start
= pci_addr
;
761 case 2: /* PCI Memory space */
762 case 3: /* PCI 64 bits Memory space */
764 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
765 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
766 (pci_space
& 0x40000000) ? "Prefetch" : "");
768 /* We support only 3 memory ranges */
771 " \\--> Skipped (too many) !\n");
774 /* Handles ISA memory hole space here */
778 if (primary
|| isa_mem_base
== 0)
779 isa_mem_base
= cpu_addr
;
780 hose
->isa_mem_phys
= cpu_addr
;
781 hose
->isa_mem_size
= size
;
784 /* We get the PCI/Mem offset from the first range or
785 * the, current one if the offset came from an ISA
786 * hole. If they don't match, bugger.
789 (isa_hole
>= 0 && pci_addr
!= 0 &&
790 hose
->pci_mem_offset
== isa_mb
))
791 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
792 else if (pci_addr
!= 0 &&
793 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
795 " \\--> Skipped (offset mismatch) !\n");
800 res
= &hose
->mem_resources
[memno
++];
801 res
->flags
= IORESOURCE_MEM
;
802 if (pci_space
& 0x40000000)
803 res
->flags
|= IORESOURCE_PREFETCH
;
804 res
->start
= cpu_addr
;
808 res
->name
= dev
->full_name
;
809 res
->end
= res
->start
+ size
- 1;
816 /* If there's an ISA hole and the pci_mem_offset is -not- matching
817 * the ISA hole offset, then we need to remove the ISA hole from
818 * the resource list for that brige
820 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
821 unsigned int next
= isa_hole
+ 1;
822 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
824 memmove(&hose
->mem_resources
[isa_hole
],
825 &hose
->mem_resources
[next
],
826 sizeof(struct resource
) * (memno
- next
));
827 hose
->mem_resources
[--memno
].flags
= 0;
831 /* Decide whether to display the domain number in /proc */
832 int pci_proc_domain(struct pci_bus
*bus
)
834 struct pci_controller
*hose
= pci_bus_to_host(bus
);
836 if (!(ppc_pci_flags
& PPC_PCI_ENABLE_PROC_DOMAINS
))
838 if (ppc_pci_flags
& PPC_PCI_COMPAT_DOMAIN_0
)
839 return hose
->global_number
!= 0;
843 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
844 struct resource
*res
)
846 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
847 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
851 if (res
->flags
& IORESOURCE_IO
) {
852 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
854 } else if (res
->flags
& IORESOURCE_MEM
)
855 offset
= hose
->pci_mem_offset
;
857 region
->start
= (res
->start
- offset
) & mask
;
858 region
->end
= (res
->end
- offset
) & mask
;
860 EXPORT_SYMBOL(pcibios_resource_to_bus
);
862 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
863 struct pci_bus_region
*region
)
865 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
866 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
870 if (res
->flags
& IORESOURCE_IO
) {
871 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
873 } else if (res
->flags
& IORESOURCE_MEM
)
874 offset
= hose
->pci_mem_offset
;
875 res
->start
= (region
->start
+ offset
) & mask
;
876 res
->end
= (region
->end
+ offset
) & mask
;
878 EXPORT_SYMBOL(pcibios_bus_to_resource
);
880 /* Fixup a bus resource into a linux resource */
881 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
883 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
884 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
886 if (res
->flags
& IORESOURCE_IO
) {
887 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
889 } else if (res
->flags
& IORESOURCE_MEM
)
890 offset
= hose
->pci_mem_offset
;
892 res
->start
= (res
->start
+ offset
) & mask
;
893 res
->end
= (res
->end
+ offset
) & mask
;
897 /* This header fixup will do the resource fixup for all devices as they are
898 * probed, but not for bridge ranges
900 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
902 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
906 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
910 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
911 struct resource
*res
= dev
->resource
+ i
;
914 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
915 * consider 0 as an unassigned BAR value. It's technically
916 * a valid value, but linux doesn't like it... so when we can
917 * re-assign things, we do so, but if we can't, we keep it
918 * around and hope for the best...
920 if (res
->start
== 0 && !(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
921 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
923 (unsigned long long)res
->start
,
924 (unsigned long long)res
->end
,
925 (unsigned int)res
->flags
);
926 res
->end
-= res
->start
;
928 res
->flags
|= IORESOURCE_UNSET
;
932 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
934 (unsigned long long)res
->start
,\
935 (unsigned long long)res
->end
,
936 (unsigned int)res
->flags
);
938 fixup_resource(res
, dev
);
940 pr_debug("PCI:%s %016llx-%016llx\n",
942 (unsigned long long)res
->start
,
943 (unsigned long long)res
->end
);
946 /* Call machine specific resource fixup */
947 if (ppc_md
.pcibios_fixup_resources
)
948 ppc_md
.pcibios_fixup_resources(dev
);
950 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
952 /* This function tries to figure out if a bridge resource has been initialized
953 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
954 * things go more smoothly when it gets it right. It should covers cases such
955 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
957 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
958 struct resource
*res
)
960 struct pci_controller
*hose
= pci_bus_to_host(bus
);
961 struct pci_dev
*dev
= bus
->self
;
962 resource_size_t offset
;
966 /* We don't do anything if PCI_PROBE_ONLY is set */
967 if (ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)
970 /* Job is a bit different between memory and IO */
971 if (res
->flags
& IORESOURCE_MEM
) {
972 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
973 * initialized by somebody
975 if (res
->start
!= hose
->pci_mem_offset
)
978 /* The BAR is 0, let's check if memory decoding is enabled on
979 * the bridge. If not, we consider it unassigned
981 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
982 if ((command
& PCI_COMMAND_MEMORY
) == 0)
985 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
986 * resources covers that starting address (0 then it's good enough for
989 for (i
= 0; i
< 3; i
++) {
990 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
991 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
995 /* Well, it starts at 0 and we know it will collide so we may as
996 * well consider it as unassigned. That covers the Apple case.
1000 /* If the BAR is non-0, then we consider it assigned */
1001 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1002 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
1005 /* Here, we are a bit different than memory as typically IO space
1006 * starting at low addresses -is- valid. What we do instead if that
1007 * we consider as unassigned anything that doesn't have IO enabled
1008 * in the PCI command register, and that's it.
1010 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1011 if (command
& PCI_COMMAND_IO
)
1014 /* It's starting at 0 and IO is disabled in the bridge, consider
1021 /* Fixup resources of a PCI<->PCI bridge */
1022 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1024 struct resource
*res
;
1027 struct pci_dev
*dev
= bus
->self
;
1029 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1030 if ((res
= bus
->resource
[i
]) == NULL
)
1034 if (i
>= 3 && bus
->self
->transparent
)
1037 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1039 (unsigned long long)res
->start
,\
1040 (unsigned long long)res
->end
,
1041 (unsigned int)res
->flags
);
1044 fixup_resource(res
, dev
);
1046 /* Try to detect uninitialized P2P bridge resources,
1047 * and clear them out so they get re-assigned later
1049 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1051 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
1054 pr_debug("PCI:%s %016llx-%016llx\n",
1056 (unsigned long long)res
->start
,
1057 (unsigned long long)res
->end
);
1062 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
1064 /* Fix up the bus resources for P2P bridges */
1065 if (bus
->self
!= NULL
)
1066 pcibios_fixup_bridge(bus
);
1068 /* Platform specific bus fixups. This is currently only used
1069 * by fsl_pci and I'm hoping to get rid of it at some point
1071 if (ppc_md
.pcibios_fixup_bus
)
1072 ppc_md
.pcibios_fixup_bus(bus
);
1074 /* Setup bus DMA mappings */
1075 if (ppc_md
.pci_dma_bus_setup
)
1076 ppc_md
.pci_dma_bus_setup(bus
);
1079 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1081 struct pci_dev
*dev
;
1083 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1084 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1086 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1087 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
1089 /* Setup OF node pointer in archdata */
1090 sd
->of_node
= pci_device_to_OF_node(dev
);
1092 /* Fixup NUMA node as it may not be setup yet by the generic
1093 * code and is needed by the DMA init
1095 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1097 /* Hook up default DMA ops */
1098 sd
->dma_ops
= pci_dma_ops
;
1099 sd
->dma_data
= (void *)PCI_DRAM_OFFSET
;
1101 /* Additional platform DMA/iommu setup */
1102 if (ppc_md
.pci_dma_dev_setup
)
1103 ppc_md
.pci_dma_dev_setup(dev
);
1105 /* Read default IRQs and fixup if necessary */
1106 pci_read_irq_line(dev
);
1107 if (ppc_md
.pci_irq_fixup
)
1108 ppc_md
.pci_irq_fixup(dev
);
1112 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1114 /* When called from the generic PCI probe, read PCI<->PCI bridge
1115 * bases. This is -not- called when generating the PCI tree from
1116 * the OF device-tree.
1118 if (bus
->self
!= NULL
)
1119 pci_read_bridge_bases(bus
);
1121 /* Now fixup the bus bus */
1122 pcibios_setup_bus_self(bus
);
1124 /* Now fixup devices on that bus */
1125 pcibios_setup_bus_devices(bus
);
1127 EXPORT_SYMBOL(pcibios_fixup_bus
);
1129 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1131 if ((ppc_pci_flags
& PPC_PCI_CAN_SKIP_ISA_ALIGN
) &&
1132 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1138 * We need to avoid collisions with `mirrored' VGA ports
1139 * and other strange ISA hardware, so we always want the
1140 * addresses to be allocated in the 0x000-0x0ff region
1143 * Why? Because some silly external IO cards only decode
1144 * the low 10 bits of the IO address. The 0x00-0xff region
1145 * is reserved for motherboard devices that decode all 16
1146 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1147 * but we want to try to avoid allocating at 0x2900-0x2bff
1148 * which might have be mirrored at 0x0100-0x03ff..
1150 void pcibios_align_resource(void *data
, struct resource
*res
,
1151 resource_size_t size
, resource_size_t align
)
1153 struct pci_dev
*dev
= data
;
1155 if (res
->flags
& IORESOURCE_IO
) {
1156 resource_size_t start
= res
->start
;
1158 if (skip_isa_ioresource_align(dev
))
1160 if (start
& 0x300) {
1161 start
= (start
+ 0x3ff) & ~0x3ff;
1166 EXPORT_SYMBOL(pcibios_align_resource
);
1169 * Reparent resource children of pr that conflict with res
1170 * under res, and make res replace those children.
1172 static int __init
reparent_resources(struct resource
*parent
,
1173 struct resource
*res
)
1175 struct resource
*p
, **pp
;
1176 struct resource
**firstpp
= NULL
;
1178 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1179 if (p
->end
< res
->start
)
1181 if (res
->end
< p
->start
)
1183 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1184 return -1; /* not completely contained */
1185 if (firstpp
== NULL
)
1188 if (firstpp
== NULL
)
1189 return -1; /* didn't find any conflicting entries? */
1190 res
->parent
= parent
;
1191 res
->child
= *firstpp
;
1195 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1197 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1199 (unsigned long long)p
->start
,
1200 (unsigned long long)p
->end
, res
->name
);
1206 * Handle resources of PCI devices. If the world were perfect, we could
1207 * just allocate all the resource regions and do nothing more. It isn't.
1208 * On the other hand, we cannot just re-allocate all devices, as it would
1209 * require us to know lots of host bridge internals. So we attempt to
1210 * keep as much of the original configuration as possible, but tweak it
1211 * when it's found to be wrong.
1213 * Known BIOS problems we have to work around:
1214 * - I/O or memory regions not configured
1215 * - regions configured, but not enabled in the command register
1216 * - bogus I/O addresses above 64K used
1217 * - expansion ROMs left enabled (this may sound harmless, but given
1218 * the fact the PCI specs explicitly allow address decoders to be
1219 * shared between expansion ROMs and other resource regions, it's
1220 * at least dangerous)
1223 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1224 * This gives us fixed barriers on where we can allocate.
1225 * (2) Allocate resources for all enabled devices. If there is
1226 * a collision, just mark the resource as unallocated. Also
1227 * disable expansion ROMs during this step.
1228 * (3) Try to allocate resources for disabled devices. If the
1229 * resources were assigned correctly, everything goes well,
1230 * if they weren't, they won't disturb allocation of other
1232 * (4) Assign new addresses to resources which were either
1233 * not configured at all or misconfigured. If explicitly
1234 * requested by the user, configure expansion ROM address
1238 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1242 struct resource
*res
, *pr
;
1244 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1245 pci_domain_nr(bus
), bus
->number
);
1247 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1248 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
1249 || res
->start
> res
->end
|| res
->parent
)
1251 if (bus
->parent
== NULL
)
1252 pr
= (res
->flags
& IORESOURCE_IO
) ?
1253 &ioport_resource
: &iomem_resource
;
1255 /* Don't bother with non-root busses when
1256 * re-assigning all resources. We clear the
1257 * resource flags as if they were colliding
1258 * and as such ensure proper re-allocation
1261 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)
1262 goto clear_resource
;
1263 pr
= pci_find_parent_resource(bus
->self
, res
);
1265 /* this happens when the generic PCI
1266 * code (wrongly) decides that this
1267 * bridge is transparent -- paulus
1273 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1274 "[0x%x], parent %p (%s)\n",
1275 bus
->self
? pci_name(bus
->self
) : "PHB",
1277 (unsigned long long)res
->start
,
1278 (unsigned long long)res
->end
,
1279 (unsigned int)res
->flags
,
1280 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1282 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1283 if (request_resource(pr
, res
) == 0)
1286 * Must be a conflict with an existing entry.
1287 * Move that entry (or entries) under the
1288 * bridge resource and try again.
1290 if (reparent_resources(pr
, res
) == 0)
1293 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1294 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1299 list_for_each_entry(b
, &bus
->children
, node
)
1300 pcibios_allocate_bus_resources(b
);
1303 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1305 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1307 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1309 (unsigned long long)r
->start
,
1310 (unsigned long long)r
->end
,
1311 (unsigned int)r
->flags
);
1313 pr
= pci_find_parent_resource(dev
, r
);
1314 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1315 request_resource(pr
, r
) < 0) {
1316 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1317 " of device %s, will remap\n", idx
, pci_name(dev
));
1319 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1321 (unsigned long long)pr
->start
,
1322 (unsigned long long)pr
->end
,
1323 (unsigned int)pr
->flags
);
1324 /* We'll assign a new address later */
1325 r
->flags
|= IORESOURCE_UNSET
;
1331 static void __init
pcibios_allocate_resources(int pass
)
1333 struct pci_dev
*dev
= NULL
;
1338 for_each_pci_dev(dev
) {
1339 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1340 for (idx
= 0; idx
< 6; idx
++) {
1341 r
= &dev
->resource
[idx
];
1342 if (r
->parent
) /* Already allocated */
1344 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1345 continue; /* Not assigned at all */
1346 if (r
->flags
& IORESOURCE_IO
)
1347 disabled
= !(command
& PCI_COMMAND_IO
);
1349 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1350 if (pass
== disabled
)
1351 alloc_resource(dev
, idx
);
1355 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1356 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
1357 /* Turn the ROM off, leave the resource region,
1358 * but keep it unregistered.
1361 pr_debug("PCI: Switching off ROM of %s\n",
1363 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1364 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1365 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1366 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1371 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1373 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1374 resource_size_t offset
;
1375 struct resource
*res
, *pres
;
1378 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus
));
1381 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1383 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1384 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1385 BUG_ON(res
== NULL
);
1386 res
->name
= "Legacy IO";
1387 res
->flags
= IORESOURCE_IO
;
1388 res
->start
= offset
;
1389 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1390 pr_debug("Candidate legacy IO: %pR\n", res
);
1391 if (request_resource(&hose
->io_resource
, res
)) {
1393 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1394 pci_domain_nr(bus
), bus
->number
, res
);
1399 /* Check for memory */
1400 offset
= hose
->pci_mem_offset
;
1401 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1402 for (i
= 0; i
< 3; i
++) {
1403 pres
= &hose
->mem_resources
[i
];
1404 if (!(pres
->flags
& IORESOURCE_MEM
))
1406 pr_debug("hose mem res: %pR\n", pres
);
1407 if ((pres
->start
- offset
) <= 0xa0000 &&
1408 (pres
->end
- offset
) >= 0xbffff)
1413 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1414 BUG_ON(res
== NULL
);
1415 res
->name
= "Legacy VGA memory";
1416 res
->flags
= IORESOURCE_MEM
;
1417 res
->start
= 0xa0000 + offset
;
1418 res
->end
= 0xbffff + offset
;
1419 pr_debug("Candidate VGA memory: %pR\n", res
);
1420 if (request_resource(pres
, res
)) {
1422 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1423 pci_domain_nr(bus
), bus
->number
, res
);
1428 void __init
pcibios_resource_survey(void)
1432 /* Allocate and assign resources. If we re-assign everything, then
1433 * we skip the allocate phase
1435 list_for_each_entry(b
, &pci_root_buses
, node
)
1436 pcibios_allocate_bus_resources(b
);
1438 if (!(ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)) {
1439 pcibios_allocate_resources(0);
1440 pcibios_allocate_resources(1);
1443 /* Before we start assigning unassigned resource, we try to reserve
1444 * the low IO area and the VGA memory area if they intersect the
1445 * bus available resources to avoid allocating things on top of them
1447 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1448 list_for_each_entry(b
, &pci_root_buses
, node
)
1449 pcibios_reserve_legacy_regions(b
);
1452 /* Now, if the platform didn't decide to blindly trust the firmware,
1453 * we proceed to assigning things that were left unassigned
1455 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1456 pr_debug("PCI: Assigning unassigned resouces...\n");
1457 pci_assign_unassigned_resources();
1460 /* Call machine dependent fixup */
1461 if (ppc_md
.pcibios_fixup
)
1462 ppc_md
.pcibios_fixup();
1465 #ifdef CONFIG_HOTPLUG
1467 /* This is used by the PCI hotplug driver to allocate resource
1468 * of newly plugged busses. We can try to consolidate with the
1469 * rest of the code later, for now, keep it as-is as our main
1470 * resource allocation function doesn't deal with sub-trees yet.
1472 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1474 struct pci_dev
*dev
;
1475 struct pci_bus
*child_bus
;
1477 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1480 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1481 struct resource
*r
= &dev
->resource
[i
];
1483 if (r
->parent
|| !r
->start
|| !r
->flags
)
1486 pr_debug("PCI: Claiming %s: "
1487 "Resource %d: %016llx..%016llx [%x]\n",
1489 (unsigned long long)r
->start
,
1490 (unsigned long long)r
->end
,
1491 (unsigned int)r
->flags
);
1493 pci_claim_resource(dev
, i
);
1497 list_for_each_entry(child_bus
, &bus
->children
, node
)
1498 pcibios_claim_one_bus(child_bus
);
1500 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1503 /* pcibios_finish_adding_to_bus
1505 * This is to be called by the hotplug code after devices have been
1506 * added to a bus, this include calling it for a PHB that is just
1509 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1511 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1512 pci_domain_nr(bus
), bus
->number
);
1514 /* Allocate bus and devices resources */
1515 pcibios_allocate_bus_resources(bus
);
1516 pcibios_claim_one_bus(bus
);
1518 /* Add new devices to global lists. Register in proc, sysfs. */
1519 pci_bus_add_devices(bus
);
1522 eeh_add_device_tree_late(bus
);
1524 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1526 #endif /* CONFIG_HOTPLUG */
1528 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1530 if (ppc_md
.pcibios_enable_device_hook
)
1531 if (ppc_md
.pcibios_enable_device_hook(dev
))
1534 return pci_enable_resources(dev
, mask
);
1537 void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
)
1539 struct pci_bus
*bus
= hose
->bus
;
1540 struct resource
*res
;
1543 /* Hookup PHB IO resource */
1544 bus
->resource
[0] = res
= &hose
->io_resource
;
1547 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1548 " bridge %s (domain %d)\n",
1549 hose
->dn
->full_name
, hose
->global_number
);
1551 /* Workaround for lack of IO resource only on 32-bit */
1552 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1553 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1554 res
->flags
= IORESOURCE_IO
;
1555 #endif /* CONFIG_PPC32 */
1558 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1559 (unsigned long long)res
->start
,
1560 (unsigned long long)res
->end
,
1561 (unsigned long)res
->flags
);
1563 /* Hookup PHB Memory resources */
1564 for (i
= 0; i
< 3; ++i
) {
1565 res
= &hose
->mem_resources
[i
];
1569 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1570 "host bridge %s (domain %d)\n",
1571 hose
->dn
->full_name
, hose
->global_number
);
1573 /* Workaround for lack of MEM resource only on 32-bit */
1574 res
->start
= hose
->pci_mem_offset
;
1575 res
->end
= (resource_size_t
)-1LL;
1576 res
->flags
= IORESOURCE_MEM
;
1577 #endif /* CONFIG_PPC32 */
1579 bus
->resource
[i
+1] = res
;
1581 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i
,
1582 (unsigned long long)res
->start
,
1583 (unsigned long long)res
->end
,
1584 (unsigned long)res
->flags
);
1587 pr_debug("PCI: PHB MEM offset = %016llx\n",
1588 (unsigned long long)hose
->pci_mem_offset
);
1589 pr_debug("PCI: PHB IO offset = %08lx\n",
1590 (unsigned long)hose
->io_base_virt
- _IO_BASE
);