2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
30 #include <asm/processor.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/byteorder.h>
35 #include <asm/machdep.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/firmware.h>
40 static DEFINE_SPINLOCK(hose_spinlock
);
42 /* XXX kill that some day ... */
43 static int global_phb_number
; /* Global phb counter */
45 /* ISA Memory physical address */
46 resource_size_t isa_mem_base
;
48 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
49 unsigned int ppc_pci_flags
= 0;
52 static struct dma_mapping_ops
*pci_dma_ops
;
54 void set_pci_dma_ops(struct dma_mapping_ops
*dma_ops
)
56 pci_dma_ops
= dma_ops
;
59 struct dma_mapping_ops
*get_pci_dma_ops(void)
63 EXPORT_SYMBOL(get_pci_dma_ops
);
65 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
67 return dma_set_mask(&dev
->dev
, mask
);
70 int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
74 rc
= dma_set_mask(&dev
->dev
, mask
);
75 dev
->dev
.coherent_dma_mask
= dev
->dma_mask
;
80 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
82 struct pci_controller
*phb
;
84 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
87 spin_lock(&hose_spinlock
);
88 phb
->global_number
= global_phb_number
++;
89 list_add_tail(&phb
->list_node
, &hose_list
);
90 spin_unlock(&hose_spinlock
);
92 phb
->is_dynamic
= mem_init_done
;
95 int nid
= of_node_to_nid(dev
);
97 if (nid
< 0 || !node_online(nid
))
100 PHB_SET_NODE(phb
, nid
);
106 void pcibios_free_controller(struct pci_controller
*phb
)
108 spin_lock(&hose_spinlock
);
109 list_del(&phb
->list_node
);
110 spin_unlock(&hose_spinlock
);
116 int pcibios_vaddr_is_ioport(void __iomem
*address
)
119 struct pci_controller
*hose
;
122 spin_lock(&hose_spinlock
);
123 list_for_each_entry(hose
, &hose_list
, list_node
) {
125 size
= hose
->pci_io_size
;
127 size
= hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
129 if (address
>= hose
->io_base_virt
&&
130 address
< (hose
->io_base_virt
+ size
)) {
135 spin_unlock(&hose_spinlock
);
140 * Return the domain number for this bus.
142 int pci_domain_nr(struct pci_bus
*bus
)
144 struct pci_controller
*hose
= pci_bus_to_host(bus
);
146 return hose
->global_number
;
148 EXPORT_SYMBOL(pci_domain_nr
);
152 /* This routine is meant to be used early during boot, when the
153 * PCI bus numbers have not yet been assigned, and you need to
154 * issue PCI config cycles to an OF device.
155 * It could also be used to "fix" RTAS config cycles if you want
156 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
159 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
162 struct pci_controller
*hose
, *tmp
;
163 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
164 if (hose
->dn
== node
)
171 static ssize_t
pci_show_devspec(struct device
*dev
,
172 struct device_attribute
*attr
, char *buf
)
174 struct pci_dev
*pdev
;
175 struct device_node
*np
;
177 pdev
= to_pci_dev (dev
);
178 np
= pci_device_to_OF_node(pdev
);
179 if (np
== NULL
|| np
->full_name
== NULL
)
181 return sprintf(buf
, "%s", np
->full_name
);
183 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
184 #endif /* CONFIG_PPC_OF */
186 /* Add sysfs properties */
187 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
190 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
193 #endif /* CONFIG_PPC_OF */
197 char __devinit
*pcibios_setup(char *str
)
203 * Reads the interrupt pin to determine if interrupt is use by card.
204 * If the interrupt is used, then gets the interrupt line from the
205 * openfirmware and sets it in the pci_dev and pci_config line.
207 int pci_read_irq_line(struct pci_dev
*pci_dev
)
212 /* The current device-tree that iSeries generates from the HV
213 * PCI informations doesn't contain proper interrupt routing,
214 * and all the fallback would do is print out crap, so we
215 * don't attempt to resolve the interrupts here at all, some
216 * iSeries specific fixup does it.
218 * In the long run, we will hopefully fix the generated device-tree
221 #ifdef CONFIG_PPC_ISERIES
222 if (firmware_has_feature(FW_FEATURE_ISERIES
))
226 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
229 memset(&oirq
, 0xff, sizeof(oirq
));
231 /* Try to get a mapping from the device-tree */
232 if (of_irq_map_pci(pci_dev
, &oirq
)) {
235 /* If that fails, lets fallback to what is in the config
236 * space and map that through the default controller. We
237 * also set the type to level low since that's what PCI
238 * interrupts are. If your platform does differently, then
239 * either provide a proper interrupt tree or don't use this
242 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
246 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
247 line
== 0xff || line
== 0) {
250 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
253 virq
= irq_create_mapping(NULL
, line
);
255 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
257 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
258 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
259 oirq
.controller
? oirq
.controller
->full_name
:
262 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
266 pr_debug(" Failed to map !\n");
270 pr_debug(" Mapped to linux irq %d\n", virq
);
276 EXPORT_SYMBOL(pci_read_irq_line
);
279 * Platform support for /proc/bus/pci/X/Y mmap()s,
280 * modelled on the sparc64 implementation by Dave Miller.
285 * Adjust vm_pgoff of VMA such that it is the physical page offset
286 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
288 * Basically, the user finds the base address for his device which he wishes
289 * to mmap. They read the 32-bit value from the config space base register,
290 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
291 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
293 * Returns negative error code on failure, zero on success.
295 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
296 resource_size_t
*offset
,
297 enum pci_mmap_state mmap_state
)
299 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
300 unsigned long io_offset
= 0;
304 return NULL
; /* should never happen */
306 /* If memory, add on the PCI bridge address offset */
307 if (mmap_state
== pci_mmap_mem
) {
308 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
309 *offset
+= hose
->pci_mem_offset
;
311 res_bit
= IORESOURCE_MEM
;
313 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
314 *offset
+= io_offset
;
315 res_bit
= IORESOURCE_IO
;
319 * Check that the offset requested corresponds to one of the
320 * resources of the device.
322 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
323 struct resource
*rp
= &dev
->resource
[i
];
324 int flags
= rp
->flags
;
326 /* treat ROM as memory (should be already) */
327 if (i
== PCI_ROM_RESOURCE
)
328 flags
|= IORESOURCE_MEM
;
330 /* Active and same type? */
331 if ((flags
& res_bit
) == 0)
334 /* In the range of this resource? */
335 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
338 /* found it! construct the final physical address */
339 if (mmap_state
== pci_mmap_io
)
340 *offset
+= hose
->io_base_phys
- io_offset
;
348 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
351 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
353 enum pci_mmap_state mmap_state
,
356 unsigned long prot
= pgprot_val(protection
);
358 /* Write combine is always 0 on non-memory space mappings. On
359 * memory space, if the user didn't pass 1, we check for a
360 * "prefetchable" resource. This is a bit hackish, but we use
361 * this to workaround the inability of /sysfs to provide a write
364 if (mmap_state
!= pci_mmap_mem
)
366 else if (write_combine
== 0) {
367 if (rp
->flags
& IORESOURCE_PREFETCH
)
371 /* XXX would be nice to have a way to ask for write-through */
373 return pgprot_noncached_wc(prot
);
375 return pgprot_noncached(prot
);
379 * This one is used by /dev/mem and fbdev who have no clue about the
380 * PCI device, it tries to find the PCI device first and calls the
383 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
388 struct pci_dev
*pdev
= NULL
;
389 struct resource
*found
= NULL
;
390 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
393 if (page_is_ram(pfn
))
396 prot
= pgprot_noncached(prot
);
397 for_each_pci_dev(pdev
) {
398 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
399 struct resource
*rp
= &pdev
->resource
[i
];
400 int flags
= rp
->flags
;
402 /* Active and same type? */
403 if ((flags
& IORESOURCE_MEM
) == 0)
405 /* In the range of this resource? */
406 if (offset
< (rp
->start
& PAGE_MASK
) ||
416 if (found
->flags
& IORESOURCE_PREFETCH
)
417 prot
= pgprot_noncached_wc(prot
);
421 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
422 (unsigned long long)offset
, pgprot_val(prot
));
429 * Perform the actual remap of the pages for a PCI device mapping, as
430 * appropriate for this architecture. The region in the process to map
431 * is described by vm_start and vm_end members of VMA, the base physical
432 * address is found in vm_pgoff.
433 * The pci device structure is provided so that architectures may make mapping
434 * decisions on a per-device or per-bus basis.
436 * Returns a negative error code on failure, zero on success.
438 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
439 enum pci_mmap_state mmap_state
, int write_combine
)
441 resource_size_t offset
=
442 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
446 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
450 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
451 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
453 mmap_state
, write_combine
);
455 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
456 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
461 /* This provides legacy IO read access on a bus */
462 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
464 unsigned long offset
;
465 struct pci_controller
*hose
= pci_bus_to_host(bus
);
466 struct resource
*rp
= &hose
->io_resource
;
469 /* Check if port can be supported by that bus. We only check
470 * the ranges of the PHB though, not the bus itself as the rules
471 * for forwarding legacy cycles down bridges are not our problem
472 * here. So if the host bridge supports it, we do it.
474 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
477 if (!(rp
->flags
& IORESOURCE_IO
))
479 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
481 addr
= hose
->io_base_virt
+ port
;
485 *((u8
*)val
) = in_8(addr
);
490 *((u16
*)val
) = in_le16(addr
);
495 *((u32
*)val
) = in_le32(addr
);
501 /* This provides legacy IO write access on a bus */
502 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
504 unsigned long offset
;
505 struct pci_controller
*hose
= pci_bus_to_host(bus
);
506 struct resource
*rp
= &hose
->io_resource
;
509 /* Check if port can be supported by that bus. We only check
510 * the ranges of the PHB though, not the bus itself as the rules
511 * for forwarding legacy cycles down bridges are not our problem
512 * here. So if the host bridge supports it, we do it.
514 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
517 if (!(rp
->flags
& IORESOURCE_IO
))
519 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
521 addr
= hose
->io_base_virt
+ port
;
523 /* WARNING: The generic code is idiotic. It gets passed a pointer
524 * to what can be a 1, 2 or 4 byte quantity and always reads that
525 * as a u32, which means that we have to correct the location of
526 * the data read within those 32 bits for size 1 and 2
530 out_8(addr
, val
>> 24);
535 out_le16(addr
, val
>> 16);
546 /* This provides legacy IO or memory mmap access on a bus */
547 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
548 struct vm_area_struct
*vma
,
549 enum pci_mmap_state mmap_state
)
551 struct pci_controller
*hose
= pci_bus_to_host(bus
);
552 resource_size_t offset
=
553 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
554 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
557 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
558 pci_domain_nr(bus
), bus
->number
,
559 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
560 (unsigned long long)offset
,
561 (unsigned long long)(offset
+ size
- 1));
563 if (mmap_state
== pci_mmap_mem
) {
564 if ((offset
+ size
) > hose
->isa_mem_size
)
566 offset
+= hose
->isa_mem_phys
;
568 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
569 unsigned long roffset
= offset
+ io_offset
;
570 rp
= &hose
->io_resource
;
571 if (!(rp
->flags
& IORESOURCE_IO
))
573 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
575 offset
+= hose
->io_base_phys
;
577 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
579 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
580 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
581 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
582 vma
->vm_end
- vma
->vm_start
,
586 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
587 const struct resource
*rsrc
,
588 resource_size_t
*start
, resource_size_t
*end
)
590 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
591 resource_size_t offset
= 0;
596 if (rsrc
->flags
& IORESOURCE_IO
)
597 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
599 /* We pass a fully fixed up address to userland for MMIO instead of
600 * a BAR value because X is lame and expects to be able to use that
601 * to pass to /dev/mem !
603 * That means that we'll have potentially 64 bits values where some
604 * userland apps only expect 32 (like X itself since it thinks only
605 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
608 * Hopefully, the sysfs insterface is immune to that gunk. Once X
609 * has been fixed (and the fix spread enough), we can re-enable the
610 * 2 lines below and pass down a BAR value to userland. In that case
611 * we'll also have to re-enable the matching code in
612 * __pci_mmap_make_offset().
617 else if (rsrc
->flags
& IORESOURCE_MEM
)
618 offset
= hose
->pci_mem_offset
;
621 *start
= rsrc
->start
- offset
;
622 *end
= rsrc
->end
- offset
;
626 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
627 * @hose: newly allocated pci_controller to be setup
628 * @dev: device node of the host bridge
629 * @primary: set if primary bus (32 bits only, soon to be deprecated)
631 * This function will parse the "ranges" property of a PCI host bridge device
632 * node and setup the resource mapping of a pci controller based on its
635 * Life would be boring if it wasn't for a few issues that we have to deal
638 * - We can only cope with one IO space range and up to 3 Memory space
639 * ranges. However, some machines (thanks Apple !) tend to split their
640 * space into lots of small contiguous ranges. So we have to coalesce.
642 * - We can only cope with all memory ranges having the same offset
643 * between CPU addresses and PCI addresses. Unfortunately, some bridges
644 * are setup for a large 1:1 mapping along with a small "window" which
645 * maps PCI address 0 to some arbitrary high address of the CPU space in
646 * order to give access to the ISA memory hole.
647 * The way out of here that I've chosen for now is to always set the
648 * offset based on the first resource found, then override it if we
649 * have a different offset and the previous was set by an ISA hole.
651 * - Some busses have IO space not starting at 0, which causes trouble with
652 * the way we do our IO resource renumbering. The code somewhat deals with
653 * it for 64 bits but I would expect problems on 32 bits.
655 * - Some 32 bits platforms such as 4xx can have physical space larger than
656 * 32 bits so we need to use 64 bits values for the parsing
658 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
659 struct device_node
*dev
,
664 int pna
= of_n_addr_cells(dev
);
666 int memno
= 0, isa_hole
= -1;
668 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
669 unsigned long long isa_mb
= 0;
670 struct resource
*res
;
672 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
673 dev
->full_name
, primary
? "(primary)" : "");
675 /* Get ranges property */
676 ranges
= of_get_property(dev
, "ranges", &rlen
);
681 while ((rlen
-= np
* 4) >= 0) {
682 /* Read next ranges element */
683 pci_space
= ranges
[0];
684 pci_addr
= of_read_number(ranges
+ 1, 2);
685 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
686 size
= of_read_number(ranges
+ pna
+ 3, 2);
689 /* If we failed translation or got a zero-sized region
690 * (some FW try to feed us with non sensical zero sized regions
691 * such as power3 which look like some kind of attempt at exposing
692 * the VGA memory hole)
694 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
697 /* Now consume following elements while they are contiguous */
698 for (; rlen
>= np
* sizeof(u32
);
699 ranges
+= np
, rlen
-= np
* 4) {
700 if (ranges
[0] != pci_space
)
702 pci_next
= of_read_number(ranges
+ 1, 2);
703 cpu_next
= of_translate_address(dev
, ranges
+ 3);
704 if (pci_next
!= pci_addr
+ size
||
705 cpu_next
!= cpu_addr
+ size
)
707 size
+= of_read_number(ranges
+ pna
+ 3, 2);
710 /* Act based on address space type */
712 switch ((pci_space
>> 24) & 0x3) {
713 case 1: /* PCI IO space */
715 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
716 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
718 /* We support only one IO range */
719 if (hose
->pci_io_size
) {
721 " \\--> Skipped (too many) !\n");
725 /* On 32 bits, limit I/O space to 16MB */
726 if (size
> 0x01000000)
729 /* 32 bits needs to map IOs here */
730 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
732 /* Expect trouble if pci_addr is not 0 */
735 (unsigned long)hose
->io_base_virt
;
736 #endif /* CONFIG_PPC32 */
737 /* pci_io_size and io_base_phys always represent IO
738 * space starting at 0 so we factor in pci_addr
740 hose
->pci_io_size
= pci_addr
+ size
;
741 hose
->io_base_phys
= cpu_addr
- pci_addr
;
744 res
= &hose
->io_resource
;
745 res
->flags
= IORESOURCE_IO
;
746 res
->start
= pci_addr
;
748 case 2: /* PCI Memory space */
749 case 3: /* PCI 64 bits Memory space */
751 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
752 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
753 (pci_space
& 0x40000000) ? "Prefetch" : "");
755 /* We support only 3 memory ranges */
758 " \\--> Skipped (too many) !\n");
761 /* Handles ISA memory hole space here */
765 if (primary
|| isa_mem_base
== 0)
766 isa_mem_base
= cpu_addr
;
767 hose
->isa_mem_phys
= cpu_addr
;
768 hose
->isa_mem_size
= size
;
771 /* We get the PCI/Mem offset from the first range or
772 * the, current one if the offset came from an ISA
773 * hole. If they don't match, bugger.
776 (isa_hole
>= 0 && pci_addr
!= 0 &&
777 hose
->pci_mem_offset
== isa_mb
))
778 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
779 else if (pci_addr
!= 0 &&
780 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
782 " \\--> Skipped (offset mismatch) !\n");
787 res
= &hose
->mem_resources
[memno
++];
788 res
->flags
= IORESOURCE_MEM
;
789 if (pci_space
& 0x40000000)
790 res
->flags
|= IORESOURCE_PREFETCH
;
791 res
->start
= cpu_addr
;
795 res
->name
= dev
->full_name
;
796 res
->end
= res
->start
+ size
- 1;
803 /* If there's an ISA hole and the pci_mem_offset is -not- matching
804 * the ISA hole offset, then we need to remove the ISA hole from
805 * the resource list for that brige
807 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
808 unsigned int next
= isa_hole
+ 1;
809 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
811 memmove(&hose
->mem_resources
[isa_hole
],
812 &hose
->mem_resources
[next
],
813 sizeof(struct resource
) * (memno
- next
));
814 hose
->mem_resources
[--memno
].flags
= 0;
818 /* Decide whether to display the domain number in /proc */
819 int pci_proc_domain(struct pci_bus
*bus
)
821 struct pci_controller
*hose
= pci_bus_to_host(bus
);
823 if (!(ppc_pci_flags
& PPC_PCI_ENABLE_PROC_DOMAINS
))
825 if (ppc_pci_flags
& PPC_PCI_COMPAT_DOMAIN_0
)
826 return hose
->global_number
!= 0;
830 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
831 struct resource
*res
)
833 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
834 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
838 if (res
->flags
& IORESOURCE_IO
) {
839 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
841 } else if (res
->flags
& IORESOURCE_MEM
)
842 offset
= hose
->pci_mem_offset
;
844 region
->start
= (res
->start
- offset
) & mask
;
845 region
->end
= (res
->end
- offset
) & mask
;
847 EXPORT_SYMBOL(pcibios_resource_to_bus
);
849 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
850 struct pci_bus_region
*region
)
852 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
853 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
857 if (res
->flags
& IORESOURCE_IO
) {
858 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
860 } else if (res
->flags
& IORESOURCE_MEM
)
861 offset
= hose
->pci_mem_offset
;
862 res
->start
= (region
->start
+ offset
) & mask
;
863 res
->end
= (region
->end
+ offset
) & mask
;
865 EXPORT_SYMBOL(pcibios_bus_to_resource
);
867 /* Fixup a bus resource into a linux resource */
868 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
870 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
871 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
873 if (res
->flags
& IORESOURCE_IO
) {
874 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
876 } else if (res
->flags
& IORESOURCE_MEM
)
877 offset
= hose
->pci_mem_offset
;
879 res
->start
= (res
->start
+ offset
) & mask
;
880 res
->end
= (res
->end
+ offset
) & mask
;
884 /* This header fixup will do the resource fixup for all devices as they are
885 * probed, but not for bridge ranges
887 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
889 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
893 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
897 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
898 struct resource
*res
= dev
->resource
+ i
;
901 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
902 * consider 0 as an unassigned BAR value. It's technically
903 * a valid value, but linux doesn't like it... so when we can
904 * re-assign things, we do so, but if we can't, we keep it
905 * around and hope for the best...
907 if (res
->start
== 0 && !(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
908 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
910 (unsigned long long)res
->start
,
911 (unsigned long long)res
->end
,
912 (unsigned int)res
->flags
);
913 res
->end
-= res
->start
;
915 res
->flags
|= IORESOURCE_UNSET
;
919 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
921 (unsigned long long)res
->start
,\
922 (unsigned long long)res
->end
,
923 (unsigned int)res
->flags
);
925 fixup_resource(res
, dev
);
927 pr_debug("PCI:%s %016llx-%016llx\n",
929 (unsigned long long)res
->start
,
930 (unsigned long long)res
->end
);
933 /* Call machine specific resource fixup */
934 if (ppc_md
.pcibios_fixup_resources
)
935 ppc_md
.pcibios_fixup_resources(dev
);
937 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
939 /* This function tries to figure out if a bridge resource has been initialized
940 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
941 * things go more smoothly when it gets it right. It should covers cases such
942 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
944 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
945 struct resource
*res
)
947 struct pci_controller
*hose
= pci_bus_to_host(bus
);
948 struct pci_dev
*dev
= bus
->self
;
949 resource_size_t offset
;
953 /* We don't do anything if PCI_PROBE_ONLY is set */
954 if (ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)
957 /* Job is a bit different between memory and IO */
958 if (res
->flags
& IORESOURCE_MEM
) {
959 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
960 * initialized by somebody
962 if (res
->start
!= hose
->pci_mem_offset
)
965 /* The BAR is 0, let's check if memory decoding is enabled on
966 * the bridge. If not, we consider it unassigned
968 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
969 if ((command
& PCI_COMMAND_MEMORY
) == 0)
972 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
973 * resources covers that starting address (0 then it's good enough for
976 for (i
= 0; i
< 3; i
++) {
977 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
978 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
982 /* Well, it starts at 0 and we know it will collide so we may as
983 * well consider it as unassigned. That covers the Apple case.
987 /* If the BAR is non-0, then we consider it assigned */
988 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
989 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
992 /* Here, we are a bit different than memory as typically IO space
993 * starting at low addresses -is- valid. What we do instead if that
994 * we consider as unassigned anything that doesn't have IO enabled
995 * in the PCI command register, and that's it.
997 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
998 if (command
& PCI_COMMAND_IO
)
1001 /* It's starting at 0 and IO is disabled in the bridge, consider
1008 /* Fixup resources of a PCI<->PCI bridge */
1009 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1011 struct resource
*res
;
1014 struct pci_dev
*dev
= bus
->self
;
1016 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1017 if ((res
= bus
->resource
[i
]) == NULL
)
1021 if (i
>= 3 && bus
->self
->transparent
)
1024 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1026 (unsigned long long)res
->start
,\
1027 (unsigned long long)res
->end
,
1028 (unsigned int)res
->flags
);
1031 fixup_resource(res
, dev
);
1033 /* Try to detect uninitialized P2P bridge resources,
1034 * and clear them out so they get re-assigned later
1036 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1038 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
1041 pr_debug("PCI:%s %016llx-%016llx\n",
1043 (unsigned long long)res
->start
,
1044 (unsigned long long)res
->end
);
1049 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
1051 /* Fix up the bus resources for P2P bridges */
1052 if (bus
->self
!= NULL
)
1053 pcibios_fixup_bridge(bus
);
1055 /* Platform specific bus fixups. This is currently only used
1056 * by fsl_pci and I'm hoping to get rid of it at some point
1058 if (ppc_md
.pcibios_fixup_bus
)
1059 ppc_md
.pcibios_fixup_bus(bus
);
1061 /* Setup bus DMA mappings */
1062 if (ppc_md
.pci_dma_bus_setup
)
1063 ppc_md
.pci_dma_bus_setup(bus
);
1066 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1068 struct pci_dev
*dev
;
1070 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1071 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1073 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1074 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
1076 /* Setup OF node pointer in archdata */
1077 sd
->of_node
= pci_device_to_OF_node(dev
);
1079 /* Fixup NUMA node as it may not be setup yet by the generic
1080 * code and is needed by the DMA init
1082 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1084 /* Hook up default DMA ops */
1085 sd
->dma_ops
= pci_dma_ops
;
1086 sd
->dma_data
= (void *)PCI_DRAM_OFFSET
;
1088 /* Additional platform DMA/iommu setup */
1089 if (ppc_md
.pci_dma_dev_setup
)
1090 ppc_md
.pci_dma_dev_setup(dev
);
1092 /* Read default IRQs and fixup if necessary */
1093 pci_read_irq_line(dev
);
1094 if (ppc_md
.pci_irq_fixup
)
1095 ppc_md
.pci_irq_fixup(dev
);
1099 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1101 /* When called from the generic PCI probe, read PCI<->PCI bridge
1102 * bases. This is -not- called when generating the PCI tree from
1103 * the OF device-tree.
1105 if (bus
->self
!= NULL
)
1106 pci_read_bridge_bases(bus
);
1108 /* Now fixup the bus bus */
1109 pcibios_setup_bus_self(bus
);
1111 /* Now fixup devices on that bus */
1112 pcibios_setup_bus_devices(bus
);
1114 EXPORT_SYMBOL(pcibios_fixup_bus
);
1116 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1118 if ((ppc_pci_flags
& PPC_PCI_CAN_SKIP_ISA_ALIGN
) &&
1119 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1125 * We need to avoid collisions with `mirrored' VGA ports
1126 * and other strange ISA hardware, so we always want the
1127 * addresses to be allocated in the 0x000-0x0ff region
1130 * Why? Because some silly external IO cards only decode
1131 * the low 10 bits of the IO address. The 0x00-0xff region
1132 * is reserved for motherboard devices that decode all 16
1133 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1134 * but we want to try to avoid allocating at 0x2900-0x2bff
1135 * which might have be mirrored at 0x0100-0x03ff..
1137 void pcibios_align_resource(void *data
, struct resource
*res
,
1138 resource_size_t size
, resource_size_t align
)
1140 struct pci_dev
*dev
= data
;
1142 if (res
->flags
& IORESOURCE_IO
) {
1143 resource_size_t start
= res
->start
;
1145 if (skip_isa_ioresource_align(dev
))
1147 if (start
& 0x300) {
1148 start
= (start
+ 0x3ff) & ~0x3ff;
1153 EXPORT_SYMBOL(pcibios_align_resource
);
1156 * Reparent resource children of pr that conflict with res
1157 * under res, and make res replace those children.
1159 static int __init
reparent_resources(struct resource
*parent
,
1160 struct resource
*res
)
1162 struct resource
*p
, **pp
;
1163 struct resource
**firstpp
= NULL
;
1165 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1166 if (p
->end
< res
->start
)
1168 if (res
->end
< p
->start
)
1170 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1171 return -1; /* not completely contained */
1172 if (firstpp
== NULL
)
1175 if (firstpp
== NULL
)
1176 return -1; /* didn't find any conflicting entries? */
1177 res
->parent
= parent
;
1178 res
->child
= *firstpp
;
1182 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1184 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1186 (unsigned long long)p
->start
,
1187 (unsigned long long)p
->end
, res
->name
);
1193 * Handle resources of PCI devices. If the world were perfect, we could
1194 * just allocate all the resource regions and do nothing more. It isn't.
1195 * On the other hand, we cannot just re-allocate all devices, as it would
1196 * require us to know lots of host bridge internals. So we attempt to
1197 * keep as much of the original configuration as possible, but tweak it
1198 * when it's found to be wrong.
1200 * Known BIOS problems we have to work around:
1201 * - I/O or memory regions not configured
1202 * - regions configured, but not enabled in the command register
1203 * - bogus I/O addresses above 64K used
1204 * - expansion ROMs left enabled (this may sound harmless, but given
1205 * the fact the PCI specs explicitly allow address decoders to be
1206 * shared between expansion ROMs and other resource regions, it's
1207 * at least dangerous)
1210 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1211 * This gives us fixed barriers on where we can allocate.
1212 * (2) Allocate resources for all enabled devices. If there is
1213 * a collision, just mark the resource as unallocated. Also
1214 * disable expansion ROMs during this step.
1215 * (3) Try to allocate resources for disabled devices. If the
1216 * resources were assigned correctly, everything goes well,
1217 * if they weren't, they won't disturb allocation of other
1219 * (4) Assign new addresses to resources which were either
1220 * not configured at all or misconfigured. If explicitly
1221 * requested by the user, configure expansion ROM address
1225 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1229 struct resource
*res
, *pr
;
1231 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1232 pci_domain_nr(bus
), bus
->number
);
1234 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1235 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
1236 || res
->start
> res
->end
|| res
->parent
)
1238 if (bus
->parent
== NULL
)
1239 pr
= (res
->flags
& IORESOURCE_IO
) ?
1240 &ioport_resource
: &iomem_resource
;
1242 /* Don't bother with non-root busses when
1243 * re-assigning all resources. We clear the
1244 * resource flags as if they were colliding
1245 * and as such ensure proper re-allocation
1248 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)
1249 goto clear_resource
;
1250 pr
= pci_find_parent_resource(bus
->self
, res
);
1252 /* this happens when the generic PCI
1253 * code (wrongly) decides that this
1254 * bridge is transparent -- paulus
1260 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1261 "[0x%x], parent %p (%s)\n",
1262 bus
->self
? pci_name(bus
->self
) : "PHB",
1264 (unsigned long long)res
->start
,
1265 (unsigned long long)res
->end
,
1266 (unsigned int)res
->flags
,
1267 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1269 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1270 if (request_resource(pr
, res
) == 0)
1273 * Must be a conflict with an existing entry.
1274 * Move that entry (or entries) under the
1275 * bridge resource and try again.
1277 if (reparent_resources(pr
, res
) == 0)
1280 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1281 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1286 list_for_each_entry(b
, &bus
->children
, node
)
1287 pcibios_allocate_bus_resources(b
);
1290 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1292 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1294 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1296 (unsigned long long)r
->start
,
1297 (unsigned long long)r
->end
,
1298 (unsigned int)r
->flags
);
1300 pr
= pci_find_parent_resource(dev
, r
);
1301 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1302 request_resource(pr
, r
) < 0) {
1303 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1304 " of device %s, will remap\n", idx
, pci_name(dev
));
1306 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1308 (unsigned long long)pr
->start
,
1309 (unsigned long long)pr
->end
,
1310 (unsigned int)pr
->flags
);
1311 /* We'll assign a new address later */
1312 r
->flags
|= IORESOURCE_UNSET
;
1318 static void __init
pcibios_allocate_resources(int pass
)
1320 struct pci_dev
*dev
= NULL
;
1325 for_each_pci_dev(dev
) {
1326 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1327 for (idx
= 0; idx
< 6; idx
++) {
1328 r
= &dev
->resource
[idx
];
1329 if (r
->parent
) /* Already allocated */
1331 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1332 continue; /* Not assigned at all */
1333 if (r
->flags
& IORESOURCE_IO
)
1334 disabled
= !(command
& PCI_COMMAND_IO
);
1336 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1337 if (pass
== disabled
)
1338 alloc_resource(dev
, idx
);
1342 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1343 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
1344 /* Turn the ROM off, leave the resource region,
1345 * but keep it unregistered.
1348 pr_debug("PCI: Switching off ROM of %s\n",
1350 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1351 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1352 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1353 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1358 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1360 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1361 resource_size_t offset
;
1362 struct resource
*res
, *pres
;
1365 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus
));
1368 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1370 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1371 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1372 BUG_ON(res
== NULL
);
1373 res
->name
= "Legacy IO";
1374 res
->flags
= IORESOURCE_IO
;
1375 res
->start
= offset
;
1376 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1377 pr_debug("Candidate legacy IO: %pR\n", res
);
1378 if (request_resource(&hose
->io_resource
, res
)) {
1380 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1381 pci_domain_nr(bus
), bus
->number
, res
);
1386 /* Check for memory */
1387 offset
= hose
->pci_mem_offset
;
1388 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1389 for (i
= 0; i
< 3; i
++) {
1390 pres
= &hose
->mem_resources
[i
];
1391 if (!(pres
->flags
& IORESOURCE_MEM
))
1393 pr_debug("hose mem res: %pR\n", pres
);
1394 if ((pres
->start
- offset
) <= 0xa0000 &&
1395 (pres
->end
- offset
) >= 0xbffff)
1400 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1401 BUG_ON(res
== NULL
);
1402 res
->name
= "Legacy VGA memory";
1403 res
->flags
= IORESOURCE_MEM
;
1404 res
->start
= 0xa0000 + offset
;
1405 res
->end
= 0xbffff + offset
;
1406 pr_debug("Candidate VGA memory: %pR\n", res
);
1407 if (request_resource(pres
, res
)) {
1409 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1410 pci_domain_nr(bus
), bus
->number
, res
);
1415 void __init
pcibios_resource_survey(void)
1419 /* Allocate and assign resources. If we re-assign everything, then
1420 * we skip the allocate phase
1422 list_for_each_entry(b
, &pci_root_buses
, node
)
1423 pcibios_allocate_bus_resources(b
);
1425 if (!(ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)) {
1426 pcibios_allocate_resources(0);
1427 pcibios_allocate_resources(1);
1430 /* Before we start assigning unassigned resource, we try to reserve
1431 * the low IO area and the VGA memory area if they intersect the
1432 * bus available resources to avoid allocating things on top of them
1434 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1435 list_for_each_entry(b
, &pci_root_buses
, node
)
1436 pcibios_reserve_legacy_regions(b
);
1439 /* Now, if the platform didn't decide to blindly trust the firmware,
1440 * we proceed to assigning things that were left unassigned
1442 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1443 pr_debug("PCI: Assigning unassigned resouces...\n");
1444 pci_assign_unassigned_resources();
1447 /* Call machine dependent fixup */
1448 if (ppc_md
.pcibios_fixup
)
1449 ppc_md
.pcibios_fixup();
1452 #ifdef CONFIG_HOTPLUG
1454 /* This is used by the PCI hotplug driver to allocate resource
1455 * of newly plugged busses. We can try to consolidate with the
1456 * rest of the code later, for now, keep it as-is as our main
1457 * resource allocation function doesn't deal with sub-trees yet.
1459 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1461 struct pci_dev
*dev
;
1462 struct pci_bus
*child_bus
;
1464 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1467 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1468 struct resource
*r
= &dev
->resource
[i
];
1470 if (r
->parent
|| !r
->start
|| !r
->flags
)
1473 pr_debug("PCI: Claiming %s: "
1474 "Resource %d: %016llx..%016llx [%x]\n",
1476 (unsigned long long)r
->start
,
1477 (unsigned long long)r
->end
,
1478 (unsigned int)r
->flags
);
1480 pci_claim_resource(dev
, i
);
1484 list_for_each_entry(child_bus
, &bus
->children
, node
)
1485 pcibios_claim_one_bus(child_bus
);
1487 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1490 /* pcibios_finish_adding_to_bus
1492 * This is to be called by the hotplug code after devices have been
1493 * added to a bus, this include calling it for a PHB that is just
1496 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1498 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1499 pci_domain_nr(bus
), bus
->number
);
1501 /* Allocate bus and devices resources */
1502 pcibios_allocate_bus_resources(bus
);
1503 pcibios_claim_one_bus(bus
);
1505 /* Add new devices to global lists. Register in proc, sysfs. */
1506 pci_bus_add_devices(bus
);
1509 eeh_add_device_tree_late(bus
);
1511 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1513 #endif /* CONFIG_HOTPLUG */
1515 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1517 if (ppc_md
.pcibios_enable_device_hook
)
1518 if (ppc_md
.pcibios_enable_device_hook(dev
))
1521 return pci_enable_resources(dev
, mask
);
1524 void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
)
1526 struct pci_bus
*bus
= hose
->bus
;
1527 struct resource
*res
;
1530 /* Hookup PHB IO resource */
1531 bus
->resource
[0] = res
= &hose
->io_resource
;
1534 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1535 " bridge %s (domain %d)\n",
1536 hose
->dn
->full_name
, hose
->global_number
);
1538 /* Workaround for lack of IO resource only on 32-bit */
1539 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1540 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1541 res
->flags
= IORESOURCE_IO
;
1542 #endif /* CONFIG_PPC32 */
1545 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1546 (unsigned long long)res
->start
,
1547 (unsigned long long)res
->end
,
1548 (unsigned long)res
->flags
);
1550 /* Hookup PHB Memory resources */
1551 for (i
= 0; i
< 3; ++i
) {
1552 res
= &hose
->mem_resources
[i
];
1556 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1557 "host bridge %s (domain %d)\n",
1558 hose
->dn
->full_name
, hose
->global_number
);
1560 /* Workaround for lack of MEM resource only on 32-bit */
1561 res
->start
= hose
->pci_mem_offset
;
1562 res
->end
= (resource_size_t
)-1LL;
1563 res
->flags
= IORESOURCE_MEM
;
1564 #endif /* CONFIG_PPC32 */
1566 bus
->resource
[i
+1] = res
;
1568 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i
,
1569 (unsigned long long)res
->start
,
1570 (unsigned long long)res
->end
,
1571 (unsigned long)res
->flags
);
1574 pr_debug("PCI: PHB MEM offset = %016llx\n",
1575 (unsigned long long)hose
->pci_mem_offset
);
1576 pr_debug("PCI: PHB IO offset = %08lx\n",
1577 (unsigned long)hose
->io_base_virt
- _IO_BASE
);