2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
27 #include <linux/list.h>
28 #include <linux/syscalls.h>
29 #include <linux/irq.h>
30 #include <linux/vmalloc.h>
32 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
37 #include <asm/machdep.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/firmware.h>
43 #define DBG(fmt...) printk(fmt)
48 static DEFINE_SPINLOCK(hose_spinlock
);
50 /* XXX kill that some day ... */
51 static int global_phb_number
; /* Global phb counter */
53 /* ISA Memory physical address */
54 resource_size_t isa_mem_base
;
56 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
57 unsigned int ppc_pci_flags
= 0;
60 static struct dma_mapping_ops
*pci_dma_ops
;
62 void set_pci_dma_ops(struct dma_mapping_ops
*dma_ops
)
64 pci_dma_ops
= dma_ops
;
67 struct dma_mapping_ops
*get_pci_dma_ops(void)
71 EXPORT_SYMBOL(get_pci_dma_ops
);
73 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
75 return dma_set_mask(&dev
->dev
, mask
);
78 int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
82 rc
= dma_set_mask(&dev
->dev
, mask
);
83 dev
->dev
.coherent_dma_mask
= dev
->dma_mask
;
88 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
90 struct pci_controller
*phb
;
92 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
95 spin_lock(&hose_spinlock
);
96 phb
->global_number
= global_phb_number
++;
97 list_add_tail(&phb
->list_node
, &hose_list
);
98 spin_unlock(&hose_spinlock
);
100 phb
->is_dynamic
= mem_init_done
;
103 int nid
= of_node_to_nid(dev
);
105 if (nid
< 0 || !node_online(nid
))
108 PHB_SET_NODE(phb
, nid
);
114 void pcibios_free_controller(struct pci_controller
*phb
)
116 spin_lock(&hose_spinlock
);
117 list_del(&phb
->list_node
);
118 spin_unlock(&hose_spinlock
);
124 int pcibios_vaddr_is_ioport(void __iomem
*address
)
127 struct pci_controller
*hose
;
130 spin_lock(&hose_spinlock
);
131 list_for_each_entry(hose
, &hose_list
, list_node
) {
133 size
= hose
->pci_io_size
;
135 size
= hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
137 if (address
>= hose
->io_base_virt
&&
138 address
< (hose
->io_base_virt
+ size
)) {
143 spin_unlock(&hose_spinlock
);
148 * Return the domain number for this bus.
150 int pci_domain_nr(struct pci_bus
*bus
)
152 struct pci_controller
*hose
= pci_bus_to_host(bus
);
154 return hose
->global_number
;
156 EXPORT_SYMBOL(pci_domain_nr
);
160 /* This routine is meant to be used early during boot, when the
161 * PCI bus numbers have not yet been assigned, and you need to
162 * issue PCI config cycles to an OF device.
163 * It could also be used to "fix" RTAS config cycles if you want
164 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
167 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
172 struct pci_controller
*hose
, *tmp
;
173 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
174 if (hose
->dn
== node
)
181 static ssize_t
pci_show_devspec(struct device
*dev
,
182 struct device_attribute
*attr
, char *buf
)
184 struct pci_dev
*pdev
;
185 struct device_node
*np
;
187 pdev
= to_pci_dev (dev
);
188 np
= pci_device_to_OF_node(pdev
);
189 if (np
== NULL
|| np
->full_name
== NULL
)
191 return sprintf(buf
, "%s", np
->full_name
);
193 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
194 #endif /* CONFIG_PPC_OF */
196 /* Add sysfs properties */
197 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
200 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
203 #endif /* CONFIG_PPC_OF */
207 char __devinit
*pcibios_setup(char *str
)
212 void __devinit
pcibios_setup_new_device(struct pci_dev
*dev
)
214 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
216 sd
->of_node
= pci_device_to_OF_node(dev
);
218 DBG("PCI: device %s OF node: %s\n", pci_name(dev
),
219 sd
->of_node
? sd
->of_node
->full_name
: "<none>");
221 sd
->dma_ops
= pci_dma_ops
;
223 sd
->dma_data
= (void *)PCI_DRAM_OFFSET
;
225 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
227 if (ppc_md
.pci_dma_dev_setup
)
228 ppc_md
.pci_dma_dev_setup(dev
);
230 EXPORT_SYMBOL(pcibios_setup_new_device
);
233 * Reads the interrupt pin to determine if interrupt is use by card.
234 * If the interrupt is used, then gets the interrupt line from the
235 * openfirmware and sets it in the pci_dev and pci_config line.
237 int pci_read_irq_line(struct pci_dev
*pci_dev
)
242 /* The current device-tree that iSeries generates from the HV
243 * PCI informations doesn't contain proper interrupt routing,
244 * and all the fallback would do is print out crap, so we
245 * don't attempt to resolve the interrupts here at all, some
246 * iSeries specific fixup does it.
248 * In the long run, we will hopefully fix the generated device-tree
251 #ifdef CONFIG_PPC_ISERIES
252 if (firmware_has_feature(FW_FEATURE_ISERIES
))
256 DBG("Try to map irq for %s...\n", pci_name(pci_dev
));
259 memset(&oirq
, 0xff, sizeof(oirq
));
261 /* Try to get a mapping from the device-tree */
262 if (of_irq_map_pci(pci_dev
, &oirq
)) {
265 /* If that fails, lets fallback to what is in the config
266 * space and map that through the default controller. We
267 * also set the type to level low since that's what PCI
268 * interrupts are. If your platform does differently, then
269 * either provide a proper interrupt tree or don't use this
272 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
276 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
277 line
== 0xff || line
== 0) {
280 DBG(" -> no map ! Using line %d (pin %d) from PCI config\n",
283 virq
= irq_create_mapping(NULL
, line
);
285 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
287 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
288 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
289 oirq
.controller
->full_name
);
291 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
295 DBG(" -> failed to map !\n");
299 DBG(" -> mapped to linux irq %d\n", virq
);
305 EXPORT_SYMBOL(pci_read_irq_line
);
308 * Platform support for /proc/bus/pci/X/Y mmap()s,
309 * modelled on the sparc64 implementation by Dave Miller.
314 * Adjust vm_pgoff of VMA such that it is the physical page offset
315 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
317 * Basically, the user finds the base address for his device which he wishes
318 * to mmap. They read the 32-bit value from the config space base register,
319 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
320 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
322 * Returns negative error code on failure, zero on success.
324 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
325 resource_size_t
*offset
,
326 enum pci_mmap_state mmap_state
)
328 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
329 unsigned long io_offset
= 0;
333 return NULL
; /* should never happen */
335 /* If memory, add on the PCI bridge address offset */
336 if (mmap_state
== pci_mmap_mem
) {
337 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
338 *offset
+= hose
->pci_mem_offset
;
340 res_bit
= IORESOURCE_MEM
;
342 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
343 *offset
+= io_offset
;
344 res_bit
= IORESOURCE_IO
;
348 * Check that the offset requested corresponds to one of the
349 * resources of the device.
351 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
352 struct resource
*rp
= &dev
->resource
[i
];
353 int flags
= rp
->flags
;
355 /* treat ROM as memory (should be already) */
356 if (i
== PCI_ROM_RESOURCE
)
357 flags
|= IORESOURCE_MEM
;
359 /* Active and same type? */
360 if ((flags
& res_bit
) == 0)
363 /* In the range of this resource? */
364 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
367 /* found it! construct the final physical address */
368 if (mmap_state
== pci_mmap_io
)
369 *offset
+= hose
->io_base_phys
- io_offset
;
377 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
380 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
382 enum pci_mmap_state mmap_state
,
385 unsigned long prot
= pgprot_val(protection
);
387 /* Write combine is always 0 on non-memory space mappings. On
388 * memory space, if the user didn't pass 1, we check for a
389 * "prefetchable" resource. This is a bit hackish, but we use
390 * this to workaround the inability of /sysfs to provide a write
393 if (mmap_state
!= pci_mmap_mem
)
395 else if (write_combine
== 0) {
396 if (rp
->flags
& IORESOURCE_PREFETCH
)
400 /* XXX would be nice to have a way to ask for write-through */
401 prot
|= _PAGE_NO_CACHE
;
403 prot
&= ~_PAGE_GUARDED
;
405 prot
|= _PAGE_GUARDED
;
407 return __pgprot(prot
);
411 * This one is used by /dev/mem and fbdev who have no clue about the
412 * PCI device, it tries to find the PCI device first and calls the
415 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
420 struct pci_dev
*pdev
= NULL
;
421 struct resource
*found
= NULL
;
422 unsigned long prot
= pgprot_val(protection
);
423 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
426 if (page_is_ram(pfn
))
427 return __pgprot(prot
);
429 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
431 for_each_pci_dev(pdev
) {
432 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
433 struct resource
*rp
= &pdev
->resource
[i
];
434 int flags
= rp
->flags
;
436 /* Active and same type? */
437 if ((flags
& IORESOURCE_MEM
) == 0)
439 /* In the range of this resource? */
440 if (offset
< (rp
->start
& PAGE_MASK
) ||
450 if (found
->flags
& IORESOURCE_PREFETCH
)
451 prot
&= ~_PAGE_GUARDED
;
455 DBG("non-PCI map for %llx, prot: %lx\n",
456 (unsigned long long)offset
, prot
);
458 return __pgprot(prot
);
463 * Perform the actual remap of the pages for a PCI device mapping, as
464 * appropriate for this architecture. The region in the process to map
465 * is described by vm_start and vm_end members of VMA, the base physical
466 * address is found in vm_pgoff.
467 * The pci device structure is provided so that architectures may make mapping
468 * decisions on a per-device or per-bus basis.
470 * Returns a negative error code on failure, zero on success.
472 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
473 enum pci_mmap_state mmap_state
, int write_combine
)
475 resource_size_t offset
=
476 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
480 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
484 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
485 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
487 mmap_state
, write_combine
);
489 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
490 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
495 /* This provides legacy IO read access on a bus */
496 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
498 unsigned long offset
;
499 struct pci_controller
*hose
= pci_bus_to_host(bus
);
500 struct resource
*rp
= &hose
->io_resource
;
503 /* Check if port can be supported by that bus. We only check
504 * the ranges of the PHB though, not the bus itself as the rules
505 * for forwarding legacy cycles down bridges are not our problem
506 * here. So if the host bridge supports it, we do it.
508 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
511 if (!(rp
->flags
& IORESOURCE_IO
))
513 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
515 addr
= hose
->io_base_virt
+ port
;
519 *((u8
*)val
) = in_8(addr
);
524 *((u16
*)val
) = in_le16(addr
);
529 *((u32
*)val
) = in_le32(addr
);
535 /* This provides legacy IO write access on a bus */
536 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
538 unsigned long offset
;
539 struct pci_controller
*hose
= pci_bus_to_host(bus
);
540 struct resource
*rp
= &hose
->io_resource
;
543 /* Check if port can be supported by that bus. We only check
544 * the ranges of the PHB though, not the bus itself as the rules
545 * for forwarding legacy cycles down bridges are not our problem
546 * here. So if the host bridge supports it, we do it.
548 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
551 if (!(rp
->flags
& IORESOURCE_IO
))
553 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
555 addr
= hose
->io_base_virt
+ port
;
557 /* WARNING: The generic code is idiotic. It gets passed a pointer
558 * to what can be a 1, 2 or 4 byte quantity and always reads that
559 * as a u32, which means that we have to correct the location of
560 * the data read within those 32 bits for size 1 and 2
564 out_8(addr
, val
>> 24);
569 out_le16(addr
, val
>> 16);
580 /* This provides legacy IO or memory mmap access on a bus */
581 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
582 struct vm_area_struct
*vma
,
583 enum pci_mmap_state mmap_state
)
585 struct pci_controller
*hose
= pci_bus_to_host(bus
);
586 resource_size_t offset
=
587 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
588 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
591 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
592 pci_domain_nr(bus
), bus
->number
,
593 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
594 (unsigned long long)offset
,
595 (unsigned long long)(offset
+ size
- 1));
597 if (mmap_state
== pci_mmap_mem
) {
598 if ((offset
+ size
) > hose
->isa_mem_size
)
600 offset
+= hose
->isa_mem_phys
;
602 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
603 unsigned long roffset
= offset
+ io_offset
;
604 rp
= &hose
->io_resource
;
605 if (!(rp
->flags
& IORESOURCE_IO
))
607 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
609 offset
+= hose
->io_base_phys
;
611 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
613 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
614 vma
->vm_page_prot
= __pgprot(pgprot_val(vma
->vm_page_prot
)
615 | _PAGE_NO_CACHE
| _PAGE_GUARDED
);
616 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
617 vma
->vm_end
- vma
->vm_start
,
621 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
622 const struct resource
*rsrc
,
623 resource_size_t
*start
, resource_size_t
*end
)
625 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
626 resource_size_t offset
= 0;
631 if (rsrc
->flags
& IORESOURCE_IO
)
632 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
634 /* We pass a fully fixed up address to userland for MMIO instead of
635 * a BAR value because X is lame and expects to be able to use that
636 * to pass to /dev/mem !
638 * That means that we'll have potentially 64 bits values where some
639 * userland apps only expect 32 (like X itself since it thinks only
640 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
643 * Hopefully, the sysfs insterface is immune to that gunk. Once X
644 * has been fixed (and the fix spread enough), we can re-enable the
645 * 2 lines below and pass down a BAR value to userland. In that case
646 * we'll also have to re-enable the matching code in
647 * __pci_mmap_make_offset().
652 else if (rsrc
->flags
& IORESOURCE_MEM
)
653 offset
= hose
->pci_mem_offset
;
656 *start
= rsrc
->start
- offset
;
657 *end
= rsrc
->end
- offset
;
661 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
662 * @hose: newly allocated pci_controller to be setup
663 * @dev: device node of the host bridge
664 * @primary: set if primary bus (32 bits only, soon to be deprecated)
666 * This function will parse the "ranges" property of a PCI host bridge device
667 * node and setup the resource mapping of a pci controller based on its
670 * Life would be boring if it wasn't for a few issues that we have to deal
673 * - We can only cope with one IO space range and up to 3 Memory space
674 * ranges. However, some machines (thanks Apple !) tend to split their
675 * space into lots of small contiguous ranges. So we have to coalesce.
677 * - We can only cope with all memory ranges having the same offset
678 * between CPU addresses and PCI addresses. Unfortunately, some bridges
679 * are setup for a large 1:1 mapping along with a small "window" which
680 * maps PCI address 0 to some arbitrary high address of the CPU space in
681 * order to give access to the ISA memory hole.
682 * The way out of here that I've chosen for now is to always set the
683 * offset based on the first resource found, then override it if we
684 * have a different offset and the previous was set by an ISA hole.
686 * - Some busses have IO space not starting at 0, which causes trouble with
687 * the way we do our IO resource renumbering. The code somewhat deals with
688 * it for 64 bits but I would expect problems on 32 bits.
690 * - Some 32 bits platforms such as 4xx can have physical space larger than
691 * 32 bits so we need to use 64 bits values for the parsing
693 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
694 struct device_node
*dev
,
699 int pna
= of_n_addr_cells(dev
);
701 int memno
= 0, isa_hole
= -1;
703 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
704 unsigned long long isa_mb
= 0;
705 struct resource
*res
;
707 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
708 dev
->full_name
, primary
? "(primary)" : "");
710 /* Get ranges property */
711 ranges
= of_get_property(dev
, "ranges", &rlen
);
716 while ((rlen
-= np
* 4) >= 0) {
717 /* Read next ranges element */
718 pci_space
= ranges
[0];
719 pci_addr
= of_read_number(ranges
+ 1, 2);
720 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
721 size
= of_read_number(ranges
+ pna
+ 3, 2);
724 /* If we failed translation or got a zero-sized region
725 * (some FW try to feed us with non sensical zero sized regions
726 * such as power3 which look like some kind of attempt at exposing
727 * the VGA memory hole)
729 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
732 /* Now consume following elements while they are contiguous */
733 for (; rlen
>= np
* sizeof(u32
);
734 ranges
+= np
, rlen
-= np
* 4) {
735 if (ranges
[0] != pci_space
)
737 pci_next
= of_read_number(ranges
+ 1, 2);
738 cpu_next
= of_translate_address(dev
, ranges
+ 3);
739 if (pci_next
!= pci_addr
+ size
||
740 cpu_next
!= cpu_addr
+ size
)
742 size
+= of_read_number(ranges
+ pna
+ 3, 2);
745 /* Act based on address space type */
747 switch ((pci_space
>> 24) & 0x3) {
748 case 1: /* PCI IO space */
750 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
751 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
753 /* We support only one IO range */
754 if (hose
->pci_io_size
) {
756 " \\--> Skipped (too many) !\n");
760 /* On 32 bits, limit I/O space to 16MB */
761 if (size
> 0x01000000)
764 /* 32 bits needs to map IOs here */
765 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
767 /* Expect trouble if pci_addr is not 0 */
770 (unsigned long)hose
->io_base_virt
;
771 #endif /* CONFIG_PPC32 */
772 /* pci_io_size and io_base_phys always represent IO
773 * space starting at 0 so we factor in pci_addr
775 hose
->pci_io_size
= pci_addr
+ size
;
776 hose
->io_base_phys
= cpu_addr
- pci_addr
;
779 res
= &hose
->io_resource
;
780 res
->flags
= IORESOURCE_IO
;
781 res
->start
= pci_addr
;
783 case 2: /* PCI Memory space */
784 case 3: /* PCI 64 bits Memory space */
786 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
787 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
788 (pci_space
& 0x40000000) ? "Prefetch" : "");
790 /* We support only 3 memory ranges */
793 " \\--> Skipped (too many) !\n");
796 /* Handles ISA memory hole space here */
800 if (primary
|| isa_mem_base
== 0)
801 isa_mem_base
= cpu_addr
;
802 hose
->isa_mem_phys
= cpu_addr
;
803 hose
->isa_mem_size
= size
;
806 /* We get the PCI/Mem offset from the first range or
807 * the, current one if the offset came from an ISA
808 * hole. If they don't match, bugger.
811 (isa_hole
>= 0 && pci_addr
!= 0 &&
812 hose
->pci_mem_offset
== isa_mb
))
813 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
814 else if (pci_addr
!= 0 &&
815 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
817 " \\--> Skipped (offset mismatch) !\n");
822 res
= &hose
->mem_resources
[memno
++];
823 res
->flags
= IORESOURCE_MEM
;
824 if (pci_space
& 0x40000000)
825 res
->flags
|= IORESOURCE_PREFETCH
;
826 res
->start
= cpu_addr
;
830 res
->name
= dev
->full_name
;
831 res
->end
= res
->start
+ size
- 1;
838 /* If there's an ISA hole and the pci_mem_offset is -not- matching
839 * the ISA hole offset, then we need to remove the ISA hole from
840 * the resource list for that brige
842 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
843 unsigned int next
= isa_hole
+ 1;
844 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
846 memmove(&hose
->mem_resources
[isa_hole
],
847 &hose
->mem_resources
[next
],
848 sizeof(struct resource
) * (memno
- next
));
849 hose
->mem_resources
[--memno
].flags
= 0;
853 /* Decide whether to display the domain number in /proc */
854 int pci_proc_domain(struct pci_bus
*bus
)
856 struct pci_controller
*hose
= pci_bus_to_host(bus
);
858 if (!(ppc_pci_flags
& PPC_PCI_ENABLE_PROC_DOMAINS
))
860 if (ppc_pci_flags
& PPC_PCI_COMPAT_DOMAIN_0
)
861 return hose
->global_number
!= 0;
865 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
866 struct resource
*res
)
868 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
869 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
873 if (res
->flags
& IORESOURCE_IO
) {
874 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
876 } else if (res
->flags
& IORESOURCE_MEM
)
877 offset
= hose
->pci_mem_offset
;
879 region
->start
= (res
->start
- offset
) & mask
;
880 region
->end
= (res
->end
- offset
) & mask
;
882 EXPORT_SYMBOL(pcibios_resource_to_bus
);
884 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
885 struct pci_bus_region
*region
)
887 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
888 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
892 if (res
->flags
& IORESOURCE_IO
) {
893 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
895 } else if (res
->flags
& IORESOURCE_MEM
)
896 offset
= hose
->pci_mem_offset
;
897 res
->start
= (region
->start
+ offset
) & mask
;
898 res
->end
= (region
->end
+ offset
) & mask
;
900 EXPORT_SYMBOL(pcibios_bus_to_resource
);
902 /* Fixup a bus resource into a linux resource */
903 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
905 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
906 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
908 if (res
->flags
& IORESOURCE_IO
) {
909 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
911 } else if (res
->flags
& IORESOURCE_MEM
)
912 offset
= hose
->pci_mem_offset
;
914 res
->start
= (res
->start
+ offset
) & mask
;
915 res
->end
= (res
->end
+ offset
) & mask
;
919 /* This header fixup will do the resource fixup for all devices as they are
920 * probed, but not for bridge ranges
922 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
924 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
928 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
932 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
933 struct resource
*res
= dev
->resource
+ i
;
936 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
937 * consider 0 as an unassigned BAR value. It's technically
938 * a valid value, but linux doesn't like it... so when we can
939 * re-assign things, we do so, but if we can't, we keep it
940 * around and hope for the best...
942 if (res
->start
== 0 && !(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
943 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
945 (unsigned long long)res
->start
,
946 (unsigned long long)res
->end
,
947 (unsigned int)res
->flags
);
948 res
->end
-= res
->start
;
950 res
->flags
|= IORESOURCE_UNSET
;
954 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
956 (unsigned long long)res
->start
,\
957 (unsigned long long)res
->end
,
958 (unsigned int)res
->flags
);
960 fixup_resource(res
, dev
);
962 pr_debug("PCI:%s %016llx-%016llx\n",
964 (unsigned long long)res
->start
,
965 (unsigned long long)res
->end
);
968 /* Call machine specific resource fixup */
969 if (ppc_md
.pcibios_fixup_resources
)
970 ppc_md
.pcibios_fixup_resources(dev
);
972 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
974 /* This function tries to figure out if a bridge resource has been initialized
975 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
976 * things go more smoothly when it gets it right. It should covers cases such
977 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
979 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
980 struct resource
*res
)
982 struct pci_controller
*hose
= pci_bus_to_host(bus
);
983 struct pci_dev
*dev
= bus
->self
;
984 resource_size_t offset
;
988 /* We don't do anything if PCI_PROBE_ONLY is set */
989 if (ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)
992 /* Job is a bit different between memory and IO */
993 if (res
->flags
& IORESOURCE_MEM
) {
994 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
995 * initialized by somebody
997 if (res
->start
!= hose
->pci_mem_offset
)
1000 /* The BAR is 0, let's check if memory decoding is enabled on
1001 * the bridge. If not, we consider it unassigned
1003 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1004 if ((command
& PCI_COMMAND_MEMORY
) == 0)
1007 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
1008 * resources covers that starting address (0 then it's good enough for
1011 for (i
= 0; i
< 3; i
++) {
1012 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
1013 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
1017 /* Well, it starts at 0 and we know it will collide so we may as
1018 * well consider it as unassigned. That covers the Apple case.
1022 /* If the BAR is non-0, then we consider it assigned */
1023 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1024 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
1027 /* Here, we are a bit different than memory as typically IO space
1028 * starting at low addresses -is- valid. What we do instead if that
1029 * we consider as unassigned anything that doesn't have IO enabled
1030 * in the PCI command register, and that's it.
1032 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1033 if (command
& PCI_COMMAND_IO
)
1036 /* It's starting at 0 and IO is disabled in the bridge, consider
1043 /* Fixup resources of a PCI<->PCI bridge */
1044 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1046 struct resource
*res
;
1049 struct pci_dev
*dev
= bus
->self
;
1051 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1052 if ((res
= bus
->resource
[i
]) == NULL
)
1056 if (i
>= 3 && bus
->self
->transparent
)
1059 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1061 (unsigned long long)res
->start
,\
1062 (unsigned long long)res
->end
,
1063 (unsigned int)res
->flags
);
1066 fixup_resource(res
, dev
);
1068 /* Try to detect uninitialized P2P bridge resources,
1069 * and clear them out so they get re-assigned later
1071 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1073 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
1076 pr_debug("PCI:%s %016llx-%016llx\n",
1078 (unsigned long long)res
->start
,
1079 (unsigned long long)res
->end
);
1084 static void __devinit
__pcibios_fixup_bus(struct pci_bus
*bus
)
1086 struct pci_dev
*dev
= bus
->self
;
1088 pr_debug("PCI: Fixup bus %d (%s)\n", bus
->number
, dev
? pci_name(dev
) : "PHB");
1090 /* Fixup PCI<->PCI bridges. Host bridges are handled separately, for
1091 * now differently between 32 and 64 bits.
1094 pcibios_fixup_bridge(bus
);
1096 /* Additional setup that is different between 32 and 64 bits for now */
1097 pcibios_do_bus_setup(bus
);
1099 /* Platform specific bus fixups */
1100 if (ppc_md
.pcibios_fixup_bus
)
1101 ppc_md
.pcibios_fixup_bus(bus
);
1103 /* Read default IRQs and fixup if necessary */
1104 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1105 pci_read_irq_line(dev
);
1106 if (ppc_md
.pci_irq_fixup
)
1107 ppc_md
.pci_irq_fixup(dev
);
1111 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1113 /* When called from the generic PCI probe, read PCI<->PCI bridge
1114 * bases before proceeding
1116 if (bus
->self
!= NULL
)
1117 pci_read_bridge_bases(bus
);
1118 __pcibios_fixup_bus(bus
);
1120 EXPORT_SYMBOL(pcibios_fixup_bus
);
1122 /* When building a bus from the OF tree rather than probing, we need a
1123 * slightly different version of the fixup which doesn't read the
1124 * bridge bases using config space accesses
1126 void __devinit
pcibios_fixup_of_probed_bus(struct pci_bus
*bus
)
1128 __pcibios_fixup_bus(bus
);
1131 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1133 if ((ppc_pci_flags
& PPC_PCI_CAN_SKIP_ISA_ALIGN
) &&
1134 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1140 * We need to avoid collisions with `mirrored' VGA ports
1141 * and other strange ISA hardware, so we always want the
1142 * addresses to be allocated in the 0x000-0x0ff region
1145 * Why? Because some silly external IO cards only decode
1146 * the low 10 bits of the IO address. The 0x00-0xff region
1147 * is reserved for motherboard devices that decode all 16
1148 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1149 * but we want to try to avoid allocating at 0x2900-0x2bff
1150 * which might have be mirrored at 0x0100-0x03ff..
1152 void pcibios_align_resource(void *data
, struct resource
*res
,
1153 resource_size_t size
, resource_size_t align
)
1155 struct pci_dev
*dev
= data
;
1157 if (res
->flags
& IORESOURCE_IO
) {
1158 resource_size_t start
= res
->start
;
1160 if (skip_isa_ioresource_align(dev
))
1162 if (start
& 0x300) {
1163 start
= (start
+ 0x3ff) & ~0x3ff;
1168 EXPORT_SYMBOL(pcibios_align_resource
);
1171 * Reparent resource children of pr that conflict with res
1172 * under res, and make res replace those children.
1174 static int __init
reparent_resources(struct resource
*parent
,
1175 struct resource
*res
)
1177 struct resource
*p
, **pp
;
1178 struct resource
**firstpp
= NULL
;
1180 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1181 if (p
->end
< res
->start
)
1183 if (res
->end
< p
->start
)
1185 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1186 return -1; /* not completely contained */
1187 if (firstpp
== NULL
)
1190 if (firstpp
== NULL
)
1191 return -1; /* didn't find any conflicting entries? */
1192 res
->parent
= parent
;
1193 res
->child
= *firstpp
;
1197 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1199 DBG(KERN_INFO
"PCI: reparented %s [%llx..%llx] under %s\n",
1201 (unsigned long long)p
->start
,
1202 (unsigned long long)p
->end
, res
->name
);
1208 * Handle resources of PCI devices. If the world were perfect, we could
1209 * just allocate all the resource regions and do nothing more. It isn't.
1210 * On the other hand, we cannot just re-allocate all devices, as it would
1211 * require us to know lots of host bridge internals. So we attempt to
1212 * keep as much of the original configuration as possible, but tweak it
1213 * when it's found to be wrong.
1215 * Known BIOS problems we have to work around:
1216 * - I/O or memory regions not configured
1217 * - regions configured, but not enabled in the command register
1218 * - bogus I/O addresses above 64K used
1219 * - expansion ROMs left enabled (this may sound harmless, but given
1220 * the fact the PCI specs explicitly allow address decoders to be
1221 * shared between expansion ROMs and other resource regions, it's
1222 * at least dangerous)
1225 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1226 * This gives us fixed barriers on where we can allocate.
1227 * (2) Allocate resources for all enabled devices. If there is
1228 * a collision, just mark the resource as unallocated. Also
1229 * disable expansion ROMs during this step.
1230 * (3) Try to allocate resources for disabled devices. If the
1231 * resources were assigned correctly, everything goes well,
1232 * if they weren't, they won't disturb allocation of other
1234 * (4) Assign new addresses to resources which were either
1235 * not configured at all or misconfigured. If explicitly
1236 * requested by the user, configure expansion ROM address
1240 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1244 struct resource
*res
, *pr
;
1246 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1247 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
1248 || res
->start
> res
->end
)
1250 if (bus
->parent
== NULL
)
1251 pr
= (res
->flags
& IORESOURCE_IO
) ?
1252 &ioport_resource
: &iomem_resource
;
1254 /* Don't bother with non-root busses when
1255 * re-assigning all resources. We clear the
1256 * resource flags as if they were colliding
1257 * and as such ensure proper re-allocation
1260 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)
1261 goto clear_resource
;
1262 pr
= pci_find_parent_resource(bus
->self
, res
);
1264 /* this happens when the generic PCI
1265 * code (wrongly) decides that this
1266 * bridge is transparent -- paulus
1272 DBG("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1273 "[0x%x], parent %p (%s)\n",
1274 bus
->self
? pci_name(bus
->self
) : "PHB",
1276 (unsigned long long)res
->start
,
1277 (unsigned long long)res
->end
,
1278 (unsigned int)res
->flags
,
1279 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1281 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1282 if (request_resource(pr
, res
) == 0)
1285 * Must be a conflict with an existing entry.
1286 * Move that entry (or entries) under the
1287 * bridge resource and try again.
1289 if (reparent_resources(pr
, res
) == 0)
1292 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1293 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1298 list_for_each_entry(b
, &bus
->children
, node
)
1299 pcibios_allocate_bus_resources(b
);
1302 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1304 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1306 DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1308 (unsigned long long)r
->start
,
1309 (unsigned long long)r
->end
,
1310 (unsigned int)r
->flags
);
1312 pr
= pci_find_parent_resource(dev
, r
);
1313 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1314 request_resource(pr
, r
) < 0) {
1315 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1316 " of device %s, will remap\n", idx
, pci_name(dev
));
1318 DBG("PCI: parent is %p: %016llx-%016llx [%x]\n", pr
,
1319 (unsigned long long)pr
->start
,
1320 (unsigned long long)pr
->end
,
1321 (unsigned int)pr
->flags
);
1322 /* We'll assign a new address later */
1323 r
->flags
|= IORESOURCE_UNSET
;
1329 static void __init
pcibios_allocate_resources(int pass
)
1331 struct pci_dev
*dev
= NULL
;
1336 for_each_pci_dev(dev
) {
1337 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1338 for (idx
= 0; idx
< 6; idx
++) {
1339 r
= &dev
->resource
[idx
];
1340 if (r
->parent
) /* Already allocated */
1342 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1343 continue; /* Not assigned at all */
1344 if (r
->flags
& IORESOURCE_IO
)
1345 disabled
= !(command
& PCI_COMMAND_IO
);
1347 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1348 if (pass
== disabled
)
1349 alloc_resource(dev
, idx
);
1353 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1354 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
1355 /* Turn the ROM off, leave the resource region,
1356 * but keep it unregistered.
1359 DBG("PCI: Switching off ROM of %s\n", pci_name(dev
));
1360 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1361 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1362 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1363 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1368 void __init
pcibios_resource_survey(void)
1372 /* Allocate and assign resources. If we re-assign everything, then
1373 * we skip the allocate phase
1375 list_for_each_entry(b
, &pci_root_buses
, node
)
1376 pcibios_allocate_bus_resources(b
);
1378 if (!(ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)) {
1379 pcibios_allocate_resources(0);
1380 pcibios_allocate_resources(1);
1383 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1384 DBG("PCI: Assigning unassigned resouces...\n");
1385 pci_assign_unassigned_resources();
1388 /* Call machine dependent fixup */
1389 if (ppc_md
.pcibios_fixup
)
1390 ppc_md
.pcibios_fixup();
1393 #ifdef CONFIG_HOTPLUG
1394 /* This is used by the pSeries hotplug driver to allocate resource
1395 * of newly plugged busses. We can try to consolidate with the
1396 * rest of the code later, for now, keep it as-is
1398 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1400 struct pci_dev
*dev
;
1401 struct pci_bus
*child_bus
;
1403 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1406 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1407 struct resource
*r
= &dev
->resource
[i
];
1409 if (r
->parent
|| !r
->start
|| !r
->flags
)
1411 pci_claim_resource(dev
, i
);
1415 list_for_each_entry(child_bus
, &bus
->children
, node
)
1416 pcibios_claim_one_bus(child_bus
);
1418 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1419 #endif /* CONFIG_HOTPLUG */
1421 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1423 if (ppc_md
.pcibios_enable_device_hook
)
1424 if (ppc_md
.pcibios_enable_device_hook(dev
))
1427 return pci_enable_resources(dev
, mask
);