2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
27 #include <linux/list.h>
28 #include <linux/syscalls.h>
29 #include <linux/irq.h>
30 #include <linux/vmalloc.h>
32 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
37 #include <asm/machdep.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/firmware.h>
41 static DEFINE_SPINLOCK(hose_spinlock
);
43 /* XXX kill that some day ... */
44 static int global_phb_number
; /* Global phb counter */
46 /* ISA Memory physical address */
47 resource_size_t isa_mem_base
;
49 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
50 unsigned int ppc_pci_flags
= 0;
53 static struct dma_mapping_ops
*pci_dma_ops
;
55 void set_pci_dma_ops(struct dma_mapping_ops
*dma_ops
)
57 pci_dma_ops
= dma_ops
;
60 struct dma_mapping_ops
*get_pci_dma_ops(void)
64 EXPORT_SYMBOL(get_pci_dma_ops
);
66 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
68 return dma_set_mask(&dev
->dev
, mask
);
71 int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
75 rc
= dma_set_mask(&dev
->dev
, mask
);
76 dev
->dev
.coherent_dma_mask
= dev
->dma_mask
;
81 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
83 struct pci_controller
*phb
;
85 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
88 spin_lock(&hose_spinlock
);
89 phb
->global_number
= global_phb_number
++;
90 list_add_tail(&phb
->list_node
, &hose_list
);
91 spin_unlock(&hose_spinlock
);
93 phb
->is_dynamic
= mem_init_done
;
96 int nid
= of_node_to_nid(dev
);
98 if (nid
< 0 || !node_online(nid
))
101 PHB_SET_NODE(phb
, nid
);
107 void pcibios_free_controller(struct pci_controller
*phb
)
109 spin_lock(&hose_spinlock
);
110 list_del(&phb
->list_node
);
111 spin_unlock(&hose_spinlock
);
117 int pcibios_vaddr_is_ioport(void __iomem
*address
)
120 struct pci_controller
*hose
;
123 spin_lock(&hose_spinlock
);
124 list_for_each_entry(hose
, &hose_list
, list_node
) {
126 size
= hose
->pci_io_size
;
128 size
= hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
130 if (address
>= hose
->io_base_virt
&&
131 address
< (hose
->io_base_virt
+ size
)) {
136 spin_unlock(&hose_spinlock
);
141 * Return the domain number for this bus.
143 int pci_domain_nr(struct pci_bus
*bus
)
145 struct pci_controller
*hose
= pci_bus_to_host(bus
);
147 return hose
->global_number
;
149 EXPORT_SYMBOL(pci_domain_nr
);
153 /* This routine is meant to be used early during boot, when the
154 * PCI bus numbers have not yet been assigned, and you need to
155 * issue PCI config cycles to an OF device.
156 * It could also be used to "fix" RTAS config cycles if you want
157 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
160 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
165 struct pci_controller
*hose
, *tmp
;
166 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
167 if (hose
->dn
== node
)
174 static ssize_t
pci_show_devspec(struct device
*dev
,
175 struct device_attribute
*attr
, char *buf
)
177 struct pci_dev
*pdev
;
178 struct device_node
*np
;
180 pdev
= to_pci_dev (dev
);
181 np
= pci_device_to_OF_node(pdev
);
182 if (np
== NULL
|| np
->full_name
== NULL
)
184 return sprintf(buf
, "%s", np
->full_name
);
186 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
187 #endif /* CONFIG_PPC_OF */
189 /* Add sysfs properties */
190 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
193 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
196 #endif /* CONFIG_PPC_OF */
200 char __devinit
*pcibios_setup(char *str
)
205 void __devinit
pcibios_setup_new_device(struct pci_dev
*dev
)
207 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
209 sd
->of_node
= pci_device_to_OF_node(dev
);
211 pr_debug("PCI: device %s OF node: %s\n", pci_name(dev
),
212 sd
->of_node
? sd
->of_node
->full_name
: "<none>");
214 sd
->dma_ops
= pci_dma_ops
;
216 sd
->dma_data
= (void *)PCI_DRAM_OFFSET
;
218 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
220 if (ppc_md
.pci_dma_dev_setup
)
221 ppc_md
.pci_dma_dev_setup(dev
);
223 EXPORT_SYMBOL(pcibios_setup_new_device
);
226 * Reads the interrupt pin to determine if interrupt is use by card.
227 * If the interrupt is used, then gets the interrupt line from the
228 * openfirmware and sets it in the pci_dev and pci_config line.
230 int pci_read_irq_line(struct pci_dev
*pci_dev
)
235 /* The current device-tree that iSeries generates from the HV
236 * PCI informations doesn't contain proper interrupt routing,
237 * and all the fallback would do is print out crap, so we
238 * don't attempt to resolve the interrupts here at all, some
239 * iSeries specific fixup does it.
241 * In the long run, we will hopefully fix the generated device-tree
244 #ifdef CONFIG_PPC_ISERIES
245 if (firmware_has_feature(FW_FEATURE_ISERIES
))
249 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
252 memset(&oirq
, 0xff, sizeof(oirq
));
254 /* Try to get a mapping from the device-tree */
255 if (of_irq_map_pci(pci_dev
, &oirq
)) {
258 /* If that fails, lets fallback to what is in the config
259 * space and map that through the default controller. We
260 * also set the type to level low since that's what PCI
261 * interrupts are. If your platform does differently, then
262 * either provide a proper interrupt tree or don't use this
265 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
269 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
270 line
== 0xff || line
== 0) {
273 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
276 virq
= irq_create_mapping(NULL
, line
);
278 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
280 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
281 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
282 oirq
.controller
->full_name
);
284 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
288 pr_debug(" Failed to map !\n");
292 pr_debug(" Mapped to linux irq %d\n", virq
);
298 EXPORT_SYMBOL(pci_read_irq_line
);
301 * Platform support for /proc/bus/pci/X/Y mmap()s,
302 * modelled on the sparc64 implementation by Dave Miller.
307 * Adjust vm_pgoff of VMA such that it is the physical page offset
308 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
310 * Basically, the user finds the base address for his device which he wishes
311 * to mmap. They read the 32-bit value from the config space base register,
312 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
313 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
315 * Returns negative error code on failure, zero on success.
317 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
318 resource_size_t
*offset
,
319 enum pci_mmap_state mmap_state
)
321 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
322 unsigned long io_offset
= 0;
326 return NULL
; /* should never happen */
328 /* If memory, add on the PCI bridge address offset */
329 if (mmap_state
== pci_mmap_mem
) {
330 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
331 *offset
+= hose
->pci_mem_offset
;
333 res_bit
= IORESOURCE_MEM
;
335 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
336 *offset
+= io_offset
;
337 res_bit
= IORESOURCE_IO
;
341 * Check that the offset requested corresponds to one of the
342 * resources of the device.
344 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
345 struct resource
*rp
= &dev
->resource
[i
];
346 int flags
= rp
->flags
;
348 /* treat ROM as memory (should be already) */
349 if (i
== PCI_ROM_RESOURCE
)
350 flags
|= IORESOURCE_MEM
;
352 /* Active and same type? */
353 if ((flags
& res_bit
) == 0)
356 /* In the range of this resource? */
357 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
360 /* found it! construct the final physical address */
361 if (mmap_state
== pci_mmap_io
)
362 *offset
+= hose
->io_base_phys
- io_offset
;
370 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
373 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
375 enum pci_mmap_state mmap_state
,
378 unsigned long prot
= pgprot_val(protection
);
380 /* Write combine is always 0 on non-memory space mappings. On
381 * memory space, if the user didn't pass 1, we check for a
382 * "prefetchable" resource. This is a bit hackish, but we use
383 * this to workaround the inability of /sysfs to provide a write
386 if (mmap_state
!= pci_mmap_mem
)
388 else if (write_combine
== 0) {
389 if (rp
->flags
& IORESOURCE_PREFETCH
)
393 /* XXX would be nice to have a way to ask for write-through */
394 prot
|= _PAGE_NO_CACHE
;
396 prot
&= ~_PAGE_GUARDED
;
398 prot
|= _PAGE_GUARDED
;
400 return __pgprot(prot
);
404 * This one is used by /dev/mem and fbdev who have no clue about the
405 * PCI device, it tries to find the PCI device first and calls the
408 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
413 struct pci_dev
*pdev
= NULL
;
414 struct resource
*found
= NULL
;
415 unsigned long prot
= pgprot_val(protection
);
416 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
419 if (page_is_ram(pfn
))
420 return __pgprot(prot
);
422 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
424 for_each_pci_dev(pdev
) {
425 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
426 struct resource
*rp
= &pdev
->resource
[i
];
427 int flags
= rp
->flags
;
429 /* Active and same type? */
430 if ((flags
& IORESOURCE_MEM
) == 0)
432 /* In the range of this resource? */
433 if (offset
< (rp
->start
& PAGE_MASK
) ||
443 if (found
->flags
& IORESOURCE_PREFETCH
)
444 prot
&= ~_PAGE_GUARDED
;
448 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
449 (unsigned long long)offset
, prot
);
451 return __pgprot(prot
);
456 * Perform the actual remap of the pages for a PCI device mapping, as
457 * appropriate for this architecture. The region in the process to map
458 * is described by vm_start and vm_end members of VMA, the base physical
459 * address is found in vm_pgoff.
460 * The pci device structure is provided so that architectures may make mapping
461 * decisions on a per-device or per-bus basis.
463 * Returns a negative error code on failure, zero on success.
465 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
466 enum pci_mmap_state mmap_state
, int write_combine
)
468 resource_size_t offset
=
469 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
473 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
477 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
478 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
480 mmap_state
, write_combine
);
482 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
483 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
488 /* This provides legacy IO read access on a bus */
489 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
491 unsigned long offset
;
492 struct pci_controller
*hose
= pci_bus_to_host(bus
);
493 struct resource
*rp
= &hose
->io_resource
;
496 /* Check if port can be supported by that bus. We only check
497 * the ranges of the PHB though, not the bus itself as the rules
498 * for forwarding legacy cycles down bridges are not our problem
499 * here. So if the host bridge supports it, we do it.
501 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
504 if (!(rp
->flags
& IORESOURCE_IO
))
506 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
508 addr
= hose
->io_base_virt
+ port
;
512 *((u8
*)val
) = in_8(addr
);
517 *((u16
*)val
) = in_le16(addr
);
522 *((u32
*)val
) = in_le32(addr
);
528 /* This provides legacy IO write access on a bus */
529 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
531 unsigned long offset
;
532 struct pci_controller
*hose
= pci_bus_to_host(bus
);
533 struct resource
*rp
= &hose
->io_resource
;
536 /* Check if port can be supported by that bus. We only check
537 * the ranges of the PHB though, not the bus itself as the rules
538 * for forwarding legacy cycles down bridges are not our problem
539 * here. So if the host bridge supports it, we do it.
541 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
544 if (!(rp
->flags
& IORESOURCE_IO
))
546 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
548 addr
= hose
->io_base_virt
+ port
;
550 /* WARNING: The generic code is idiotic. It gets passed a pointer
551 * to what can be a 1, 2 or 4 byte quantity and always reads that
552 * as a u32, which means that we have to correct the location of
553 * the data read within those 32 bits for size 1 and 2
557 out_8(addr
, val
>> 24);
562 out_le16(addr
, val
>> 16);
573 /* This provides legacy IO or memory mmap access on a bus */
574 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
575 struct vm_area_struct
*vma
,
576 enum pci_mmap_state mmap_state
)
578 struct pci_controller
*hose
= pci_bus_to_host(bus
);
579 resource_size_t offset
=
580 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
581 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
584 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
585 pci_domain_nr(bus
), bus
->number
,
586 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
587 (unsigned long long)offset
,
588 (unsigned long long)(offset
+ size
- 1));
590 if (mmap_state
== pci_mmap_mem
) {
591 if ((offset
+ size
) > hose
->isa_mem_size
)
593 offset
+= hose
->isa_mem_phys
;
595 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
596 unsigned long roffset
= offset
+ io_offset
;
597 rp
= &hose
->io_resource
;
598 if (!(rp
->flags
& IORESOURCE_IO
))
600 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
602 offset
+= hose
->io_base_phys
;
604 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
606 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
607 vma
->vm_page_prot
= __pgprot(pgprot_val(vma
->vm_page_prot
)
608 | _PAGE_NO_CACHE
| _PAGE_GUARDED
);
609 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
610 vma
->vm_end
- vma
->vm_start
,
614 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
615 const struct resource
*rsrc
,
616 resource_size_t
*start
, resource_size_t
*end
)
618 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
619 resource_size_t offset
= 0;
624 if (rsrc
->flags
& IORESOURCE_IO
)
625 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
627 /* We pass a fully fixed up address to userland for MMIO instead of
628 * a BAR value because X is lame and expects to be able to use that
629 * to pass to /dev/mem !
631 * That means that we'll have potentially 64 bits values where some
632 * userland apps only expect 32 (like X itself since it thinks only
633 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
636 * Hopefully, the sysfs insterface is immune to that gunk. Once X
637 * has been fixed (and the fix spread enough), we can re-enable the
638 * 2 lines below and pass down a BAR value to userland. In that case
639 * we'll also have to re-enable the matching code in
640 * __pci_mmap_make_offset().
645 else if (rsrc
->flags
& IORESOURCE_MEM
)
646 offset
= hose
->pci_mem_offset
;
649 *start
= rsrc
->start
- offset
;
650 *end
= rsrc
->end
- offset
;
654 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
655 * @hose: newly allocated pci_controller to be setup
656 * @dev: device node of the host bridge
657 * @primary: set if primary bus (32 bits only, soon to be deprecated)
659 * This function will parse the "ranges" property of a PCI host bridge device
660 * node and setup the resource mapping of a pci controller based on its
663 * Life would be boring if it wasn't for a few issues that we have to deal
666 * - We can only cope with one IO space range and up to 3 Memory space
667 * ranges. However, some machines (thanks Apple !) tend to split their
668 * space into lots of small contiguous ranges. So we have to coalesce.
670 * - We can only cope with all memory ranges having the same offset
671 * between CPU addresses and PCI addresses. Unfortunately, some bridges
672 * are setup for a large 1:1 mapping along with a small "window" which
673 * maps PCI address 0 to some arbitrary high address of the CPU space in
674 * order to give access to the ISA memory hole.
675 * The way out of here that I've chosen for now is to always set the
676 * offset based on the first resource found, then override it if we
677 * have a different offset and the previous was set by an ISA hole.
679 * - Some busses have IO space not starting at 0, which causes trouble with
680 * the way we do our IO resource renumbering. The code somewhat deals with
681 * it for 64 bits but I would expect problems on 32 bits.
683 * - Some 32 bits platforms such as 4xx can have physical space larger than
684 * 32 bits so we need to use 64 bits values for the parsing
686 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
687 struct device_node
*dev
,
692 int pna
= of_n_addr_cells(dev
);
694 int memno
= 0, isa_hole
= -1;
696 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
697 unsigned long long isa_mb
= 0;
698 struct resource
*res
;
700 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
701 dev
->full_name
, primary
? "(primary)" : "");
703 /* Get ranges property */
704 ranges
= of_get_property(dev
, "ranges", &rlen
);
709 while ((rlen
-= np
* 4) >= 0) {
710 /* Read next ranges element */
711 pci_space
= ranges
[0];
712 pci_addr
= of_read_number(ranges
+ 1, 2);
713 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
714 size
= of_read_number(ranges
+ pna
+ 3, 2);
717 /* If we failed translation or got a zero-sized region
718 * (some FW try to feed us with non sensical zero sized regions
719 * such as power3 which look like some kind of attempt at exposing
720 * the VGA memory hole)
722 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
725 /* Now consume following elements while they are contiguous */
726 for (; rlen
>= np
* sizeof(u32
);
727 ranges
+= np
, rlen
-= np
* 4) {
728 if (ranges
[0] != pci_space
)
730 pci_next
= of_read_number(ranges
+ 1, 2);
731 cpu_next
= of_translate_address(dev
, ranges
+ 3);
732 if (pci_next
!= pci_addr
+ size
||
733 cpu_next
!= cpu_addr
+ size
)
735 size
+= of_read_number(ranges
+ pna
+ 3, 2);
738 /* Act based on address space type */
740 switch ((pci_space
>> 24) & 0x3) {
741 case 1: /* PCI IO space */
743 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
744 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
746 /* We support only one IO range */
747 if (hose
->pci_io_size
) {
749 " \\--> Skipped (too many) !\n");
753 /* On 32 bits, limit I/O space to 16MB */
754 if (size
> 0x01000000)
757 /* 32 bits needs to map IOs here */
758 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
760 /* Expect trouble if pci_addr is not 0 */
763 (unsigned long)hose
->io_base_virt
;
764 #endif /* CONFIG_PPC32 */
765 /* pci_io_size and io_base_phys always represent IO
766 * space starting at 0 so we factor in pci_addr
768 hose
->pci_io_size
= pci_addr
+ size
;
769 hose
->io_base_phys
= cpu_addr
- pci_addr
;
772 res
= &hose
->io_resource
;
773 res
->flags
= IORESOURCE_IO
;
774 res
->start
= pci_addr
;
776 case 2: /* PCI Memory space */
777 case 3: /* PCI 64 bits Memory space */
779 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
780 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
781 (pci_space
& 0x40000000) ? "Prefetch" : "");
783 /* We support only 3 memory ranges */
786 " \\--> Skipped (too many) !\n");
789 /* Handles ISA memory hole space here */
793 if (primary
|| isa_mem_base
== 0)
794 isa_mem_base
= cpu_addr
;
795 hose
->isa_mem_phys
= cpu_addr
;
796 hose
->isa_mem_size
= size
;
799 /* We get the PCI/Mem offset from the first range or
800 * the, current one if the offset came from an ISA
801 * hole. If they don't match, bugger.
804 (isa_hole
>= 0 && pci_addr
!= 0 &&
805 hose
->pci_mem_offset
== isa_mb
))
806 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
807 else if (pci_addr
!= 0 &&
808 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
810 " \\--> Skipped (offset mismatch) !\n");
815 res
= &hose
->mem_resources
[memno
++];
816 res
->flags
= IORESOURCE_MEM
;
817 if (pci_space
& 0x40000000)
818 res
->flags
|= IORESOURCE_PREFETCH
;
819 res
->start
= cpu_addr
;
823 res
->name
= dev
->full_name
;
824 res
->end
= res
->start
+ size
- 1;
831 /* If there's an ISA hole and the pci_mem_offset is -not- matching
832 * the ISA hole offset, then we need to remove the ISA hole from
833 * the resource list for that brige
835 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
836 unsigned int next
= isa_hole
+ 1;
837 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
839 memmove(&hose
->mem_resources
[isa_hole
],
840 &hose
->mem_resources
[next
],
841 sizeof(struct resource
) * (memno
- next
));
842 hose
->mem_resources
[--memno
].flags
= 0;
846 /* Decide whether to display the domain number in /proc */
847 int pci_proc_domain(struct pci_bus
*bus
)
849 struct pci_controller
*hose
= pci_bus_to_host(bus
);
851 if (!(ppc_pci_flags
& PPC_PCI_ENABLE_PROC_DOMAINS
))
853 if (ppc_pci_flags
& PPC_PCI_COMPAT_DOMAIN_0
)
854 return hose
->global_number
!= 0;
858 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
859 struct resource
*res
)
861 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
862 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
866 if (res
->flags
& IORESOURCE_IO
) {
867 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
869 } else if (res
->flags
& IORESOURCE_MEM
)
870 offset
= hose
->pci_mem_offset
;
872 region
->start
= (res
->start
- offset
) & mask
;
873 region
->end
= (res
->end
- offset
) & mask
;
875 EXPORT_SYMBOL(pcibios_resource_to_bus
);
877 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
878 struct pci_bus_region
*region
)
880 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
881 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
885 if (res
->flags
& IORESOURCE_IO
) {
886 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
888 } else if (res
->flags
& IORESOURCE_MEM
)
889 offset
= hose
->pci_mem_offset
;
890 res
->start
= (region
->start
+ offset
) & mask
;
891 res
->end
= (region
->end
+ offset
) & mask
;
893 EXPORT_SYMBOL(pcibios_bus_to_resource
);
895 /* Fixup a bus resource into a linux resource */
896 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
898 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
899 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
901 if (res
->flags
& IORESOURCE_IO
) {
902 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
904 } else if (res
->flags
& IORESOURCE_MEM
)
905 offset
= hose
->pci_mem_offset
;
907 res
->start
= (res
->start
+ offset
) & mask
;
908 res
->end
= (res
->end
+ offset
) & mask
;
912 /* This header fixup will do the resource fixup for all devices as they are
913 * probed, but not for bridge ranges
915 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
917 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
921 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
925 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
926 struct resource
*res
= dev
->resource
+ i
;
929 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
930 * consider 0 as an unassigned BAR value. It's technically
931 * a valid value, but linux doesn't like it... so when we can
932 * re-assign things, we do so, but if we can't, we keep it
933 * around and hope for the best...
935 if (res
->start
== 0 && !(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
936 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
938 (unsigned long long)res
->start
,
939 (unsigned long long)res
->end
,
940 (unsigned int)res
->flags
);
941 res
->end
-= res
->start
;
943 res
->flags
|= IORESOURCE_UNSET
;
947 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
949 (unsigned long long)res
->start
,\
950 (unsigned long long)res
->end
,
951 (unsigned int)res
->flags
);
953 fixup_resource(res
, dev
);
955 pr_debug("PCI:%s %016llx-%016llx\n",
957 (unsigned long long)res
->start
,
958 (unsigned long long)res
->end
);
961 /* Call machine specific resource fixup */
962 if (ppc_md
.pcibios_fixup_resources
)
963 ppc_md
.pcibios_fixup_resources(dev
);
965 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
967 /* This function tries to figure out if a bridge resource has been initialized
968 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
969 * things go more smoothly when it gets it right. It should covers cases such
970 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
972 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
973 struct resource
*res
)
975 struct pci_controller
*hose
= pci_bus_to_host(bus
);
976 struct pci_dev
*dev
= bus
->self
;
977 resource_size_t offset
;
981 /* We don't do anything if PCI_PROBE_ONLY is set */
982 if (ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)
985 /* Job is a bit different between memory and IO */
986 if (res
->flags
& IORESOURCE_MEM
) {
987 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
988 * initialized by somebody
990 if (res
->start
!= hose
->pci_mem_offset
)
993 /* The BAR is 0, let's check if memory decoding is enabled on
994 * the bridge. If not, we consider it unassigned
996 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
997 if ((command
& PCI_COMMAND_MEMORY
) == 0)
1000 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
1001 * resources covers that starting address (0 then it's good enough for
1004 for (i
= 0; i
< 3; i
++) {
1005 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
1006 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
1010 /* Well, it starts at 0 and we know it will collide so we may as
1011 * well consider it as unassigned. That covers the Apple case.
1015 /* If the BAR is non-0, then we consider it assigned */
1016 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1017 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
1020 /* Here, we are a bit different than memory as typically IO space
1021 * starting at low addresses -is- valid. What we do instead if that
1022 * we consider as unassigned anything that doesn't have IO enabled
1023 * in the PCI command register, and that's it.
1025 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1026 if (command
& PCI_COMMAND_IO
)
1029 /* It's starting at 0 and IO is disabled in the bridge, consider
1036 /* Fixup resources of a PCI<->PCI bridge */
1037 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1039 struct resource
*res
;
1042 struct pci_dev
*dev
= bus
->self
;
1044 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1045 if ((res
= bus
->resource
[i
]) == NULL
)
1049 if (i
>= 3 && bus
->self
->transparent
)
1052 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1054 (unsigned long long)res
->start
,\
1055 (unsigned long long)res
->end
,
1056 (unsigned int)res
->flags
);
1059 fixup_resource(res
, dev
);
1061 /* Try to detect uninitialized P2P bridge resources,
1062 * and clear them out so they get re-assigned later
1064 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1066 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
1069 pr_debug("PCI:%s %016llx-%016llx\n",
1071 (unsigned long long)res
->start
,
1072 (unsigned long long)res
->end
);
1077 static void __devinit
__pcibios_fixup_bus(struct pci_bus
*bus
)
1079 struct pci_dev
*dev
= bus
->self
;
1081 pr_debug("PCI: Fixup bus %d (%s)\n", bus
->number
, dev
? pci_name(dev
) : "PHB");
1083 /* Fixup PCI<->PCI bridges. Host bridges are handled separately, for
1084 * now differently between 32 and 64 bits.
1087 pcibios_fixup_bridge(bus
);
1089 /* Additional setup that is different between 32 and 64 bits for now */
1090 pcibios_do_bus_setup(bus
);
1092 /* Platform specific bus fixups */
1093 if (ppc_md
.pcibios_fixup_bus
)
1094 ppc_md
.pcibios_fixup_bus(bus
);
1096 /* Read default IRQs and fixup if necessary */
1097 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1098 pci_read_irq_line(dev
);
1099 if (ppc_md
.pci_irq_fixup
)
1100 ppc_md
.pci_irq_fixup(dev
);
1104 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1106 /* When called from the generic PCI probe, read PCI<->PCI bridge
1107 * bases before proceeding
1109 if (bus
->self
!= NULL
)
1110 pci_read_bridge_bases(bus
);
1111 __pcibios_fixup_bus(bus
);
1113 EXPORT_SYMBOL(pcibios_fixup_bus
);
1115 /* When building a bus from the OF tree rather than probing, we need a
1116 * slightly different version of the fixup which doesn't read the
1117 * bridge bases using config space accesses
1119 void __devinit
pcibios_fixup_of_probed_bus(struct pci_bus
*bus
)
1121 __pcibios_fixup_bus(bus
);
1124 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1126 if ((ppc_pci_flags
& PPC_PCI_CAN_SKIP_ISA_ALIGN
) &&
1127 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1133 * We need to avoid collisions with `mirrored' VGA ports
1134 * and other strange ISA hardware, so we always want the
1135 * addresses to be allocated in the 0x000-0x0ff region
1138 * Why? Because some silly external IO cards only decode
1139 * the low 10 bits of the IO address. The 0x00-0xff region
1140 * is reserved for motherboard devices that decode all 16
1141 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1142 * but we want to try to avoid allocating at 0x2900-0x2bff
1143 * which might have be mirrored at 0x0100-0x03ff..
1145 void pcibios_align_resource(void *data
, struct resource
*res
,
1146 resource_size_t size
, resource_size_t align
)
1148 struct pci_dev
*dev
= data
;
1150 if (res
->flags
& IORESOURCE_IO
) {
1151 resource_size_t start
= res
->start
;
1153 if (skip_isa_ioresource_align(dev
))
1155 if (start
& 0x300) {
1156 start
= (start
+ 0x3ff) & ~0x3ff;
1161 EXPORT_SYMBOL(pcibios_align_resource
);
1164 * Reparent resource children of pr that conflict with res
1165 * under res, and make res replace those children.
1167 static int __init
reparent_resources(struct resource
*parent
,
1168 struct resource
*res
)
1170 struct resource
*p
, **pp
;
1171 struct resource
**firstpp
= NULL
;
1173 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1174 if (p
->end
< res
->start
)
1176 if (res
->end
< p
->start
)
1178 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1179 return -1; /* not completely contained */
1180 if (firstpp
== NULL
)
1183 if (firstpp
== NULL
)
1184 return -1; /* didn't find any conflicting entries? */
1185 res
->parent
= parent
;
1186 res
->child
= *firstpp
;
1190 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1192 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1194 (unsigned long long)p
->start
,
1195 (unsigned long long)p
->end
, res
->name
);
1201 * Handle resources of PCI devices. If the world were perfect, we could
1202 * just allocate all the resource regions and do nothing more. It isn't.
1203 * On the other hand, we cannot just re-allocate all devices, as it would
1204 * require us to know lots of host bridge internals. So we attempt to
1205 * keep as much of the original configuration as possible, but tweak it
1206 * when it's found to be wrong.
1208 * Known BIOS problems we have to work around:
1209 * - I/O or memory regions not configured
1210 * - regions configured, but not enabled in the command register
1211 * - bogus I/O addresses above 64K used
1212 * - expansion ROMs left enabled (this may sound harmless, but given
1213 * the fact the PCI specs explicitly allow address decoders to be
1214 * shared between expansion ROMs and other resource regions, it's
1215 * at least dangerous)
1218 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1219 * This gives us fixed barriers on where we can allocate.
1220 * (2) Allocate resources for all enabled devices. If there is
1221 * a collision, just mark the resource as unallocated. Also
1222 * disable expansion ROMs during this step.
1223 * (3) Try to allocate resources for disabled devices. If the
1224 * resources were assigned correctly, everything goes well,
1225 * if they weren't, they won't disturb allocation of other
1227 * (4) Assign new addresses to resources which were either
1228 * not configured at all or misconfigured. If explicitly
1229 * requested by the user, configure expansion ROM address
1233 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1237 struct resource
*res
, *pr
;
1239 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1240 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
1241 || res
->start
> res
->end
)
1243 if (bus
->parent
== NULL
)
1244 pr
= (res
->flags
& IORESOURCE_IO
) ?
1245 &ioport_resource
: &iomem_resource
;
1247 /* Don't bother with non-root busses when
1248 * re-assigning all resources. We clear the
1249 * resource flags as if they were colliding
1250 * and as such ensure proper re-allocation
1253 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)
1254 goto clear_resource
;
1255 pr
= pci_find_parent_resource(bus
->self
, res
);
1257 /* this happens when the generic PCI
1258 * code (wrongly) decides that this
1259 * bridge is transparent -- paulus
1265 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1266 "[0x%x], parent %p (%s)\n",
1267 bus
->self
? pci_name(bus
->self
) : "PHB",
1269 (unsigned long long)res
->start
,
1270 (unsigned long long)res
->end
,
1271 (unsigned int)res
->flags
,
1272 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1274 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1275 if (request_resource(pr
, res
) == 0)
1278 * Must be a conflict with an existing entry.
1279 * Move that entry (or entries) under the
1280 * bridge resource and try again.
1282 if (reparent_resources(pr
, res
) == 0)
1285 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1286 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1291 list_for_each_entry(b
, &bus
->children
, node
)
1292 pcibios_allocate_bus_resources(b
);
1295 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1297 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1299 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1301 (unsigned long long)r
->start
,
1302 (unsigned long long)r
->end
,
1303 (unsigned int)r
->flags
);
1305 pr
= pci_find_parent_resource(dev
, r
);
1306 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1307 request_resource(pr
, r
) < 0) {
1308 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1309 " of device %s, will remap\n", idx
, pci_name(dev
));
1311 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1313 (unsigned long long)pr
->start
,
1314 (unsigned long long)pr
->end
,
1315 (unsigned int)pr
->flags
);
1316 /* We'll assign a new address later */
1317 r
->flags
|= IORESOURCE_UNSET
;
1323 static void __init
pcibios_allocate_resources(int pass
)
1325 struct pci_dev
*dev
= NULL
;
1330 for_each_pci_dev(dev
) {
1331 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1332 for (idx
= 0; idx
< 6; idx
++) {
1333 r
= &dev
->resource
[idx
];
1334 if (r
->parent
) /* Already allocated */
1336 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1337 continue; /* Not assigned at all */
1338 if (r
->flags
& IORESOURCE_IO
)
1339 disabled
= !(command
& PCI_COMMAND_IO
);
1341 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1342 if (pass
== disabled
)
1343 alloc_resource(dev
, idx
);
1347 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1348 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
1349 /* Turn the ROM off, leave the resource region,
1350 * but keep it unregistered.
1353 pr_debug("PCI: Switching off ROM of %s\n",
1355 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1356 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1357 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1358 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1363 void __init
pcibios_resource_survey(void)
1367 /* Allocate and assign resources. If we re-assign everything, then
1368 * we skip the allocate phase
1370 list_for_each_entry(b
, &pci_root_buses
, node
)
1371 pcibios_allocate_bus_resources(b
);
1373 if (!(ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)) {
1374 pcibios_allocate_resources(0);
1375 pcibios_allocate_resources(1);
1378 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1379 pr_debug("PCI: Assigning unassigned resouces...\n");
1380 pci_assign_unassigned_resources();
1383 /* Call machine dependent fixup */
1384 if (ppc_md
.pcibios_fixup
)
1385 ppc_md
.pcibios_fixup();
1388 #ifdef CONFIG_HOTPLUG
1389 /* This is used by the pSeries hotplug driver to allocate resource
1390 * of newly plugged busses. We can try to consolidate with the
1391 * rest of the code later, for now, keep it as-is
1393 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1395 struct pci_dev
*dev
;
1396 struct pci_bus
*child_bus
;
1398 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1401 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1402 struct resource
*r
= &dev
->resource
[i
];
1404 if (r
->parent
|| !r
->start
|| !r
->flags
)
1406 pci_claim_resource(dev
, i
);
1410 list_for_each_entry(child_bus
, &bus
->children
, node
)
1411 pcibios_claim_one_bus(child_bus
);
1413 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1414 #endif /* CONFIG_HOTPLUG */
1416 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1418 if (ppc_md
.pcibios_enable_device_hook
)
1419 if (ppc_md
.pcibios_enable_device_hook(dev
))
1422 return pci_enable_resources(dev
, mask
);
1425 void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
)
1427 struct pci_bus
*bus
= hose
->bus
;
1428 struct resource
*res
;
1431 /* Hookup PHB IO resource */
1432 bus
->resource
[0] = res
= &hose
->io_resource
;
1435 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1436 " bridge %s (domain %d)\n",
1437 hose
->dn
->full_name
, hose
->global_number
);
1439 /* Workaround for lack of IO resource only on 32-bit */
1440 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1441 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1442 res
->flags
= IORESOURCE_IO
;
1443 #endif /* CONFIG_PPC32 */
1446 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1447 (unsigned long long)res
->start
,
1448 (unsigned long long)res
->end
,
1449 (unsigned long)res
->flags
);
1451 /* Hookup PHB Memory resources */
1452 for (i
= 0; i
< 3; ++i
) {
1453 res
= &hose
->mem_resources
[i
];
1457 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1458 "host bridge %s (domain %d)\n",
1459 hose
->dn
->full_name
, hose
->global_number
);
1461 /* Workaround for lack of MEM resource only on 32-bit */
1462 res
->start
= hose
->pci_mem_offset
;
1463 res
->end
= (resource_size_t
)-1LL;
1464 res
->flags
= IORESOURCE_MEM
;
1465 #endif /* CONFIG_PPC32 */
1467 bus
->resource
[i
+1] = res
;
1469 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i
,
1470 (unsigned long long)res
->start
,
1471 (unsigned long long)res
->end
,
1472 (unsigned long)res
->flags
);
1475 pr_debug("PCI: PHB MEM offset = %016llx\n",
1476 (unsigned long long)hose
->pci_mem_offset
);
1477 pr_debug("PCI: PHB IO offset = %08lx\n",
1478 (unsigned long)hose
->io_base_virt
- _IO_BASE
);