2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/delay.h>
25 #include <linux/export.h>
26 #include <linux/of_address.h>
27 #include <linux/of_pci.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 static DEFINE_SPINLOCK(hose_spinlock
);
48 /* XXX kill that some day ... */
49 static int global_phb_number
; /* Global phb counter */
51 /* ISA Memory physical address */
52 resource_size_t isa_mem_base
;
55 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
57 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
59 pci_dma_ops
= dma_ops
;
62 struct dma_map_ops
*get_pci_dma_ops(void)
66 EXPORT_SYMBOL(get_pci_dma_ops
);
68 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
70 struct pci_controller
*phb
;
72 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
75 spin_lock(&hose_spinlock
);
76 phb
->global_number
= global_phb_number
++;
77 list_add_tail(&phb
->list_node
, &hose_list
);
78 spin_unlock(&hose_spinlock
);
80 phb
->is_dynamic
= mem_init_done
;
83 int nid
= of_node_to_nid(dev
);
85 if (nid
< 0 || !node_online(nid
))
88 PHB_SET_NODE(phb
, nid
);
94 void pcibios_free_controller(struct pci_controller
*phb
)
96 spin_lock(&hose_spinlock
);
97 list_del(&phb
->list_node
);
98 spin_unlock(&hose_spinlock
);
105 * The function is used to return the minimal alignment
106 * for memory or I/O windows of the associated P2P bridge.
107 * By default, 4KiB alignment for I/O windows and 1MiB for
110 resource_size_t
pcibios_window_alignment(struct pci_bus
*bus
,
113 if (ppc_md
.pcibios_window_alignment
)
114 return ppc_md
.pcibios_window_alignment(bus
, type
);
117 * PCI core will figure out the default
118 * alignment: 4KiB for I/O and 1MiB for
124 void pcibios_reset_secondary_bus(struct pci_dev
*dev
)
128 if (ppc_md
.pcibios_reset_secondary_bus
) {
129 ppc_md
.pcibios_reset_secondary_bus(dev
);
133 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
134 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
135 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
138 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
139 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
143 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
146 return hose
->pci_io_size
;
148 return resource_size(&hose
->io_resource
);
152 int pcibios_vaddr_is_ioport(void __iomem
*address
)
155 struct pci_controller
*hose
;
156 resource_size_t size
;
158 spin_lock(&hose_spinlock
);
159 list_for_each_entry(hose
, &hose_list
, list_node
) {
160 size
= pcibios_io_size(hose
);
161 if (address
>= hose
->io_base_virt
&&
162 address
< (hose
->io_base_virt
+ size
)) {
167 spin_unlock(&hose_spinlock
);
171 unsigned long pci_address_to_pio(phys_addr_t address
)
173 struct pci_controller
*hose
;
174 resource_size_t size
;
175 unsigned long ret
= ~0;
177 spin_lock(&hose_spinlock
);
178 list_for_each_entry(hose
, &hose_list
, list_node
) {
179 size
= pcibios_io_size(hose
);
180 if (address
>= hose
->io_base_phys
&&
181 address
< (hose
->io_base_phys
+ size
)) {
183 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
184 ret
= base
+ (address
- hose
->io_base_phys
);
188 spin_unlock(&hose_spinlock
);
192 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
195 * Return the domain number for this bus.
197 int pci_domain_nr(struct pci_bus
*bus
)
199 struct pci_controller
*hose
= pci_bus_to_host(bus
);
201 return hose
->global_number
;
203 EXPORT_SYMBOL(pci_domain_nr
);
205 /* This routine is meant to be used early during boot, when the
206 * PCI bus numbers have not yet been assigned, and you need to
207 * issue PCI config cycles to an OF device.
208 * It could also be used to "fix" RTAS config cycles if you want
209 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
212 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
215 struct pci_controller
*hose
, *tmp
;
216 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
217 if (hose
->dn
== node
)
224 static ssize_t
pci_show_devspec(struct device
*dev
,
225 struct device_attribute
*attr
, char *buf
)
227 struct pci_dev
*pdev
;
228 struct device_node
*np
;
230 pdev
= to_pci_dev (dev
);
231 np
= pci_device_to_OF_node(pdev
);
232 if (np
== NULL
|| np
->full_name
== NULL
)
234 return sprintf(buf
, "%s", np
->full_name
);
236 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
238 /* Add sysfs properties */
239 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
241 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
245 * Reads the interrupt pin to determine if interrupt is use by card.
246 * If the interrupt is used, then gets the interrupt line from the
247 * openfirmware and sets it in the pci_dev and pci_config line.
249 static int pci_read_irq_line(struct pci_dev
*pci_dev
)
251 struct of_phandle_args oirq
;
254 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
257 memset(&oirq
, 0xff, sizeof(oirq
));
259 /* Try to get a mapping from the device-tree */
260 if (of_irq_parse_pci(pci_dev
, &oirq
)) {
263 /* If that fails, lets fallback to what is in the config
264 * space and map that through the default controller. We
265 * also set the type to level low since that's what PCI
266 * interrupts are. If your platform does differently, then
267 * either provide a proper interrupt tree or don't use this
270 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
274 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
275 line
== 0xff || line
== 0) {
278 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
281 virq
= irq_create_mapping(NULL
, line
);
283 irq_set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
285 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
286 oirq
.args_count
, oirq
.args
[0], oirq
.args
[1],
287 of_node_full_name(oirq
.np
));
289 virq
= irq_create_of_mapping(&oirq
);
292 pr_debug(" Failed to map !\n");
296 pr_debug(" Mapped to linux irq %d\n", virq
);
304 * Platform support for /proc/bus/pci/X/Y mmap()s,
305 * modelled on the sparc64 implementation by Dave Miller.
310 * Adjust vm_pgoff of VMA such that it is the physical page offset
311 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
313 * Basically, the user finds the base address for his device which he wishes
314 * to mmap. They read the 32-bit value from the config space base register,
315 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
316 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
318 * Returns negative error code on failure, zero on success.
320 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
321 resource_size_t
*offset
,
322 enum pci_mmap_state mmap_state
)
324 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
325 unsigned long io_offset
= 0;
329 return NULL
; /* should never happen */
331 /* If memory, add on the PCI bridge address offset */
332 if (mmap_state
== pci_mmap_mem
) {
333 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
334 *offset
+= hose
->pci_mem_offset
;
336 res_bit
= IORESOURCE_MEM
;
338 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
339 *offset
+= io_offset
;
340 res_bit
= IORESOURCE_IO
;
344 * Check that the offset requested corresponds to one of the
345 * resources of the device.
347 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
348 struct resource
*rp
= &dev
->resource
[i
];
349 int flags
= rp
->flags
;
351 /* treat ROM as memory (should be already) */
352 if (i
== PCI_ROM_RESOURCE
)
353 flags
|= IORESOURCE_MEM
;
355 /* Active and same type? */
356 if ((flags
& res_bit
) == 0)
359 /* In the range of this resource? */
360 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
363 /* found it! construct the final physical address */
364 if (mmap_state
== pci_mmap_io
)
365 *offset
+= hose
->io_base_phys
- io_offset
;
373 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
376 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
378 enum pci_mmap_state mmap_state
,
382 /* Write combine is always 0 on non-memory space mappings. On
383 * memory space, if the user didn't pass 1, we check for a
384 * "prefetchable" resource. This is a bit hackish, but we use
385 * this to workaround the inability of /sysfs to provide a write
388 if (mmap_state
!= pci_mmap_mem
)
390 else if (write_combine
== 0) {
391 if (rp
->flags
& IORESOURCE_PREFETCH
)
395 /* XXX would be nice to have a way to ask for write-through */
397 return pgprot_noncached_wc(protection
);
399 return pgprot_noncached(protection
);
403 * This one is used by /dev/mem and fbdev who have no clue about the
404 * PCI device, it tries to find the PCI device first and calls the
407 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
412 struct pci_dev
*pdev
= NULL
;
413 struct resource
*found
= NULL
;
414 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
417 if (page_is_ram(pfn
))
420 prot
= pgprot_noncached(prot
);
421 for_each_pci_dev(pdev
) {
422 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
423 struct resource
*rp
= &pdev
->resource
[i
];
424 int flags
= rp
->flags
;
426 /* Active and same type? */
427 if ((flags
& IORESOURCE_MEM
) == 0)
429 /* In the range of this resource? */
430 if (offset
< (rp
->start
& PAGE_MASK
) ||
440 if (found
->flags
& IORESOURCE_PREFETCH
)
441 prot
= pgprot_noncached_wc(prot
);
445 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
446 (unsigned long long)offset
, pgprot_val(prot
));
453 * Perform the actual remap of the pages for a PCI device mapping, as
454 * appropriate for this architecture. The region in the process to map
455 * is described by vm_start and vm_end members of VMA, the base physical
456 * address is found in vm_pgoff.
457 * The pci device structure is provided so that architectures may make mapping
458 * decisions on a per-device or per-bus basis.
460 * Returns a negative error code on failure, zero on success.
462 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
463 enum pci_mmap_state mmap_state
, int write_combine
)
465 resource_size_t offset
=
466 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
470 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
474 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
475 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
477 mmap_state
, write_combine
);
479 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
480 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
485 /* This provides legacy IO read access on a bus */
486 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
488 unsigned long offset
;
489 struct pci_controller
*hose
= pci_bus_to_host(bus
);
490 struct resource
*rp
= &hose
->io_resource
;
493 /* Check if port can be supported by that bus. We only check
494 * the ranges of the PHB though, not the bus itself as the rules
495 * for forwarding legacy cycles down bridges are not our problem
496 * here. So if the host bridge supports it, we do it.
498 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
501 if (!(rp
->flags
& IORESOURCE_IO
))
503 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
505 addr
= hose
->io_base_virt
+ port
;
509 *((u8
*)val
) = in_8(addr
);
514 *((u16
*)val
) = in_le16(addr
);
519 *((u32
*)val
) = in_le32(addr
);
525 /* This provides legacy IO write access on a bus */
526 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
528 unsigned long offset
;
529 struct pci_controller
*hose
= pci_bus_to_host(bus
);
530 struct resource
*rp
= &hose
->io_resource
;
533 /* Check if port can be supported by that bus. We only check
534 * the ranges of the PHB though, not the bus itself as the rules
535 * for forwarding legacy cycles down bridges are not our problem
536 * here. So if the host bridge supports it, we do it.
538 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
541 if (!(rp
->flags
& IORESOURCE_IO
))
543 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
545 addr
= hose
->io_base_virt
+ port
;
547 /* WARNING: The generic code is idiotic. It gets passed a pointer
548 * to what can be a 1, 2 or 4 byte quantity and always reads that
549 * as a u32, which means that we have to correct the location of
550 * the data read within those 32 bits for size 1 and 2
554 out_8(addr
, val
>> 24);
559 out_le16(addr
, val
>> 16);
570 /* This provides legacy IO or memory mmap access on a bus */
571 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
572 struct vm_area_struct
*vma
,
573 enum pci_mmap_state mmap_state
)
575 struct pci_controller
*hose
= pci_bus_to_host(bus
);
576 resource_size_t offset
=
577 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
578 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
581 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
582 pci_domain_nr(bus
), bus
->number
,
583 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
584 (unsigned long long)offset
,
585 (unsigned long long)(offset
+ size
- 1));
587 if (mmap_state
== pci_mmap_mem
) {
590 * Because X is lame and can fail starting if it gets an error trying
591 * to mmap legacy_mem (instead of just moving on without legacy memory
592 * access) we fake it here by giving it anonymous memory, effectively
593 * behaving just like /dev/zero
595 if ((offset
+ size
) > hose
->isa_mem_size
) {
597 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
598 current
->comm
, current
->pid
, pci_domain_nr(bus
), bus
->number
);
599 if (vma
->vm_flags
& VM_SHARED
)
600 return shmem_zero_setup(vma
);
603 offset
+= hose
->isa_mem_phys
;
605 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
606 unsigned long roffset
= offset
+ io_offset
;
607 rp
= &hose
->io_resource
;
608 if (!(rp
->flags
& IORESOURCE_IO
))
610 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
612 offset
+= hose
->io_base_phys
;
614 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
616 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
617 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
618 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
619 vma
->vm_end
- vma
->vm_start
,
623 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
624 const struct resource
*rsrc
,
625 resource_size_t
*start
, resource_size_t
*end
)
627 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
628 resource_size_t offset
= 0;
633 if (rsrc
->flags
& IORESOURCE_IO
)
634 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
636 /* We pass a fully fixed up address to userland for MMIO instead of
637 * a BAR value because X is lame and expects to be able to use that
638 * to pass to /dev/mem !
640 * That means that we'll have potentially 64 bits values where some
641 * userland apps only expect 32 (like X itself since it thinks only
642 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
645 * Hopefully, the sysfs insterface is immune to that gunk. Once X
646 * has been fixed (and the fix spread enough), we can re-enable the
647 * 2 lines below and pass down a BAR value to userland. In that case
648 * we'll also have to re-enable the matching code in
649 * __pci_mmap_make_offset().
654 else if (rsrc
->flags
& IORESOURCE_MEM
)
655 offset
= hose
->pci_mem_offset
;
658 *start
= rsrc
->start
- offset
;
659 *end
= rsrc
->end
- offset
;
663 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
664 * @hose: newly allocated pci_controller to be setup
665 * @dev: device node of the host bridge
666 * @primary: set if primary bus (32 bits only, soon to be deprecated)
668 * This function will parse the "ranges" property of a PCI host bridge device
669 * node and setup the resource mapping of a pci controller based on its
672 * Life would be boring if it wasn't for a few issues that we have to deal
675 * - We can only cope with one IO space range and up to 3 Memory space
676 * ranges. However, some machines (thanks Apple !) tend to split their
677 * space into lots of small contiguous ranges. So we have to coalesce.
679 * - Some busses have IO space not starting at 0, which causes trouble with
680 * the way we do our IO resource renumbering. The code somewhat deals with
681 * it for 64 bits but I would expect problems on 32 bits.
683 * - Some 32 bits platforms such as 4xx can have physical space larger than
684 * 32 bits so we need to use 64 bits values for the parsing
686 void pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
687 struct device_node
*dev
, int primary
)
690 struct resource
*res
;
691 struct of_pci_range range
;
692 struct of_pci_range_parser parser
;
694 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
695 dev
->full_name
, primary
? "(primary)" : "");
697 /* Check for ranges property */
698 if (of_pci_range_parser_init(&parser
, dev
))
702 for_each_of_pci_range(&parser
, &range
) {
703 /* If we failed translation or got a zero-sized region
704 * (some FW try to feed us with non sensical zero sized regions
705 * such as power3 which look like some kind of attempt at exposing
706 * the VGA memory hole)
708 if (range
.cpu_addr
== OF_BAD_ADDR
|| range
.size
== 0)
711 /* Act based on address space type */
713 switch (range
.flags
& IORESOURCE_TYPE_BITS
) {
716 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
717 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
720 /* We support only one IO range */
721 if (hose
->pci_io_size
) {
723 " \\--> Skipped (too many) !\n");
727 /* On 32 bits, limit I/O space to 16MB */
728 if (range
.size
> 0x01000000)
729 range
.size
= 0x01000000;
731 /* 32 bits needs to map IOs here */
732 hose
->io_base_virt
= ioremap(range
.cpu_addr
,
735 /* Expect trouble if pci_addr is not 0 */
738 (unsigned long)hose
->io_base_virt
;
739 #endif /* CONFIG_PPC32 */
740 /* pci_io_size and io_base_phys always represent IO
741 * space starting at 0 so we factor in pci_addr
743 hose
->pci_io_size
= range
.pci_addr
+ range
.size
;
744 hose
->io_base_phys
= range
.cpu_addr
- range
.pci_addr
;
747 res
= &hose
->io_resource
;
748 range
.cpu_addr
= range
.pci_addr
;
752 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
753 range
.cpu_addr
, range
.cpu_addr
+ range
.size
- 1,
755 (range
.pci_space
& 0x40000000) ?
758 /* We support only 3 memory ranges */
761 " \\--> Skipped (too many) !\n");
764 /* Handles ISA memory hole space here */
765 if (range
.pci_addr
== 0) {
766 if (primary
|| isa_mem_base
== 0)
767 isa_mem_base
= range
.cpu_addr
;
768 hose
->isa_mem_phys
= range
.cpu_addr
;
769 hose
->isa_mem_size
= range
.size
;
773 hose
->mem_offset
[memno
] = range
.cpu_addr
-
775 res
= &hose
->mem_resources
[memno
++];
779 of_pci_range_to_resource(&range
, dev
, res
);
784 /* Decide whether to display the domain number in /proc */
785 int pci_proc_domain(struct pci_bus
*bus
)
787 struct pci_controller
*hose
= pci_bus_to_host(bus
);
789 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS
))
791 if (pci_has_flag(PCI_COMPAT_DOMAIN_0
))
792 return hose
->global_number
!= 0;
796 int pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
798 if (ppc_md
.pcibios_root_bridge_prepare
)
799 return ppc_md
.pcibios_root_bridge_prepare(bridge
);
804 /* This header fixup will do the resource fixup for all devices as they are
805 * probed, but not for bridge ranges
807 static void pcibios_fixup_resources(struct pci_dev
*dev
)
809 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
813 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
817 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
818 struct resource
*res
= dev
->resource
+ i
;
819 struct pci_bus_region reg
;
823 /* If we're going to re-assign everything, we mark all resources
824 * as unset (and 0-base them). In addition, we mark BARs starting
825 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
826 * since in that case, we don't want to re-assign anything
828 pcibios_resource_to_bus(dev
->bus
, ®
, res
);
829 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC
) ||
830 (reg
.start
== 0 && !pci_has_flag(PCI_PROBE_ONLY
))) {
831 /* Only print message if not re-assigning */
832 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC
))
833 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
836 (unsigned long long)res
->start
,
837 (unsigned long long)res
->end
,
838 (unsigned int)res
->flags
);
839 res
->end
-= res
->start
;
841 res
->flags
|= IORESOURCE_UNSET
;
845 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
847 (unsigned long long)res
->start
,\
848 (unsigned long long)res
->end
,
849 (unsigned int)res
->flags
);
852 /* Call machine specific resource fixup */
853 if (ppc_md
.pcibios_fixup_resources
)
854 ppc_md
.pcibios_fixup_resources(dev
);
856 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
858 /* This function tries to figure out if a bridge resource has been initialized
859 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
860 * things go more smoothly when it gets it right. It should covers cases such
861 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
863 static int pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
864 struct resource
*res
)
866 struct pci_controller
*hose
= pci_bus_to_host(bus
);
867 struct pci_dev
*dev
= bus
->self
;
868 resource_size_t offset
;
869 struct pci_bus_region region
;
873 /* We don't do anything if PCI_PROBE_ONLY is set */
874 if (pci_has_flag(PCI_PROBE_ONLY
))
877 /* Job is a bit different between memory and IO */
878 if (res
->flags
& IORESOURCE_MEM
) {
879 pcibios_resource_to_bus(dev
->bus
, ®ion
, res
);
881 /* If the BAR is non-0 then it's probably been initialized */
882 if (region
.start
!= 0)
885 /* The BAR is 0, let's check if memory decoding is enabled on
886 * the bridge. If not, we consider it unassigned
888 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
889 if ((command
& PCI_COMMAND_MEMORY
) == 0)
892 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
893 * resources covers that starting address (0 then it's good enough for
894 * us for memory space)
896 for (i
= 0; i
< 3; i
++) {
897 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
898 hose
->mem_resources
[i
].start
== hose
->mem_offset
[i
])
902 /* Well, it starts at 0 and we know it will collide so we may as
903 * well consider it as unassigned. That covers the Apple case.
907 /* If the BAR is non-0, then we consider it assigned */
908 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
909 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
912 /* Here, we are a bit different than memory as typically IO space
913 * starting at low addresses -is- valid. What we do instead if that
914 * we consider as unassigned anything that doesn't have IO enabled
915 * in the PCI command register, and that's it.
917 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
918 if (command
& PCI_COMMAND_IO
)
921 /* It's starting at 0 and IO is disabled in the bridge, consider
928 /* Fixup resources of a PCI<->PCI bridge */
929 static void pcibios_fixup_bridge(struct pci_bus
*bus
)
931 struct resource
*res
;
934 struct pci_dev
*dev
= bus
->self
;
936 pci_bus_for_each_resource(bus
, res
, i
) {
937 if (!res
|| !res
->flags
)
939 if (i
>= 3 && bus
->self
->transparent
)
942 /* If we're going to reassign everything, we can
943 * shrink the P2P resource to have size as being
944 * of 0 in order to save space.
946 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC
)) {
947 res
->flags
|= IORESOURCE_UNSET
;
953 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
955 (unsigned long long)res
->start
,\
956 (unsigned long long)res
->end
,
957 (unsigned int)res
->flags
);
959 /* Try to detect uninitialized P2P bridge resources,
960 * and clear them out so they get re-assigned later
962 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
964 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
969 void pcibios_setup_bus_self(struct pci_bus
*bus
)
971 /* Fix up the bus resources for P2P bridges */
972 if (bus
->self
!= NULL
)
973 pcibios_fixup_bridge(bus
);
975 /* Platform specific bus fixups. This is currently only used
976 * by fsl_pci and I'm hoping to get rid of it at some point
978 if (ppc_md
.pcibios_fixup_bus
)
979 ppc_md
.pcibios_fixup_bus(bus
);
981 /* Setup bus DMA mappings */
982 if (ppc_md
.pci_dma_bus_setup
)
983 ppc_md
.pci_dma_bus_setup(bus
);
986 static void pcibios_setup_device(struct pci_dev
*dev
)
988 /* Fixup NUMA node as it may not be setup yet by the generic
989 * code and is needed by the DMA init
991 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
993 /* Hook up default DMA ops */
994 set_dma_ops(&dev
->dev
, pci_dma_ops
);
995 set_dma_offset(&dev
->dev
, PCI_DRAM_OFFSET
);
997 /* Additional platform DMA/iommu setup */
998 if (ppc_md
.pci_dma_dev_setup
)
999 ppc_md
.pci_dma_dev_setup(dev
);
1001 /* Read default IRQs and fixup if necessary */
1002 pci_read_irq_line(dev
);
1003 if (ppc_md
.pci_irq_fixup
)
1004 ppc_md
.pci_irq_fixup(dev
);
1007 int pcibios_add_device(struct pci_dev
*dev
)
1010 * We can only call pcibios_setup_device() after bus setup is complete,
1011 * since some of the platform specific DMA setup code depends on it.
1013 if (dev
->bus
->is_added
)
1014 pcibios_setup_device(dev
);
1018 void pcibios_setup_bus_devices(struct pci_bus
*bus
)
1020 struct pci_dev
*dev
;
1022 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1023 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1025 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1026 /* Cardbus can call us to add new devices to a bus, so ignore
1027 * those who are already fully discovered
1032 pcibios_setup_device(dev
);
1036 void pcibios_set_master(struct pci_dev
*dev
)
1038 /* No special bus mastering setup handling */
1041 void pcibios_fixup_bus(struct pci_bus
*bus
)
1043 /* When called from the generic PCI probe, read PCI<->PCI bridge
1044 * bases. This is -not- called when generating the PCI tree from
1045 * the OF device-tree.
1047 pci_read_bridge_bases(bus
);
1049 /* Now fixup the bus bus */
1050 pcibios_setup_bus_self(bus
);
1052 /* Now fixup devices on that bus */
1053 pcibios_setup_bus_devices(bus
);
1055 EXPORT_SYMBOL(pcibios_fixup_bus
);
1057 void pci_fixup_cardbus(struct pci_bus
*bus
)
1059 /* Now fixup devices on that bus */
1060 pcibios_setup_bus_devices(bus
);
1064 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1066 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN
) &&
1067 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1073 * We need to avoid collisions with `mirrored' VGA ports
1074 * and other strange ISA hardware, so we always want the
1075 * addresses to be allocated in the 0x000-0x0ff region
1078 * Why? Because some silly external IO cards only decode
1079 * the low 10 bits of the IO address. The 0x00-0xff region
1080 * is reserved for motherboard devices that decode all 16
1081 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1082 * but we want to try to avoid allocating at 0x2900-0x2bff
1083 * which might have be mirrored at 0x0100-0x03ff..
1085 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1086 resource_size_t size
, resource_size_t align
)
1088 struct pci_dev
*dev
= data
;
1089 resource_size_t start
= res
->start
;
1091 if (res
->flags
& IORESOURCE_IO
) {
1092 if (skip_isa_ioresource_align(dev
))
1095 start
= (start
+ 0x3ff) & ~0x3ff;
1100 EXPORT_SYMBOL(pcibios_align_resource
);
1103 * Reparent resource children of pr that conflict with res
1104 * under res, and make res replace those children.
1106 static int reparent_resources(struct resource
*parent
,
1107 struct resource
*res
)
1109 struct resource
*p
, **pp
;
1110 struct resource
**firstpp
= NULL
;
1112 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1113 if (p
->end
< res
->start
)
1115 if (res
->end
< p
->start
)
1117 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1118 return -1; /* not completely contained */
1119 if (firstpp
== NULL
)
1122 if (firstpp
== NULL
)
1123 return -1; /* didn't find any conflicting entries? */
1124 res
->parent
= parent
;
1125 res
->child
= *firstpp
;
1129 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1131 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1133 (unsigned long long)p
->start
,
1134 (unsigned long long)p
->end
, res
->name
);
1140 * Handle resources of PCI devices. If the world were perfect, we could
1141 * just allocate all the resource regions and do nothing more. It isn't.
1142 * On the other hand, we cannot just re-allocate all devices, as it would
1143 * require us to know lots of host bridge internals. So we attempt to
1144 * keep as much of the original configuration as possible, but tweak it
1145 * when it's found to be wrong.
1147 * Known BIOS problems we have to work around:
1148 * - I/O or memory regions not configured
1149 * - regions configured, but not enabled in the command register
1150 * - bogus I/O addresses above 64K used
1151 * - expansion ROMs left enabled (this may sound harmless, but given
1152 * the fact the PCI specs explicitly allow address decoders to be
1153 * shared between expansion ROMs and other resource regions, it's
1154 * at least dangerous)
1157 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1158 * This gives us fixed barriers on where we can allocate.
1159 * (2) Allocate resources for all enabled devices. If there is
1160 * a collision, just mark the resource as unallocated. Also
1161 * disable expansion ROMs during this step.
1162 * (3) Try to allocate resources for disabled devices. If the
1163 * resources were assigned correctly, everything goes well,
1164 * if they weren't, they won't disturb allocation of other
1166 * (4) Assign new addresses to resources which were either
1167 * not configured at all or misconfigured. If explicitly
1168 * requested by the user, configure expansion ROM address
1172 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1176 struct resource
*res
, *pr
;
1178 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1179 pci_domain_nr(bus
), bus
->number
);
1181 pci_bus_for_each_resource(bus
, res
, i
) {
1182 if (!res
|| !res
->flags
|| res
->start
> res
->end
|| res
->parent
)
1185 /* If the resource was left unset at this point, we clear it */
1186 if (res
->flags
& IORESOURCE_UNSET
)
1187 goto clear_resource
;
1189 if (bus
->parent
== NULL
)
1190 pr
= (res
->flags
& IORESOURCE_IO
) ?
1191 &ioport_resource
: &iomem_resource
;
1193 pr
= pci_find_parent_resource(bus
->self
, res
);
1195 /* this happens when the generic PCI
1196 * code (wrongly) decides that this
1197 * bridge is transparent -- paulus
1203 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1204 "[0x%x], parent %p (%s)\n",
1205 bus
->self
? pci_name(bus
->self
) : "PHB",
1207 (unsigned long long)res
->start
,
1208 (unsigned long long)res
->end
,
1209 (unsigned int)res
->flags
,
1210 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1212 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1213 if (request_resource(pr
, res
) == 0)
1216 * Must be a conflict with an existing entry.
1217 * Move that entry (or entries) under the
1218 * bridge resource and try again.
1220 if (reparent_resources(pr
, res
) == 0)
1223 pr_warning("PCI: Cannot allocate resource region "
1224 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1226 /* The resource might be figured out when doing
1227 * reassignment based on the resources required
1228 * by the downstream PCI devices. Here we set
1229 * the size of the resource to be 0 in order to
1237 list_for_each_entry(b
, &bus
->children
, node
)
1238 pcibios_allocate_bus_resources(b
);
1241 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
1243 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1245 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1247 (unsigned long long)r
->start
,
1248 (unsigned long long)r
->end
,
1249 (unsigned int)r
->flags
);
1251 pr
= pci_find_parent_resource(dev
, r
);
1252 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1253 request_resource(pr
, r
) < 0) {
1254 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1255 " of device %s, will remap\n", idx
, pci_name(dev
));
1257 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1259 (unsigned long long)pr
->start
,
1260 (unsigned long long)pr
->end
,
1261 (unsigned int)pr
->flags
);
1262 /* We'll assign a new address later */
1263 r
->flags
|= IORESOURCE_UNSET
;
1269 static void __init
pcibios_allocate_resources(int pass
)
1271 struct pci_dev
*dev
= NULL
;
1276 for_each_pci_dev(dev
) {
1277 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1278 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1279 r
= &dev
->resource
[idx
];
1280 if (r
->parent
) /* Already allocated */
1282 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1283 continue; /* Not assigned at all */
1284 /* We only allocate ROMs on pass 1 just in case they
1285 * have been screwed up by firmware
1287 if (idx
== PCI_ROM_RESOURCE
)
1289 if (r
->flags
& IORESOURCE_IO
)
1290 disabled
= !(command
& PCI_COMMAND_IO
);
1292 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1293 if (pass
== disabled
)
1294 alloc_resource(dev
, idx
);
1298 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1300 /* Turn the ROM off, leave the resource region,
1301 * but keep it unregistered.
1304 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1305 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1306 pr_debug("PCI: Switching off ROM of %s\n",
1308 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1309 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1310 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1316 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1318 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1319 resource_size_t offset
;
1320 struct resource
*res
, *pres
;
1323 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus
));
1326 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1328 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1329 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1330 BUG_ON(res
== NULL
);
1331 res
->name
= "Legacy IO";
1332 res
->flags
= IORESOURCE_IO
;
1333 res
->start
= offset
;
1334 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1335 pr_debug("Candidate legacy IO: %pR\n", res
);
1336 if (request_resource(&hose
->io_resource
, res
)) {
1338 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1339 pci_domain_nr(bus
), bus
->number
, res
);
1344 /* Check for memory */
1345 for (i
= 0; i
< 3; i
++) {
1346 pres
= &hose
->mem_resources
[i
];
1347 offset
= hose
->mem_offset
[i
];
1348 if (!(pres
->flags
& IORESOURCE_MEM
))
1350 pr_debug("hose mem res: %pR\n", pres
);
1351 if ((pres
->start
- offset
) <= 0xa0000 &&
1352 (pres
->end
- offset
) >= 0xbffff)
1357 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1358 BUG_ON(res
== NULL
);
1359 res
->name
= "Legacy VGA memory";
1360 res
->flags
= IORESOURCE_MEM
;
1361 res
->start
= 0xa0000 + offset
;
1362 res
->end
= 0xbffff + offset
;
1363 pr_debug("Candidate VGA memory: %pR\n", res
);
1364 if (request_resource(pres
, res
)) {
1366 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1367 pci_domain_nr(bus
), bus
->number
, res
);
1372 void __init
pcibios_resource_survey(void)
1376 /* Allocate and assign resources */
1377 list_for_each_entry(b
, &pci_root_buses
, node
)
1378 pcibios_allocate_bus_resources(b
);
1379 pcibios_allocate_resources(0);
1380 pcibios_allocate_resources(1);
1382 /* Before we start assigning unassigned resource, we try to reserve
1383 * the low IO area and the VGA memory area if they intersect the
1384 * bus available resources to avoid allocating things on top of them
1386 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
1387 list_for_each_entry(b
, &pci_root_buses
, node
)
1388 pcibios_reserve_legacy_regions(b
);
1391 /* Now, if the platform didn't decide to blindly trust the firmware,
1392 * we proceed to assigning things that were left unassigned
1394 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
1395 pr_debug("PCI: Assigning unassigned resources...\n");
1396 pci_assign_unassigned_resources();
1399 /* Call machine dependent fixup */
1400 if (ppc_md
.pcibios_fixup
)
1401 ppc_md
.pcibios_fixup();
1404 /* This is used by the PCI hotplug driver to allocate resource
1405 * of newly plugged busses. We can try to consolidate with the
1406 * rest of the code later, for now, keep it as-is as our main
1407 * resource allocation function doesn't deal with sub-trees yet.
1409 void pcibios_claim_one_bus(struct pci_bus
*bus
)
1411 struct pci_dev
*dev
;
1412 struct pci_bus
*child_bus
;
1414 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1417 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1418 struct resource
*r
= &dev
->resource
[i
];
1420 if (r
->parent
|| !r
->start
|| !r
->flags
)
1423 pr_debug("PCI: Claiming %s: "
1424 "Resource %d: %016llx..%016llx [%x]\n",
1426 (unsigned long long)r
->start
,
1427 (unsigned long long)r
->end
,
1428 (unsigned int)r
->flags
);
1430 pci_claim_resource(dev
, i
);
1434 list_for_each_entry(child_bus
, &bus
->children
, node
)
1435 pcibios_claim_one_bus(child_bus
);
1439 /* pcibios_finish_adding_to_bus
1441 * This is to be called by the hotplug code after devices have been
1442 * added to a bus, this include calling it for a PHB that is just
1445 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1447 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1448 pci_domain_nr(bus
), bus
->number
);
1450 /* Allocate bus and devices resources */
1451 pcibios_allocate_bus_resources(bus
);
1452 pcibios_claim_one_bus(bus
);
1453 if (!pci_has_flag(PCI_PROBE_ONLY
))
1454 pci_assign_unassigned_bus_resources(bus
);
1457 eeh_add_device_tree_late(bus
);
1459 /* Add new devices to global lists. Register in proc, sysfs. */
1460 pci_bus_add_devices(bus
);
1462 /* sysfs files should only be added after devices are added */
1463 eeh_add_sysfs_files(bus
);
1465 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1467 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1469 if (ppc_md
.pcibios_enable_device_hook
)
1470 if (ppc_md
.pcibios_enable_device_hook(dev
))
1473 return pci_enable_resources(dev
, mask
);
1476 resource_size_t
pcibios_io_space_offset(struct pci_controller
*hose
)
1478 return (unsigned long) hose
->io_base_virt
- _IO_BASE
;
1481 static void pcibios_setup_phb_resources(struct pci_controller
*hose
,
1482 struct list_head
*resources
)
1484 struct resource
*res
;
1485 resource_size_t offset
;
1488 /* Hookup PHB IO resource */
1489 res
= &hose
->io_resource
;
1492 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1493 " bridge %s (domain %d)\n",
1494 hose
->dn
->full_name
, hose
->global_number
);
1496 offset
= pcibios_io_space_offset(hose
);
1498 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
1499 (unsigned long long)res
->start
,
1500 (unsigned long long)res
->end
,
1501 (unsigned long)res
->flags
,
1502 (unsigned long long)offset
);
1503 pci_add_resource_offset(resources
, res
, offset
);
1506 /* Hookup PHB Memory resources */
1507 for (i
= 0; i
< 3; ++i
) {
1508 res
= &hose
->mem_resources
[i
];
1511 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1512 "host bridge %s (domain %d)\n",
1513 hose
->dn
->full_name
, hose
->global_number
);
1516 offset
= hose
->mem_offset
[i
];
1519 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i
,
1520 (unsigned long long)res
->start
,
1521 (unsigned long long)res
->end
,
1522 (unsigned long)res
->flags
,
1523 (unsigned long long)offset
);
1525 pci_add_resource_offset(resources
, res
, offset
);
1530 * Null PCI config access functions, for the case when we can't
1533 #define NULL_PCI_OP(rw, size, type) \
1535 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1537 return PCIBIOS_DEVICE_NOT_FOUND; \
1541 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1544 return PCIBIOS_DEVICE_NOT_FOUND
;
1548 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1551 return PCIBIOS_DEVICE_NOT_FOUND
;
1554 static struct pci_ops null_pci_ops
=
1556 .read
= null_read_config
,
1557 .write
= null_write_config
,
1561 * These functions are used early on before PCI scanning is done
1562 * and all of the pci_dev and pci_bus structures have been created.
1564 static struct pci_bus
*
1565 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1567 static struct pci_bus bus
;
1570 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1574 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1578 #define EARLY_PCI_OP(rw, size, type) \
1579 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1580 int devfn, int offset, type value) \
1582 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1583 devfn, offset, value); \
1586 EARLY_PCI_OP(read
, byte
, u8
*)
1587 EARLY_PCI_OP(read
, word
, u16
*)
1588 EARLY_PCI_OP(read
, dword
, u32
*)
1589 EARLY_PCI_OP(write
, byte
, u8
)
1590 EARLY_PCI_OP(write
, word
, u16
)
1591 EARLY_PCI_OP(write
, dword
, u32
)
1593 extern int pci_bus_find_capability (struct pci_bus
*bus
, unsigned int devfn
, int cap
);
1594 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1597 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);
1600 struct device_node
*pcibios_get_phb_of_node(struct pci_bus
*bus
)
1602 struct pci_controller
*hose
= bus
->sysdata
;
1604 return of_node_get(hose
->dn
);
1608 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1609 * @hose: Pointer to the PCI host controller instance structure
1611 void pcibios_scan_phb(struct pci_controller
*hose
)
1613 LIST_HEAD(resources
);
1614 struct pci_bus
*bus
;
1615 struct device_node
*node
= hose
->dn
;
1618 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node
));
1620 /* Get some IO space for the new PHB */
1621 pcibios_setup_phb_io_space(hose
);
1623 /* Wire up PHB bus resources */
1624 pcibios_setup_phb_resources(hose
, &resources
);
1626 hose
->busn
.start
= hose
->first_busno
;
1627 hose
->busn
.end
= hose
->last_busno
;
1628 hose
->busn
.flags
= IORESOURCE_BUS
;
1629 pci_add_resource(&resources
, &hose
->busn
);
1631 /* Create an empty bus for the toplevel */
1632 bus
= pci_create_root_bus(hose
->parent
, hose
->first_busno
,
1633 hose
->ops
, hose
, &resources
);
1635 pr_err("Failed to create bus for PCI domain %04x\n",
1636 hose
->global_number
);
1637 pci_free_resource_list(&resources
);
1642 /* Get probe mode and perform scan */
1643 mode
= PCI_PROBE_NORMAL
;
1644 if (node
&& ppc_md
.pci_probe_mode
)
1645 mode
= ppc_md
.pci_probe_mode(bus
);
1646 pr_debug(" probe mode: %d\n", mode
);
1647 if (mode
== PCI_PROBE_DEVTREE
)
1648 of_scan_bus(node
, bus
);
1650 if (mode
== PCI_PROBE_NORMAL
) {
1651 pci_bus_update_busn_res_end(bus
, 255);
1652 hose
->last_busno
= pci_scan_child_bus(bus
);
1653 pci_bus_update_busn_res_end(bus
, hose
->last_busno
);
1656 /* Platform gets a chance to do some global fixups before
1657 * we proceed to resource allocation
1659 if (ppc_md
.pcibios_fixup_phb
)
1660 ppc_md
.pcibios_fixup_phb(hose
);
1662 /* Configure PCI Express settings */
1663 if (bus
&& !pci_has_flag(PCI_PROBE_ONLY
)) {
1664 struct pci_bus
*child
;
1665 list_for_each_entry(child
, &bus
->children
, node
)
1666 pcie_bus_configure_settings(child
);
1670 static void fixup_hide_host_resource_fsl(struct pci_dev
*dev
)
1672 int i
, class = dev
->class >> 8;
1673 /* When configured as agent, programing interface = 1 */
1674 int prog_if
= dev
->class & 0xf;
1676 if ((class == PCI_CLASS_PROCESSOR_POWERPC
||
1677 class == PCI_CLASS_BRIDGE_OTHER
) &&
1678 (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) &&
1680 (dev
->bus
->parent
== NULL
)) {
1681 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
1682 dev
->resource
[i
].start
= 0;
1683 dev
->resource
[i
].end
= 0;
1684 dev
->resource
[i
].flags
= 0;
1688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);
1689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
, fixup_hide_host_resource_fsl
);
1691 static void fixup_vga(struct pci_dev
*pdev
)
1695 pci_read_config_word(pdev
, PCI_COMMAND
, &cmd
);
1696 if ((cmd
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
)) || !vga_default_device())
1697 vga_set_default_device(pdev
);
1700 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
1701 PCI_CLASS_DISPLAY_VGA
, 8, fixup_vga
);