2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
27 #include <linux/list.h>
28 #include <linux/syscalls.h>
29 #include <linux/irq.h>
30 #include <linux/vmalloc.h>
32 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
37 #include <asm/machdep.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/firmware.h>
42 static DEFINE_SPINLOCK(hose_spinlock
);
44 /* XXX kill that some day ... */
45 static int global_phb_number
; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base
;
50 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
51 unsigned int ppc_pci_flags
= 0;
54 static struct dma_mapping_ops
*pci_dma_ops
;
56 void set_pci_dma_ops(struct dma_mapping_ops
*dma_ops
)
58 pci_dma_ops
= dma_ops
;
61 struct dma_mapping_ops
*get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops
);
67 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
69 return dma_set_mask(&dev
->dev
, mask
);
72 int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
76 rc
= dma_set_mask(&dev
->dev
, mask
);
77 dev
->dev
.coherent_dma_mask
= dev
->dma_mask
;
82 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
84 struct pci_controller
*phb
;
86 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
89 spin_lock(&hose_spinlock
);
90 phb
->global_number
= global_phb_number
++;
91 list_add_tail(&phb
->list_node
, &hose_list
);
92 spin_unlock(&hose_spinlock
);
94 phb
->is_dynamic
= mem_init_done
;
97 int nid
= of_node_to_nid(dev
);
99 if (nid
< 0 || !node_online(nid
))
102 PHB_SET_NODE(phb
, nid
);
108 void pcibios_free_controller(struct pci_controller
*phb
)
110 spin_lock(&hose_spinlock
);
111 list_del(&phb
->list_node
);
112 spin_unlock(&hose_spinlock
);
118 int pcibios_vaddr_is_ioport(void __iomem
*address
)
121 struct pci_controller
*hose
;
124 spin_lock(&hose_spinlock
);
125 list_for_each_entry(hose
, &hose_list
, list_node
) {
127 size
= hose
->pci_io_size
;
129 size
= hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
131 if (address
>= hose
->io_base_virt
&&
132 address
< (hose
->io_base_virt
+ size
)) {
137 spin_unlock(&hose_spinlock
);
142 * Return the domain number for this bus.
144 int pci_domain_nr(struct pci_bus
*bus
)
146 struct pci_controller
*hose
= pci_bus_to_host(bus
);
148 return hose
->global_number
;
150 EXPORT_SYMBOL(pci_domain_nr
);
154 /* This routine is meant to be used early during boot, when the
155 * PCI bus numbers have not yet been assigned, and you need to
156 * issue PCI config cycles to an OF device.
157 * It could also be used to "fix" RTAS config cycles if you want
158 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
161 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
164 struct pci_controller
*hose
, *tmp
;
165 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
166 if (hose
->dn
== node
)
173 static ssize_t
pci_show_devspec(struct device
*dev
,
174 struct device_attribute
*attr
, char *buf
)
176 struct pci_dev
*pdev
;
177 struct device_node
*np
;
179 pdev
= to_pci_dev (dev
);
180 np
= pci_device_to_OF_node(pdev
);
181 if (np
== NULL
|| np
->full_name
== NULL
)
183 return sprintf(buf
, "%s", np
->full_name
);
185 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
186 #endif /* CONFIG_PPC_OF */
188 /* Add sysfs properties */
189 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
192 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
195 #endif /* CONFIG_PPC_OF */
199 char __devinit
*pcibios_setup(char *str
)
205 * Reads the interrupt pin to determine if interrupt is use by card.
206 * If the interrupt is used, then gets the interrupt line from the
207 * openfirmware and sets it in the pci_dev and pci_config line.
209 int pci_read_irq_line(struct pci_dev
*pci_dev
)
214 /* The current device-tree that iSeries generates from the HV
215 * PCI informations doesn't contain proper interrupt routing,
216 * and all the fallback would do is print out crap, so we
217 * don't attempt to resolve the interrupts here at all, some
218 * iSeries specific fixup does it.
220 * In the long run, we will hopefully fix the generated device-tree
223 #ifdef CONFIG_PPC_ISERIES
224 if (firmware_has_feature(FW_FEATURE_ISERIES
))
228 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
231 memset(&oirq
, 0xff, sizeof(oirq
));
233 /* Try to get a mapping from the device-tree */
234 if (of_irq_map_pci(pci_dev
, &oirq
)) {
237 /* If that fails, lets fallback to what is in the config
238 * space and map that through the default controller. We
239 * also set the type to level low since that's what PCI
240 * interrupts are. If your platform does differently, then
241 * either provide a proper interrupt tree or don't use this
244 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
248 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
249 line
== 0xff || line
== 0) {
252 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
255 virq
= irq_create_mapping(NULL
, line
);
257 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
259 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
260 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
261 oirq
.controller
->full_name
);
263 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
267 pr_debug(" Failed to map !\n");
271 pr_debug(" Mapped to linux irq %d\n", virq
);
277 EXPORT_SYMBOL(pci_read_irq_line
);
280 * Platform support for /proc/bus/pci/X/Y mmap()s,
281 * modelled on the sparc64 implementation by Dave Miller.
286 * Adjust vm_pgoff of VMA such that it is the physical page offset
287 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
289 * Basically, the user finds the base address for his device which he wishes
290 * to mmap. They read the 32-bit value from the config space base register,
291 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
292 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
294 * Returns negative error code on failure, zero on success.
296 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
297 resource_size_t
*offset
,
298 enum pci_mmap_state mmap_state
)
300 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
301 unsigned long io_offset
= 0;
305 return NULL
; /* should never happen */
307 /* If memory, add on the PCI bridge address offset */
308 if (mmap_state
== pci_mmap_mem
) {
309 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
310 *offset
+= hose
->pci_mem_offset
;
312 res_bit
= IORESOURCE_MEM
;
314 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
315 *offset
+= io_offset
;
316 res_bit
= IORESOURCE_IO
;
320 * Check that the offset requested corresponds to one of the
321 * resources of the device.
323 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
324 struct resource
*rp
= &dev
->resource
[i
];
325 int flags
= rp
->flags
;
327 /* treat ROM as memory (should be already) */
328 if (i
== PCI_ROM_RESOURCE
)
329 flags
|= IORESOURCE_MEM
;
331 /* Active and same type? */
332 if ((flags
& res_bit
) == 0)
335 /* In the range of this resource? */
336 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
339 /* found it! construct the final physical address */
340 if (mmap_state
== pci_mmap_io
)
341 *offset
+= hose
->io_base_phys
- io_offset
;
349 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
352 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
354 enum pci_mmap_state mmap_state
,
357 unsigned long prot
= pgprot_val(protection
);
359 /* Write combine is always 0 on non-memory space mappings. On
360 * memory space, if the user didn't pass 1, we check for a
361 * "prefetchable" resource. This is a bit hackish, but we use
362 * this to workaround the inability of /sysfs to provide a write
365 if (mmap_state
!= pci_mmap_mem
)
367 else if (write_combine
== 0) {
368 if (rp
->flags
& IORESOURCE_PREFETCH
)
372 /* XXX would be nice to have a way to ask for write-through */
374 return pgprot_noncached_wc(prot
);
376 return pgprot_noncached(prot
);
380 * This one is used by /dev/mem and fbdev who have no clue about the
381 * PCI device, it tries to find the PCI device first and calls the
384 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
389 struct pci_dev
*pdev
= NULL
;
390 struct resource
*found
= NULL
;
391 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
394 if (page_is_ram(pfn
))
397 prot
= pgprot_noncached(prot
);
398 for_each_pci_dev(pdev
) {
399 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
400 struct resource
*rp
= &pdev
->resource
[i
];
401 int flags
= rp
->flags
;
403 /* Active and same type? */
404 if ((flags
& IORESOURCE_MEM
) == 0)
406 /* In the range of this resource? */
407 if (offset
< (rp
->start
& PAGE_MASK
) ||
417 if (found
->flags
& IORESOURCE_PREFETCH
)
418 prot
= pgprot_noncached_wc(prot
);
422 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
423 (unsigned long long)offset
, pgprot_val(prot
));
430 * Perform the actual remap of the pages for a PCI device mapping, as
431 * appropriate for this architecture. The region in the process to map
432 * is described by vm_start and vm_end members of VMA, the base physical
433 * address is found in vm_pgoff.
434 * The pci device structure is provided so that architectures may make mapping
435 * decisions on a per-device or per-bus basis.
437 * Returns a negative error code on failure, zero on success.
439 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
440 enum pci_mmap_state mmap_state
, int write_combine
)
442 resource_size_t offset
=
443 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
447 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
451 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
452 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
454 mmap_state
, write_combine
);
456 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
457 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
462 /* This provides legacy IO read access on a bus */
463 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
465 unsigned long offset
;
466 struct pci_controller
*hose
= pci_bus_to_host(bus
);
467 struct resource
*rp
= &hose
->io_resource
;
470 /* Check if port can be supported by that bus. We only check
471 * the ranges of the PHB though, not the bus itself as the rules
472 * for forwarding legacy cycles down bridges are not our problem
473 * here. So if the host bridge supports it, we do it.
475 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
478 if (!(rp
->flags
& IORESOURCE_IO
))
480 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
482 addr
= hose
->io_base_virt
+ port
;
486 *((u8
*)val
) = in_8(addr
);
491 *((u16
*)val
) = in_le16(addr
);
496 *((u32
*)val
) = in_le32(addr
);
502 /* This provides legacy IO write access on a bus */
503 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
505 unsigned long offset
;
506 struct pci_controller
*hose
= pci_bus_to_host(bus
);
507 struct resource
*rp
= &hose
->io_resource
;
510 /* Check if port can be supported by that bus. We only check
511 * the ranges of the PHB though, not the bus itself as the rules
512 * for forwarding legacy cycles down bridges are not our problem
513 * here. So if the host bridge supports it, we do it.
515 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
518 if (!(rp
->flags
& IORESOURCE_IO
))
520 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
522 addr
= hose
->io_base_virt
+ port
;
524 /* WARNING: The generic code is idiotic. It gets passed a pointer
525 * to what can be a 1, 2 or 4 byte quantity and always reads that
526 * as a u32, which means that we have to correct the location of
527 * the data read within those 32 bits for size 1 and 2
531 out_8(addr
, val
>> 24);
536 out_le16(addr
, val
>> 16);
547 /* This provides legacy IO or memory mmap access on a bus */
548 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
549 struct vm_area_struct
*vma
,
550 enum pci_mmap_state mmap_state
)
552 struct pci_controller
*hose
= pci_bus_to_host(bus
);
553 resource_size_t offset
=
554 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
555 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
558 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
559 pci_domain_nr(bus
), bus
->number
,
560 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
561 (unsigned long long)offset
,
562 (unsigned long long)(offset
+ size
- 1));
564 if (mmap_state
== pci_mmap_mem
) {
565 if ((offset
+ size
) > hose
->isa_mem_size
)
567 offset
+= hose
->isa_mem_phys
;
569 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
570 unsigned long roffset
= offset
+ io_offset
;
571 rp
= &hose
->io_resource
;
572 if (!(rp
->flags
& IORESOURCE_IO
))
574 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
576 offset
+= hose
->io_base_phys
;
578 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
580 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
581 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
582 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
583 vma
->vm_end
- vma
->vm_start
,
587 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
588 const struct resource
*rsrc
,
589 resource_size_t
*start
, resource_size_t
*end
)
591 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
592 resource_size_t offset
= 0;
597 if (rsrc
->flags
& IORESOURCE_IO
)
598 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
600 /* We pass a fully fixed up address to userland for MMIO instead of
601 * a BAR value because X is lame and expects to be able to use that
602 * to pass to /dev/mem !
604 * That means that we'll have potentially 64 bits values where some
605 * userland apps only expect 32 (like X itself since it thinks only
606 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
609 * Hopefully, the sysfs insterface is immune to that gunk. Once X
610 * has been fixed (and the fix spread enough), we can re-enable the
611 * 2 lines below and pass down a BAR value to userland. In that case
612 * we'll also have to re-enable the matching code in
613 * __pci_mmap_make_offset().
618 else if (rsrc
->flags
& IORESOURCE_MEM
)
619 offset
= hose
->pci_mem_offset
;
622 *start
= rsrc
->start
- offset
;
623 *end
= rsrc
->end
- offset
;
627 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
628 * @hose: newly allocated pci_controller to be setup
629 * @dev: device node of the host bridge
630 * @primary: set if primary bus (32 bits only, soon to be deprecated)
632 * This function will parse the "ranges" property of a PCI host bridge device
633 * node and setup the resource mapping of a pci controller based on its
636 * Life would be boring if it wasn't for a few issues that we have to deal
639 * - We can only cope with one IO space range and up to 3 Memory space
640 * ranges. However, some machines (thanks Apple !) tend to split their
641 * space into lots of small contiguous ranges. So we have to coalesce.
643 * - We can only cope with all memory ranges having the same offset
644 * between CPU addresses and PCI addresses. Unfortunately, some bridges
645 * are setup for a large 1:1 mapping along with a small "window" which
646 * maps PCI address 0 to some arbitrary high address of the CPU space in
647 * order to give access to the ISA memory hole.
648 * The way out of here that I've chosen for now is to always set the
649 * offset based on the first resource found, then override it if we
650 * have a different offset and the previous was set by an ISA hole.
652 * - Some busses have IO space not starting at 0, which causes trouble with
653 * the way we do our IO resource renumbering. The code somewhat deals with
654 * it for 64 bits but I would expect problems on 32 bits.
656 * - Some 32 bits platforms such as 4xx can have physical space larger than
657 * 32 bits so we need to use 64 bits values for the parsing
659 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
660 struct device_node
*dev
,
665 int pna
= of_n_addr_cells(dev
);
667 int memno
= 0, isa_hole
= -1;
669 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
670 unsigned long long isa_mb
= 0;
671 struct resource
*res
;
673 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
674 dev
->full_name
, primary
? "(primary)" : "");
676 /* Get ranges property */
677 ranges
= of_get_property(dev
, "ranges", &rlen
);
682 while ((rlen
-= np
* 4) >= 0) {
683 /* Read next ranges element */
684 pci_space
= ranges
[0];
685 pci_addr
= of_read_number(ranges
+ 1, 2);
686 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
687 size
= of_read_number(ranges
+ pna
+ 3, 2);
690 /* If we failed translation or got a zero-sized region
691 * (some FW try to feed us with non sensical zero sized regions
692 * such as power3 which look like some kind of attempt at exposing
693 * the VGA memory hole)
695 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
698 /* Now consume following elements while they are contiguous */
699 for (; rlen
>= np
* sizeof(u32
);
700 ranges
+= np
, rlen
-= np
* 4) {
701 if (ranges
[0] != pci_space
)
703 pci_next
= of_read_number(ranges
+ 1, 2);
704 cpu_next
= of_translate_address(dev
, ranges
+ 3);
705 if (pci_next
!= pci_addr
+ size
||
706 cpu_next
!= cpu_addr
+ size
)
708 size
+= of_read_number(ranges
+ pna
+ 3, 2);
711 /* Act based on address space type */
713 switch ((pci_space
>> 24) & 0x3) {
714 case 1: /* PCI IO space */
716 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
717 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
719 /* We support only one IO range */
720 if (hose
->pci_io_size
) {
722 " \\--> Skipped (too many) !\n");
726 /* On 32 bits, limit I/O space to 16MB */
727 if (size
> 0x01000000)
730 /* 32 bits needs to map IOs here */
731 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
733 /* Expect trouble if pci_addr is not 0 */
736 (unsigned long)hose
->io_base_virt
;
737 #endif /* CONFIG_PPC32 */
738 /* pci_io_size and io_base_phys always represent IO
739 * space starting at 0 so we factor in pci_addr
741 hose
->pci_io_size
= pci_addr
+ size
;
742 hose
->io_base_phys
= cpu_addr
- pci_addr
;
745 res
= &hose
->io_resource
;
746 res
->flags
= IORESOURCE_IO
;
747 res
->start
= pci_addr
;
749 case 2: /* PCI Memory space */
750 case 3: /* PCI 64 bits Memory space */
752 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
753 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
754 (pci_space
& 0x40000000) ? "Prefetch" : "");
756 /* We support only 3 memory ranges */
759 " \\--> Skipped (too many) !\n");
762 /* Handles ISA memory hole space here */
766 if (primary
|| isa_mem_base
== 0)
767 isa_mem_base
= cpu_addr
;
768 hose
->isa_mem_phys
= cpu_addr
;
769 hose
->isa_mem_size
= size
;
772 /* We get the PCI/Mem offset from the first range or
773 * the, current one if the offset came from an ISA
774 * hole. If they don't match, bugger.
777 (isa_hole
>= 0 && pci_addr
!= 0 &&
778 hose
->pci_mem_offset
== isa_mb
))
779 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
780 else if (pci_addr
!= 0 &&
781 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
783 " \\--> Skipped (offset mismatch) !\n");
788 res
= &hose
->mem_resources
[memno
++];
789 res
->flags
= IORESOURCE_MEM
;
790 if (pci_space
& 0x40000000)
791 res
->flags
|= IORESOURCE_PREFETCH
;
792 res
->start
= cpu_addr
;
796 res
->name
= dev
->full_name
;
797 res
->end
= res
->start
+ size
- 1;
804 /* If there's an ISA hole and the pci_mem_offset is -not- matching
805 * the ISA hole offset, then we need to remove the ISA hole from
806 * the resource list for that brige
808 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
809 unsigned int next
= isa_hole
+ 1;
810 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
812 memmove(&hose
->mem_resources
[isa_hole
],
813 &hose
->mem_resources
[next
],
814 sizeof(struct resource
) * (memno
- next
));
815 hose
->mem_resources
[--memno
].flags
= 0;
819 /* Decide whether to display the domain number in /proc */
820 int pci_proc_domain(struct pci_bus
*bus
)
822 struct pci_controller
*hose
= pci_bus_to_host(bus
);
824 if (!(ppc_pci_flags
& PPC_PCI_ENABLE_PROC_DOMAINS
))
826 if (ppc_pci_flags
& PPC_PCI_COMPAT_DOMAIN_0
)
827 return hose
->global_number
!= 0;
831 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
832 struct resource
*res
)
834 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
835 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
839 if (res
->flags
& IORESOURCE_IO
) {
840 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
842 } else if (res
->flags
& IORESOURCE_MEM
)
843 offset
= hose
->pci_mem_offset
;
845 region
->start
= (res
->start
- offset
) & mask
;
846 region
->end
= (res
->end
- offset
) & mask
;
848 EXPORT_SYMBOL(pcibios_resource_to_bus
);
850 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
851 struct pci_bus_region
*region
)
853 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
854 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
858 if (res
->flags
& IORESOURCE_IO
) {
859 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
861 } else if (res
->flags
& IORESOURCE_MEM
)
862 offset
= hose
->pci_mem_offset
;
863 res
->start
= (region
->start
+ offset
) & mask
;
864 res
->end
= (region
->end
+ offset
) & mask
;
866 EXPORT_SYMBOL(pcibios_bus_to_resource
);
868 /* Fixup a bus resource into a linux resource */
869 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
871 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
872 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
874 if (res
->flags
& IORESOURCE_IO
) {
875 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
877 } else if (res
->flags
& IORESOURCE_MEM
)
878 offset
= hose
->pci_mem_offset
;
880 res
->start
= (res
->start
+ offset
) & mask
;
881 res
->end
= (res
->end
+ offset
) & mask
;
885 /* This header fixup will do the resource fixup for all devices as they are
886 * probed, but not for bridge ranges
888 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
890 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
894 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
898 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
899 struct resource
*res
= dev
->resource
+ i
;
902 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
903 * consider 0 as an unassigned BAR value. It's technically
904 * a valid value, but linux doesn't like it... so when we can
905 * re-assign things, we do so, but if we can't, we keep it
906 * around and hope for the best...
908 if (res
->start
== 0 && !(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
909 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
911 (unsigned long long)res
->start
,
912 (unsigned long long)res
->end
,
913 (unsigned int)res
->flags
);
914 res
->end
-= res
->start
;
916 res
->flags
|= IORESOURCE_UNSET
;
920 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
922 (unsigned long long)res
->start
,\
923 (unsigned long long)res
->end
,
924 (unsigned int)res
->flags
);
926 fixup_resource(res
, dev
);
928 pr_debug("PCI:%s %016llx-%016llx\n",
930 (unsigned long long)res
->start
,
931 (unsigned long long)res
->end
);
934 /* Call machine specific resource fixup */
935 if (ppc_md
.pcibios_fixup_resources
)
936 ppc_md
.pcibios_fixup_resources(dev
);
938 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
940 /* This function tries to figure out if a bridge resource has been initialized
941 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
942 * things go more smoothly when it gets it right. It should covers cases such
943 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
945 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
946 struct resource
*res
)
948 struct pci_controller
*hose
= pci_bus_to_host(bus
);
949 struct pci_dev
*dev
= bus
->self
;
950 resource_size_t offset
;
954 /* We don't do anything if PCI_PROBE_ONLY is set */
955 if (ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)
958 /* Job is a bit different between memory and IO */
959 if (res
->flags
& IORESOURCE_MEM
) {
960 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
961 * initialized by somebody
963 if (res
->start
!= hose
->pci_mem_offset
)
966 /* The BAR is 0, let's check if memory decoding is enabled on
967 * the bridge. If not, we consider it unassigned
969 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
970 if ((command
& PCI_COMMAND_MEMORY
) == 0)
973 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
974 * resources covers that starting address (0 then it's good enough for
977 for (i
= 0; i
< 3; i
++) {
978 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
979 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
983 /* Well, it starts at 0 and we know it will collide so we may as
984 * well consider it as unassigned. That covers the Apple case.
988 /* If the BAR is non-0, then we consider it assigned */
989 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
990 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
993 /* Here, we are a bit different than memory as typically IO space
994 * starting at low addresses -is- valid. What we do instead if that
995 * we consider as unassigned anything that doesn't have IO enabled
996 * in the PCI command register, and that's it.
998 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
999 if (command
& PCI_COMMAND_IO
)
1002 /* It's starting at 0 and IO is disabled in the bridge, consider
1009 /* Fixup resources of a PCI<->PCI bridge */
1010 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1012 struct resource
*res
;
1015 struct pci_dev
*dev
= bus
->self
;
1017 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1018 if ((res
= bus
->resource
[i
]) == NULL
)
1022 if (i
>= 3 && bus
->self
->transparent
)
1025 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1027 (unsigned long long)res
->start
,\
1028 (unsigned long long)res
->end
,
1029 (unsigned int)res
->flags
);
1032 fixup_resource(res
, dev
);
1034 /* Try to detect uninitialized P2P bridge resources,
1035 * and clear them out so they get re-assigned later
1037 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1039 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
1042 pr_debug("PCI:%s %016llx-%016llx\n",
1044 (unsigned long long)res
->start
,
1045 (unsigned long long)res
->end
);
1050 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
1052 /* Fix up the bus resources for P2P bridges */
1053 if (bus
->self
!= NULL
)
1054 pcibios_fixup_bridge(bus
);
1056 /* Platform specific bus fixups. This is currently only used
1057 * by fsl_pci and I'm hoping to get rid of it at some point
1059 if (ppc_md
.pcibios_fixup_bus
)
1060 ppc_md
.pcibios_fixup_bus(bus
);
1062 /* Setup bus DMA mappings */
1063 if (ppc_md
.pci_dma_bus_setup
)
1064 ppc_md
.pci_dma_bus_setup(bus
);
1067 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1069 struct pci_dev
*dev
;
1071 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1072 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1074 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1075 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
1077 /* Setup OF node pointer in archdata */
1078 sd
->of_node
= pci_device_to_OF_node(dev
);
1080 /* Fixup NUMA node as it may not be setup yet by the generic
1081 * code and is needed by the DMA init
1083 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1085 /* Hook up default DMA ops */
1086 sd
->dma_ops
= pci_dma_ops
;
1087 sd
->dma_data
= (void *)PCI_DRAM_OFFSET
;
1089 /* Additional platform DMA/iommu setup */
1090 if (ppc_md
.pci_dma_dev_setup
)
1091 ppc_md
.pci_dma_dev_setup(dev
);
1093 /* Read default IRQs and fixup if necessary */
1094 pci_read_irq_line(dev
);
1095 if (ppc_md
.pci_irq_fixup
)
1096 ppc_md
.pci_irq_fixup(dev
);
1100 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1102 /* When called from the generic PCI probe, read PCI<->PCI bridge
1103 * bases. This is -not- called when generating the PCI tree from
1104 * the OF device-tree.
1106 if (bus
->self
!= NULL
)
1107 pci_read_bridge_bases(bus
);
1109 /* Now fixup the bus bus */
1110 pcibios_setup_bus_self(bus
);
1112 /* Now fixup devices on that bus */
1113 pcibios_setup_bus_devices(bus
);
1115 EXPORT_SYMBOL(pcibios_fixup_bus
);
1117 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1119 if ((ppc_pci_flags
& PPC_PCI_CAN_SKIP_ISA_ALIGN
) &&
1120 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1126 * We need to avoid collisions with `mirrored' VGA ports
1127 * and other strange ISA hardware, so we always want the
1128 * addresses to be allocated in the 0x000-0x0ff region
1131 * Why? Because some silly external IO cards only decode
1132 * the low 10 bits of the IO address. The 0x00-0xff region
1133 * is reserved for motherboard devices that decode all 16
1134 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1135 * but we want to try to avoid allocating at 0x2900-0x2bff
1136 * which might have be mirrored at 0x0100-0x03ff..
1138 void pcibios_align_resource(void *data
, struct resource
*res
,
1139 resource_size_t size
, resource_size_t align
)
1141 struct pci_dev
*dev
= data
;
1143 if (res
->flags
& IORESOURCE_IO
) {
1144 resource_size_t start
= res
->start
;
1146 if (skip_isa_ioresource_align(dev
))
1148 if (start
& 0x300) {
1149 start
= (start
+ 0x3ff) & ~0x3ff;
1154 EXPORT_SYMBOL(pcibios_align_resource
);
1157 * Reparent resource children of pr that conflict with res
1158 * under res, and make res replace those children.
1160 static int __init
reparent_resources(struct resource
*parent
,
1161 struct resource
*res
)
1163 struct resource
*p
, **pp
;
1164 struct resource
**firstpp
= NULL
;
1166 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1167 if (p
->end
< res
->start
)
1169 if (res
->end
< p
->start
)
1171 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1172 return -1; /* not completely contained */
1173 if (firstpp
== NULL
)
1176 if (firstpp
== NULL
)
1177 return -1; /* didn't find any conflicting entries? */
1178 res
->parent
= parent
;
1179 res
->child
= *firstpp
;
1183 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1185 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1187 (unsigned long long)p
->start
,
1188 (unsigned long long)p
->end
, res
->name
);
1194 * Handle resources of PCI devices. If the world were perfect, we could
1195 * just allocate all the resource regions and do nothing more. It isn't.
1196 * On the other hand, we cannot just re-allocate all devices, as it would
1197 * require us to know lots of host bridge internals. So we attempt to
1198 * keep as much of the original configuration as possible, but tweak it
1199 * when it's found to be wrong.
1201 * Known BIOS problems we have to work around:
1202 * - I/O or memory regions not configured
1203 * - regions configured, but not enabled in the command register
1204 * - bogus I/O addresses above 64K used
1205 * - expansion ROMs left enabled (this may sound harmless, but given
1206 * the fact the PCI specs explicitly allow address decoders to be
1207 * shared between expansion ROMs and other resource regions, it's
1208 * at least dangerous)
1211 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1212 * This gives us fixed barriers on where we can allocate.
1213 * (2) Allocate resources for all enabled devices. If there is
1214 * a collision, just mark the resource as unallocated. Also
1215 * disable expansion ROMs during this step.
1216 * (3) Try to allocate resources for disabled devices. If the
1217 * resources were assigned correctly, everything goes well,
1218 * if they weren't, they won't disturb allocation of other
1220 * (4) Assign new addresses to resources which were either
1221 * not configured at all or misconfigured. If explicitly
1222 * requested by the user, configure expansion ROM address
1226 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1230 struct resource
*res
, *pr
;
1232 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1233 pci_domain_nr(bus
), bus
->number
);
1235 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1236 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
1237 || res
->start
> res
->end
|| res
->parent
)
1239 if (bus
->parent
== NULL
)
1240 pr
= (res
->flags
& IORESOURCE_IO
) ?
1241 &ioport_resource
: &iomem_resource
;
1243 /* Don't bother with non-root busses when
1244 * re-assigning all resources. We clear the
1245 * resource flags as if they were colliding
1246 * and as such ensure proper re-allocation
1249 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)
1250 goto clear_resource
;
1251 pr
= pci_find_parent_resource(bus
->self
, res
);
1253 /* this happens when the generic PCI
1254 * code (wrongly) decides that this
1255 * bridge is transparent -- paulus
1261 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1262 "[0x%x], parent %p (%s)\n",
1263 bus
->self
? pci_name(bus
->self
) : "PHB",
1265 (unsigned long long)res
->start
,
1266 (unsigned long long)res
->end
,
1267 (unsigned int)res
->flags
,
1268 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1270 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1271 if (request_resource(pr
, res
) == 0)
1274 * Must be a conflict with an existing entry.
1275 * Move that entry (or entries) under the
1276 * bridge resource and try again.
1278 if (reparent_resources(pr
, res
) == 0)
1281 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1282 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1287 list_for_each_entry(b
, &bus
->children
, node
)
1288 pcibios_allocate_bus_resources(b
);
1291 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1293 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1295 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1297 (unsigned long long)r
->start
,
1298 (unsigned long long)r
->end
,
1299 (unsigned int)r
->flags
);
1301 pr
= pci_find_parent_resource(dev
, r
);
1302 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1303 request_resource(pr
, r
) < 0) {
1304 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1305 " of device %s, will remap\n", idx
, pci_name(dev
));
1307 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1309 (unsigned long long)pr
->start
,
1310 (unsigned long long)pr
->end
,
1311 (unsigned int)pr
->flags
);
1312 /* We'll assign a new address later */
1313 r
->flags
|= IORESOURCE_UNSET
;
1319 static void __init
pcibios_allocate_resources(int pass
)
1321 struct pci_dev
*dev
= NULL
;
1326 for_each_pci_dev(dev
) {
1327 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1328 for (idx
= 0; idx
< 6; idx
++) {
1329 r
= &dev
->resource
[idx
];
1330 if (r
->parent
) /* Already allocated */
1332 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1333 continue; /* Not assigned at all */
1334 if (r
->flags
& IORESOURCE_IO
)
1335 disabled
= !(command
& PCI_COMMAND_IO
);
1337 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1338 if (pass
== disabled
)
1339 alloc_resource(dev
, idx
);
1343 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1344 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
1345 /* Turn the ROM off, leave the resource region,
1346 * but keep it unregistered.
1349 pr_debug("PCI: Switching off ROM of %s\n",
1351 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1352 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1353 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1354 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1359 void __init
pcibios_resource_survey(void)
1363 /* Allocate and assign resources. If we re-assign everything, then
1364 * we skip the allocate phase
1366 list_for_each_entry(b
, &pci_root_buses
, node
)
1367 pcibios_allocate_bus_resources(b
);
1369 if (!(ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)) {
1370 pcibios_allocate_resources(0);
1371 pcibios_allocate_resources(1);
1374 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1375 pr_debug("PCI: Assigning unassigned resouces...\n");
1376 pci_assign_unassigned_resources();
1379 /* Call machine dependent fixup */
1380 if (ppc_md
.pcibios_fixup
)
1381 ppc_md
.pcibios_fixup();
1384 #ifdef CONFIG_HOTPLUG
1386 /* This is used by the PCI hotplug driver to allocate resource
1387 * of newly plugged busses. We can try to consolidate with the
1388 * rest of the code later, for now, keep it as-is as our main
1389 * resource allocation function doesn't deal with sub-trees yet.
1391 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1393 struct pci_dev
*dev
;
1394 struct pci_bus
*child_bus
;
1396 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1399 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1400 struct resource
*r
= &dev
->resource
[i
];
1402 if (r
->parent
|| !r
->start
|| !r
->flags
)
1405 pr_debug("PCI: Claiming %s: "
1406 "Resource %d: %016llx..%016llx [%x]\n",
1408 (unsigned long long)r
->start
,
1409 (unsigned long long)r
->end
,
1410 (unsigned int)r
->flags
);
1412 pci_claim_resource(dev
, i
);
1416 list_for_each_entry(child_bus
, &bus
->children
, node
)
1417 pcibios_claim_one_bus(child_bus
);
1419 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1422 /* pcibios_finish_adding_to_bus
1424 * This is to be called by the hotplug code after devices have been
1425 * added to a bus, this include calling it for a PHB that is just
1428 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1430 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1431 pci_domain_nr(bus
), bus
->number
);
1433 /* Allocate bus and devices resources */
1434 pcibios_allocate_bus_resources(bus
);
1435 pcibios_claim_one_bus(bus
);
1437 /* Add new devices to global lists. Register in proc, sysfs. */
1438 pci_bus_add_devices(bus
);
1441 eeh_add_device_tree_late(bus
);
1443 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1445 #endif /* CONFIG_HOTPLUG */
1447 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1449 if (ppc_md
.pcibios_enable_device_hook
)
1450 if (ppc_md
.pcibios_enable_device_hook(dev
))
1453 return pci_enable_resources(dev
, mask
);
1456 void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
)
1458 struct pci_bus
*bus
= hose
->bus
;
1459 struct resource
*res
;
1462 /* Hookup PHB IO resource */
1463 bus
->resource
[0] = res
= &hose
->io_resource
;
1466 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1467 " bridge %s (domain %d)\n",
1468 hose
->dn
->full_name
, hose
->global_number
);
1470 /* Workaround for lack of IO resource only on 32-bit */
1471 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1472 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1473 res
->flags
= IORESOURCE_IO
;
1474 #endif /* CONFIG_PPC32 */
1477 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1478 (unsigned long long)res
->start
,
1479 (unsigned long long)res
->end
,
1480 (unsigned long)res
->flags
);
1482 /* Hookup PHB Memory resources */
1483 for (i
= 0; i
< 3; ++i
) {
1484 res
= &hose
->mem_resources
[i
];
1488 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1489 "host bridge %s (domain %d)\n",
1490 hose
->dn
->full_name
, hose
->global_number
);
1492 /* Workaround for lack of MEM resource only on 32-bit */
1493 res
->start
= hose
->pci_mem_offset
;
1494 res
->end
= (resource_size_t
)-1LL;
1495 res
->flags
= IORESOURCE_MEM
;
1496 #endif /* CONFIG_PPC32 */
1498 bus
->resource
[i
+1] = res
;
1500 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i
,
1501 (unsigned long long)res
->start
,
1502 (unsigned long long)res
->end
,
1503 (unsigned long)res
->flags
);
1506 pr_debug("PCI: PHB MEM offset = %016llx\n",
1507 (unsigned long long)hose
->pci_mem_offset
);
1508 pr_debug("PCI: PHB IO offset = %08lx\n",
1509 (unsigned long)hose
->io_base_virt
- _IO_BASE
);