arch/powerpc/kernel/pci-common.c

   1 /*
   2  * Contains common pci routines for ALL ppc platform
   3  * (based on pci_32.c and pci_64.c)
   4  *
   5  * Port for PPC64 David Engebretsen, IBM Corp.
   6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   7  *
   8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *   Rework, based on alpha PCI code.
  10  *
  11  * Common pmac/prep/chrp pci routines. -- Cort
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version
  16  * 2 of the License, or (at your option) any later version.
  17  */
  18
  19 #undef DEBUG
  20
  21 #include <linux/kernel.h>
  22 #include <linux/pci.h>
  23 #include <linux/string.h>
  24 #include <linux/init.h>
  25 #include <linux/bootmem.h>
  26 #include <linux/mm.h>
  27 #include <linux/list.h>
  28 #include <linux/syscalls.h>
  29 #include <linux/irq.h>
  30 #include <linux/vmalloc.h>
  31
  32 #include <asm/processor.h>
  33 #include <asm/io.h>
  34 #include <asm/prom.h>
  35 #include <asm/pci-bridge.h>
  36 #include <asm/byteorder.h>
  37 #include <asm/machdep.h>
  38 #include <asm/ppc-pci.h>
  39 #include <asm/firmware.h>
  40
  41 #ifdef DEBUG
  42 #include <asm/udbg.h>
  43 #define DBG(fmt...) printk(fmt)
  44 #else
  45 #define DBG(fmt...)
  46 #endif
  47
  48 static DEFINE_SPINLOCK(hose_spinlock);
  49
  50 /* XXX kill that some day ... */
  51 int global_phb_number;          /* Global phb counter */
  52
  53 extern struct list_head hose_list;
  54
  55 /*
  56  * pci_controller(phb) initialized common variables.
  57  */
  58 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
  59 {
  60         memset(hose, 0, sizeof(struct pci_controller));
  61
  62         spin_lock(&hose_spinlock);
  63         hose->global_number = global_phb_number++;
  64         list_add_tail(&hose->list_node, &hose_list);
  65         spin_unlock(&hose_spinlock);
  66 }
  67
  68 __init_refok struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
  69 {
  70         struct pci_controller *phb;
  71
  72         if (mem_init_done)
  73                 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
  74         else
  75                 phb = alloc_bootmem(sizeof (struct pci_controller));
  76         if (phb == NULL)
  77                 return NULL;
  78         pci_setup_pci_controller(phb);
  79         phb->arch_data = dev;
  80         phb->is_dynamic = mem_init_done;
  81 #ifdef CONFIG_PPC64
  82         if (dev) {
  83                 int nid = of_node_to_nid(dev);
  84
  85                 if (nid < 0 || !node_online(nid))
  86                         nid = -1;
  87
  88                 PHB_SET_NODE(phb, nid);
  89         }
  90 #endif
  91         return phb;
  92 }
  93
  94 void pcibios_free_controller(struct pci_controller *phb)
  95 {
  96         spin_lock(&hose_spinlock);
  97         list_del(&phb->list_node);
  98         spin_unlock(&hose_spinlock);
  99
 100         if (phb->is_dynamic)
 101                 kfree(phb);
 102 }
 103
 104 int pcibios_vaddr_is_ioport(void __iomem *address)
 105 {
 106         int ret = 0;
 107         struct pci_controller *hose;
 108         unsigned long size;
 109
 110         spin_lock(&hose_spinlock);
 111         list_for_each_entry(hose, &hose_list, list_node) {
 112 #ifdef CONFIG_PPC64
 113                 size = hose->pci_io_size;
 114 #else
 115                 size = hose->io_resource.end - hose->io_resource.start + 1;
 116 #endif
 117                 if (address >= hose->io_base_virt &&
 118                     address < (hose->io_base_virt + size)) {
 119                         ret = 1;
 120                         break;
 121                 }
 122         }
 123         spin_unlock(&hose_spinlock);
 124         return ret;
 125 }
 126
 127 /*
 128  * Return the domain number for this bus.
 129  */
 130 int pci_domain_nr(struct pci_bus *bus)
 131 {
 132         if (firmware_has_feature(FW_FEATURE_ISERIES))
 133                 return 0;
 134         else {
 135                 struct pci_controller *hose = pci_bus_to_host(bus);
 136
 137                 return hose->global_number;
 138         }
 139 }
 140
 141 EXPORT_SYMBOL(pci_domain_nr);
 142
 143 #ifdef CONFIG_PPC_OF
 144
 145 /* This routine is meant to be used early during boot, when the
 146  * PCI bus numbers have not yet been assigned, and you need to
 147  * issue PCI config cycles to an OF device.
 148  * It could also be used to "fix" RTAS config cycles if you want
 149  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
 150  * config cycles.
 151  */
 152 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
 153 {
 154         if (!have_of)
 155                 return NULL;
 156         while(node) {
 157                 struct pci_controller *hose, *tmp;
 158                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
 159                         if (hose->arch_data == node)
 160                                 return hose;
 161                 node = node->parent;
 162         }
 163         return NULL;
 164 }
 165
 166 static ssize_t pci_show_devspec(struct device *dev,
 167                 struct device_attribute *attr, char *buf)
 168 {
 169         struct pci_dev *pdev;
 170         struct device_node *np;
 171
 172         pdev = to_pci_dev (dev);
 173         np = pci_device_to_OF_node(pdev);
 174         if (np == NULL || np->full_name == NULL)
 175                 return 0;
 176         return sprintf(buf, "%s", np->full_name);
 177 }
 178 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
 179 #endif /* CONFIG_PPC_OF */
 180
 181 /* Add sysfs properties */
 182 int pcibios_add_platform_entries(struct pci_dev *pdev)
 183 {
 184 #ifdef CONFIG_PPC_OF
 185         return device_create_file(&pdev->dev, &dev_attr_devspec);
 186 #else
 187         return 0;
 188 #endif /* CONFIG_PPC_OF */
 189
 190 }
 191
 192 char __devinit *pcibios_setup(char *str)
 193 {
 194         return str;
 195 }
 196
 197 /*
 198  * Reads the interrupt pin to determine if interrupt is use by card.
 199  * If the interrupt is used, then gets the interrupt line from the
 200  * openfirmware and sets it in the pci_dev and pci_config line.
 201  */
 202 int pci_read_irq_line(struct pci_dev *pci_dev)
 203 {
 204         struct of_irq oirq;
 205         unsigned int virq;
 206
 207         DBG("Try to map irq for %s...\n", pci_name(pci_dev));
 208
 209 #ifdef DEBUG
 210         memset(&oirq, 0xff, sizeof(oirq));
 211 #endif
 212         /* Try to get a mapping from the device-tree */
 213         if (of_irq_map_pci(pci_dev, &oirq)) {
 214                 u8 line, pin;
 215
 216                 /* If that fails, lets fallback to what is in the config
 217                  * space and map that through the default controller. We
 218                  * also set the type to level low since that's what PCI
 219                  * interrupts are. If your platform does differently, then
 220                  * either provide a proper interrupt tree or don't use this
 221                  * function.
 222                  */
 223                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
 224                         return -1;
 225                 if (pin == 0)
 226                         return -1;
 227                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
 228                     line == 0xff) {
 229                         return -1;
 230                 }
 231                 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
 232
 233                 virq = irq_create_mapping(NULL, line);
 234                 if (virq != NO_IRQ)
 235                         set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
 236         } else {
 237                 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
 238                     oirq.size, oirq.specifier[0], oirq.specifier[1],
 239                     oirq.controller->full_name);
 240
 241                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
 242                                              oirq.size);
 243         }
 244         if(virq == NO_IRQ) {
 245                 DBG(" -> failed to map !\n");
 246                 return -1;
 247         }
 248
 249         DBG(" -> mapped to linux irq %d\n", virq);
 250
 251         pci_dev->irq = virq;
 252
 253         return 0;
 254 }
 255 EXPORT_SYMBOL(pci_read_irq_line);
 256
 257 /*
 258  * Platform support for /proc/bus/pci/X/Y mmap()s,
 259  * modelled on the sparc64 implementation by Dave Miller.
 260  *  -- paulus.
 261  */
 262
 263 /*
 264  * Adjust vm_pgoff of VMA such that it is the physical page offset
 265  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
 266  *
 267  * Basically, the user finds the base address for his device which he wishes
 268  * to mmap.  They read the 32-bit value from the config space base register,
 269  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 270  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 271  *
 272  * Returns negative error code on failure, zero on success.
 273  */
 274 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
 275                                                resource_size_t *offset,
 276                                                enum pci_mmap_state mmap_state)
 277 {
 278         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 279         unsigned long io_offset = 0;
 280         int i, res_bit;
 281
 282         if (hose == 0)
 283                 return NULL;            /* should never happen */
 284
 285         /* If memory, add on the PCI bridge address offset */
 286         if (mmap_state == pci_mmap_mem) {
 287 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
 288                 *offset += hose->pci_mem_offset;
 289 #endif
 290                 res_bit = IORESOURCE_MEM;
 291         } else {
 292                 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 293                 *offset += io_offset;
 294                 res_bit = IORESOURCE_IO;
 295         }
 296
 297         /*
 298          * Check that the offset requested corresponds to one of the
 299          * resources of the device.
 300          */
 301         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 302                 struct resource *rp = &dev->resource[i];
 303                 int flags = rp->flags;
 304
 305                 /* treat ROM as memory (should be already) */
 306                 if (i == PCI_ROM_RESOURCE)
 307                         flags |= IORESOURCE_MEM;
 308
 309                 /* Active and same type? */
 310                 if ((flags & res_bit) == 0)
 311                         continue;
 312
 313                 /* In the range of this resource? */
 314                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
 315                         continue;
 316
 317                 /* found it! construct the final physical address */
 318                 if (mmap_state == pci_mmap_io)
 319                         *offset += hose->io_base_phys - io_offset;
 320                 return rp;
 321         }
 322
 323         return NULL;
 324 }
 325
 326 /*
 327  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 328  * device mapping.
 329  */
 330 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
 331                                       pgprot_t protection,
 332                                       enum pci_mmap_state mmap_state,
 333                                       int write_combine)
 334 {
 335         unsigned long prot = pgprot_val(protection);
 336
 337         /* Write combine is always 0 on non-memory space mappings. On
 338          * memory space, if the user didn't pass 1, we check for a
 339          * "prefetchable" resource. This is a bit hackish, but we use
 340          * this to workaround the inability of /sysfs to provide a write
 341          * combine bit
 342          */
 343         if (mmap_state != pci_mmap_mem)
 344                 write_combine = 0;
 345         else if (write_combine == 0) {
 346                 if (rp->flags & IORESOURCE_PREFETCH)
 347                         write_combine = 1;
 348         }
 349
 350         /* XXX would be nice to have a way to ask for write-through */
 351         prot |= _PAGE_NO_CACHE;
 352         if (write_combine)
 353                 prot &= ~_PAGE_GUARDED;
 354         else
 355                 prot |= _PAGE_GUARDED;
 356
 357         return __pgprot(prot);
 358 }
 359
 360 /*
 361  * This one is used by /dev/mem and fbdev who have no clue about the
 362  * PCI device, it tries to find the PCI device first and calls the
 363  * above routine
 364  */
 365 pgprot_t pci_phys_mem_access_prot(struct file *file,
 366                                   unsigned long pfn,
 367                                   unsigned long size,
 368                                   pgprot_t protection)
 369 {
 370         struct pci_dev *pdev = NULL;
 371         struct resource *found = NULL;
 372         unsigned long prot = pgprot_val(protection);
 373         unsigned long offset = pfn << PAGE_SHIFT;
 374         int i;
 375
 376         if (page_is_ram(pfn))
 377                 return __pgprot(prot);
 378
 379         prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
 380
 381         for_each_pci_dev(pdev) {
 382                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 383                         struct resource *rp = &pdev->resource[i];
 384                         int flags = rp->flags;
 385
 386                         /* Active and same type? */
 387                         if ((flags & IORESOURCE_MEM) == 0)
 388                                 continue;
 389                         /* In the range of this resource? */
 390                         if (offset < (rp->start & PAGE_MASK) ||
 391                             offset > rp->end)
 392                                 continue;
 393                         found = rp;
 394                         break;
 395                 }
 396                 if (found)
 397                         break;
 398         }
 399         if (found) {
 400                 if (found->flags & IORESOURCE_PREFETCH)
 401                         prot &= ~_PAGE_GUARDED;
 402                 pci_dev_put(pdev);
 403         }
 404
 405         DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
 406
 407         return __pgprot(prot);
 408 }
 409
 410
 411 /*
 412  * Perform the actual remap of the pages for a PCI device mapping, as
 413  * appropriate for this architecture.  The region in the process to map
 414  * is described by vm_start and vm_end members of VMA, the base physical
 415  * address is found in vm_pgoff.
 416  * The pci device structure is provided so that architectures may make mapping
 417  * decisions on a per-device or per-bus basis.
 418  *
 419  * Returns a negative error code on failure, zero on success.
 420  */
 421 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 422                         enum pci_mmap_state mmap_state, int write_combine)
 423 {
 424         resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
 425         struct resource *rp;
 426         int ret;
 427
 428         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
 429         if (rp == NULL)
 430                 return -EINVAL;
 431
 432         vma->vm_pgoff = offset >> PAGE_SHIFT;
 433         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
 434                                                   vma->vm_page_prot,
 435                                                   mmap_state, write_combine);
 436
 437         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 438                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
 439
 440         return ret;
 441 }
 442
 443 void pci_resource_to_user(const struct pci_dev *dev, int bar,
 444                           const struct resource *rsrc,
 445                           resource_size_t *start, resource_size_t *end)
 446 {
 447         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 448         resource_size_t offset = 0;
 449
 450         if (hose == NULL)
 451                 return;
 452
 453         if (rsrc->flags & IORESOURCE_IO)
 454                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 455
 456         /* We pass a fully fixed up address to userland for MMIO instead of
 457          * a BAR value because X is lame and expects to be able to use that
 458          * to pass to /dev/mem !
 459          *
 460          * That means that we'll have potentially 64 bits values where some
 461          * userland apps only expect 32 (like X itself since it thinks only
 462          * Sparc has 64 bits MMIO) but if we don't do that, we break it on
 463          * 32 bits CHRPs :-(
 464          *
 465          * Hopefully, the sysfs insterface is immune to that gunk. Once X
 466          * has been fixed (and the fix spread enough), we can re-enable the
 467          * 2 lines below and pass down a BAR value to userland. In that case
 468          * we'll also have to re-enable the matching code in
 469          * __pci_mmap_make_offset().
 470          *
 471          * BenH.
 472          */
 473 #if 0
 474         else if (rsrc->flags & IORESOURCE_MEM)
 475                 offset = hose->pci_mem_offset;
 476 #endif
 477
 478         *start = rsrc->start - offset;
 479         *end = rsrc->end - offset;
 480 }