2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
27 #include <linux/list.h>
28 #include <linux/syscalls.h>
29 #include <linux/irq.h>
30 #include <linux/vmalloc.h>
32 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
37 #include <asm/machdep.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/firmware.h>
43 #define DBG(fmt...) printk(fmt)
48 static DEFINE_SPINLOCK(hose_spinlock
);
50 /* XXX kill that some day ... */
51 static int global_phb_number
; /* Global phb counter */
53 /* ISA Memory physical address */
54 resource_size_t isa_mem_base
;
56 /* Default PCI flags is 0 */
57 unsigned int ppc_pci_flags
;
59 static struct dma_mapping_ops
*pci_dma_ops
;
61 void set_pci_dma_ops(struct dma_mapping_ops
*dma_ops
)
63 pci_dma_ops
= dma_ops
;
66 struct dma_mapping_ops
*get_pci_dma_ops(void)
70 EXPORT_SYMBOL(get_pci_dma_ops
);
72 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
74 return dma_set_mask(&dev
->dev
, mask
);
77 int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
81 rc
= dma_set_mask(&dev
->dev
, mask
);
82 dev
->dev
.coherent_dma_mask
= dev
->dma_mask
;
87 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
89 struct pci_controller
*phb
;
91 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
94 spin_lock(&hose_spinlock
);
95 phb
->global_number
= global_phb_number
++;
96 list_add_tail(&phb
->list_node
, &hose_list
);
97 spin_unlock(&hose_spinlock
);
99 phb
->is_dynamic
= mem_init_done
;
102 int nid
= of_node_to_nid(dev
);
104 if (nid
< 0 || !node_online(nid
))
107 PHB_SET_NODE(phb
, nid
);
113 void pcibios_free_controller(struct pci_controller
*phb
)
115 spin_lock(&hose_spinlock
);
116 list_del(&phb
->list_node
);
117 spin_unlock(&hose_spinlock
);
123 int pcibios_vaddr_is_ioport(void __iomem
*address
)
126 struct pci_controller
*hose
;
129 spin_lock(&hose_spinlock
);
130 list_for_each_entry(hose
, &hose_list
, list_node
) {
132 size
= hose
->pci_io_size
;
134 size
= hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
136 if (address
>= hose
->io_base_virt
&&
137 address
< (hose
->io_base_virt
+ size
)) {
142 spin_unlock(&hose_spinlock
);
147 * Return the domain number for this bus.
149 int pci_domain_nr(struct pci_bus
*bus
)
151 struct pci_controller
*hose
= pci_bus_to_host(bus
);
153 return hose
->global_number
;
155 EXPORT_SYMBOL(pci_domain_nr
);
159 /* This routine is meant to be used early during boot, when the
160 * PCI bus numbers have not yet been assigned, and you need to
161 * issue PCI config cycles to an OF device.
162 * It could also be used to "fix" RTAS config cycles if you want
163 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
166 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
171 struct pci_controller
*hose
, *tmp
;
172 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
173 if (hose
->dn
== node
)
180 static ssize_t
pci_show_devspec(struct device
*dev
,
181 struct device_attribute
*attr
, char *buf
)
183 struct pci_dev
*pdev
;
184 struct device_node
*np
;
186 pdev
= to_pci_dev (dev
);
187 np
= pci_device_to_OF_node(pdev
);
188 if (np
== NULL
|| np
->full_name
== NULL
)
190 return sprintf(buf
, "%s", np
->full_name
);
192 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
193 #endif /* CONFIG_PPC_OF */
195 /* Add sysfs properties */
196 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
199 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
202 #endif /* CONFIG_PPC_OF */
206 char __devinit
*pcibios_setup(char *str
)
211 void __devinit
pcibios_setup_new_device(struct pci_dev
*dev
)
213 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
215 sd
->of_node
= pci_device_to_OF_node(dev
);
217 DBG("PCI: device %s OF node: %s\n", pci_name(dev
),
218 sd
->of_node
? sd
->of_node
->full_name
: "<none>");
220 sd
->dma_ops
= pci_dma_ops
;
222 sd
->dma_data
= (void *)PCI_DRAM_OFFSET
;
224 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
226 if (ppc_md
.pci_dma_dev_setup
)
227 ppc_md
.pci_dma_dev_setup(dev
);
229 EXPORT_SYMBOL(pcibios_setup_new_device
);
232 * Reads the interrupt pin to determine if interrupt is use by card.
233 * If the interrupt is used, then gets the interrupt line from the
234 * openfirmware and sets it in the pci_dev and pci_config line.
236 int pci_read_irq_line(struct pci_dev
*pci_dev
)
241 /* The current device-tree that iSeries generates from the HV
242 * PCI informations doesn't contain proper interrupt routing,
243 * and all the fallback would do is print out crap, so we
244 * don't attempt to resolve the interrupts here at all, some
245 * iSeries specific fixup does it.
247 * In the long run, we will hopefully fix the generated device-tree
250 #ifdef CONFIG_PPC_ISERIES
251 if (firmware_has_feature(FW_FEATURE_ISERIES
))
255 DBG("Try to map irq for %s...\n", pci_name(pci_dev
));
258 memset(&oirq
, 0xff, sizeof(oirq
));
260 /* Try to get a mapping from the device-tree */
261 if (of_irq_map_pci(pci_dev
, &oirq
)) {
264 /* If that fails, lets fallback to what is in the config
265 * space and map that through the default controller. We
266 * also set the type to level low since that's what PCI
267 * interrupts are. If your platform does differently, then
268 * either provide a proper interrupt tree or don't use this
271 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
275 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
276 line
== 0xff || line
== 0) {
279 DBG(" -> no map ! Using line %d (pin %d) from PCI config\n",
282 virq
= irq_create_mapping(NULL
, line
);
284 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
286 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
287 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
288 oirq
.controller
->full_name
);
290 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
294 DBG(" -> failed to map !\n");
298 DBG(" -> mapped to linux irq %d\n", virq
);
304 EXPORT_SYMBOL(pci_read_irq_line
);
307 * Platform support for /proc/bus/pci/X/Y mmap()s,
308 * modelled on the sparc64 implementation by Dave Miller.
313 * Adjust vm_pgoff of VMA such that it is the physical page offset
314 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
316 * Basically, the user finds the base address for his device which he wishes
317 * to mmap. They read the 32-bit value from the config space base register,
318 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
319 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
321 * Returns negative error code on failure, zero on success.
323 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
324 resource_size_t
*offset
,
325 enum pci_mmap_state mmap_state
)
327 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
328 unsigned long io_offset
= 0;
332 return NULL
; /* should never happen */
334 /* If memory, add on the PCI bridge address offset */
335 if (mmap_state
== pci_mmap_mem
) {
336 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
337 *offset
+= hose
->pci_mem_offset
;
339 res_bit
= IORESOURCE_MEM
;
341 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
342 *offset
+= io_offset
;
343 res_bit
= IORESOURCE_IO
;
347 * Check that the offset requested corresponds to one of the
348 * resources of the device.
350 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
351 struct resource
*rp
= &dev
->resource
[i
];
352 int flags
= rp
->flags
;
354 /* treat ROM as memory (should be already) */
355 if (i
== PCI_ROM_RESOURCE
)
356 flags
|= IORESOURCE_MEM
;
358 /* Active and same type? */
359 if ((flags
& res_bit
) == 0)
362 /* In the range of this resource? */
363 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
366 /* found it! construct the final physical address */
367 if (mmap_state
== pci_mmap_io
)
368 *offset
+= hose
->io_base_phys
- io_offset
;
376 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
379 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
381 enum pci_mmap_state mmap_state
,
384 unsigned long prot
= pgprot_val(protection
);
386 /* Write combine is always 0 on non-memory space mappings. On
387 * memory space, if the user didn't pass 1, we check for a
388 * "prefetchable" resource. This is a bit hackish, but we use
389 * this to workaround the inability of /sysfs to provide a write
392 if (mmap_state
!= pci_mmap_mem
)
394 else if (write_combine
== 0) {
395 if (rp
->flags
& IORESOURCE_PREFETCH
)
399 /* XXX would be nice to have a way to ask for write-through */
400 prot
|= _PAGE_NO_CACHE
;
402 prot
&= ~_PAGE_GUARDED
;
404 prot
|= _PAGE_GUARDED
;
406 return __pgprot(prot
);
410 * This one is used by /dev/mem and fbdev who have no clue about the
411 * PCI device, it tries to find the PCI device first and calls the
414 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
419 struct pci_dev
*pdev
= NULL
;
420 struct resource
*found
= NULL
;
421 unsigned long prot
= pgprot_val(protection
);
422 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
425 if (page_is_ram(pfn
))
426 return __pgprot(prot
);
428 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
430 for_each_pci_dev(pdev
) {
431 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
432 struct resource
*rp
= &pdev
->resource
[i
];
433 int flags
= rp
->flags
;
435 /* Active and same type? */
436 if ((flags
& IORESOURCE_MEM
) == 0)
438 /* In the range of this resource? */
439 if (offset
< (rp
->start
& PAGE_MASK
) ||
449 if (found
->flags
& IORESOURCE_PREFETCH
)
450 prot
&= ~_PAGE_GUARDED
;
454 DBG("non-PCI map for %llx, prot: %lx\n",
455 (unsigned long long)offset
, prot
);
457 return __pgprot(prot
);
462 * Perform the actual remap of the pages for a PCI device mapping, as
463 * appropriate for this architecture. The region in the process to map
464 * is described by vm_start and vm_end members of VMA, the base physical
465 * address is found in vm_pgoff.
466 * The pci device structure is provided so that architectures may make mapping
467 * decisions on a per-device or per-bus basis.
469 * Returns a negative error code on failure, zero on success.
471 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
472 enum pci_mmap_state mmap_state
, int write_combine
)
474 resource_size_t offset
=
475 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
479 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
483 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
484 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
486 mmap_state
, write_combine
);
488 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
489 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
494 /* This provides legacy IO read access on a bus */
495 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
497 unsigned long offset
;
498 struct pci_controller
*hose
= pci_bus_to_host(bus
);
499 struct resource
*rp
= &hose
->io_resource
;
502 /* Check if port can be supported by that bus. We only check
503 * the ranges of the PHB though, not the bus itself as the rules
504 * for forwarding legacy cycles down bridges are not our problem
505 * here. So if the host bridge supports it, we do it.
507 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
510 if (!(rp
->flags
& IORESOURCE_IO
))
512 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
514 addr
= hose
->io_base_virt
+ port
;
518 *((u8
*)val
) = in_8(addr
);
523 *((u16
*)val
) = in_le16(addr
);
528 *((u32
*)val
) = in_le32(addr
);
534 /* This provides legacy IO write access on a bus */
535 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
537 unsigned long offset
;
538 struct pci_controller
*hose
= pci_bus_to_host(bus
);
539 struct resource
*rp
= &hose
->io_resource
;
542 /* Check if port can be supported by that bus. We only check
543 * the ranges of the PHB though, not the bus itself as the rules
544 * for forwarding legacy cycles down bridges are not our problem
545 * here. So if the host bridge supports it, we do it.
547 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
550 if (!(rp
->flags
& IORESOURCE_IO
))
552 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
554 addr
= hose
->io_base_virt
+ port
;
556 /* WARNING: The generic code is idiotic. It gets passed a pointer
557 * to what can be a 1, 2 or 4 byte quantity and always reads that
558 * as a u32, which means that we have to correct the location of
559 * the data read within those 32 bits for size 1 and 2
563 out_8(addr
, val
>> 24);
568 out_le16(addr
, val
>> 16);
579 /* This provides legacy IO or memory mmap access on a bus */
580 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
581 struct vm_area_struct
*vma
,
582 enum pci_mmap_state mmap_state
)
584 struct pci_controller
*hose
= pci_bus_to_host(bus
);
585 resource_size_t offset
=
586 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
587 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
590 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
591 pci_domain_nr(bus
), bus
->number
,
592 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
593 (unsigned long long)offset
,
594 (unsigned long long)(offset
+ size
- 1));
596 if (mmap_state
== pci_mmap_mem
) {
597 if ((offset
+ size
) > hose
->isa_mem_size
)
599 offset
+= hose
->isa_mem_phys
;
601 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
602 unsigned long roffset
= offset
+ io_offset
;
603 rp
= &hose
->io_resource
;
604 if (!(rp
->flags
& IORESOURCE_IO
))
606 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
608 offset
+= hose
->io_base_phys
;
610 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
612 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
613 vma
->vm_page_prot
= __pgprot(pgprot_val(vma
->vm_page_prot
)
614 | _PAGE_NO_CACHE
| _PAGE_GUARDED
);
615 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
616 vma
->vm_end
- vma
->vm_start
,
620 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
621 const struct resource
*rsrc
,
622 resource_size_t
*start
, resource_size_t
*end
)
624 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
625 resource_size_t offset
= 0;
630 if (rsrc
->flags
& IORESOURCE_IO
)
631 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
633 /* We pass a fully fixed up address to userland for MMIO instead of
634 * a BAR value because X is lame and expects to be able to use that
635 * to pass to /dev/mem !
637 * That means that we'll have potentially 64 bits values where some
638 * userland apps only expect 32 (like X itself since it thinks only
639 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
642 * Hopefully, the sysfs insterface is immune to that gunk. Once X
643 * has been fixed (and the fix spread enough), we can re-enable the
644 * 2 lines below and pass down a BAR value to userland. In that case
645 * we'll also have to re-enable the matching code in
646 * __pci_mmap_make_offset().
651 else if (rsrc
->flags
& IORESOURCE_MEM
)
652 offset
= hose
->pci_mem_offset
;
655 *start
= rsrc
->start
- offset
;
656 *end
= rsrc
->end
- offset
;
660 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
661 * @hose: newly allocated pci_controller to be setup
662 * @dev: device node of the host bridge
663 * @primary: set if primary bus (32 bits only, soon to be deprecated)
665 * This function will parse the "ranges" property of a PCI host bridge device
666 * node and setup the resource mapping of a pci controller based on its
669 * Life would be boring if it wasn't for a few issues that we have to deal
672 * - We can only cope with one IO space range and up to 3 Memory space
673 * ranges. However, some machines (thanks Apple !) tend to split their
674 * space into lots of small contiguous ranges. So we have to coalesce.
676 * - We can only cope with all memory ranges having the same offset
677 * between CPU addresses and PCI addresses. Unfortunately, some bridges
678 * are setup for a large 1:1 mapping along with a small "window" which
679 * maps PCI address 0 to some arbitrary high address of the CPU space in
680 * order to give access to the ISA memory hole.
681 * The way out of here that I've chosen for now is to always set the
682 * offset based on the first resource found, then override it if we
683 * have a different offset and the previous was set by an ISA hole.
685 * - Some busses have IO space not starting at 0, which causes trouble with
686 * the way we do our IO resource renumbering. The code somewhat deals with
687 * it for 64 bits but I would expect problems on 32 bits.
689 * - Some 32 bits platforms such as 4xx can have physical space larger than
690 * 32 bits so we need to use 64 bits values for the parsing
692 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
693 struct device_node
*dev
,
698 int pna
= of_n_addr_cells(dev
);
700 int memno
= 0, isa_hole
= -1;
702 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
703 unsigned long long isa_mb
= 0;
704 struct resource
*res
;
706 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
707 dev
->full_name
, primary
? "(primary)" : "");
709 /* Get ranges property */
710 ranges
= of_get_property(dev
, "ranges", &rlen
);
715 while ((rlen
-= np
* 4) >= 0) {
716 /* Read next ranges element */
717 pci_space
= ranges
[0];
718 pci_addr
= of_read_number(ranges
+ 1, 2);
719 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
720 size
= of_read_number(ranges
+ pna
+ 3, 2);
723 /* If we failed translation or got a zero-sized region
724 * (some FW try to feed us with non sensical zero sized regions
725 * such as power3 which look like some kind of attempt at exposing
726 * the VGA memory hole)
728 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
731 /* Now consume following elements while they are contiguous */
732 for (; rlen
>= np
* sizeof(u32
);
733 ranges
+= np
, rlen
-= np
* 4) {
734 if (ranges
[0] != pci_space
)
736 pci_next
= of_read_number(ranges
+ 1, 2);
737 cpu_next
= of_translate_address(dev
, ranges
+ 3);
738 if (pci_next
!= pci_addr
+ size
||
739 cpu_next
!= cpu_addr
+ size
)
741 size
+= of_read_number(ranges
+ pna
+ 3, 2);
744 /* Act based on address space type */
746 switch ((pci_space
>> 24) & 0x3) {
747 case 1: /* PCI IO space */
749 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
750 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
752 /* We support only one IO range */
753 if (hose
->pci_io_size
) {
755 " \\--> Skipped (too many) !\n");
759 /* On 32 bits, limit I/O space to 16MB */
760 if (size
> 0x01000000)
763 /* 32 bits needs to map IOs here */
764 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
766 /* Expect trouble if pci_addr is not 0 */
769 (unsigned long)hose
->io_base_virt
;
770 #endif /* CONFIG_PPC32 */
771 /* pci_io_size and io_base_phys always represent IO
772 * space starting at 0 so we factor in pci_addr
774 hose
->pci_io_size
= pci_addr
+ size
;
775 hose
->io_base_phys
= cpu_addr
- pci_addr
;
778 res
= &hose
->io_resource
;
779 res
->flags
= IORESOURCE_IO
;
780 res
->start
= pci_addr
;
782 case 2: /* PCI Memory space */
783 case 3: /* PCI 64 bits Memory space */
785 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
786 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
787 (pci_space
& 0x40000000) ? "Prefetch" : "");
789 /* We support only 3 memory ranges */
792 " \\--> Skipped (too many) !\n");
795 /* Handles ISA memory hole space here */
799 if (primary
|| isa_mem_base
== 0)
800 isa_mem_base
= cpu_addr
;
801 hose
->isa_mem_phys
= cpu_addr
;
802 hose
->isa_mem_size
= size
;
805 /* We get the PCI/Mem offset from the first range or
806 * the, current one if the offset came from an ISA
807 * hole. If they don't match, bugger.
810 (isa_hole
>= 0 && pci_addr
!= 0 &&
811 hose
->pci_mem_offset
== isa_mb
))
812 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
813 else if (pci_addr
!= 0 &&
814 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
816 " \\--> Skipped (offset mismatch) !\n");
821 res
= &hose
->mem_resources
[memno
++];
822 res
->flags
= IORESOURCE_MEM
;
823 if (pci_space
& 0x40000000)
824 res
->flags
|= IORESOURCE_PREFETCH
;
825 res
->start
= cpu_addr
;
829 res
->name
= dev
->full_name
;
830 res
->end
= res
->start
+ size
- 1;
837 /* If there's an ISA hole and the pci_mem_offset is -not- matching
838 * the ISA hole offset, then we need to remove the ISA hole from
839 * the resource list for that brige
841 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
842 unsigned int next
= isa_hole
+ 1;
843 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
845 memmove(&hose
->mem_resources
[isa_hole
],
846 &hose
->mem_resources
[next
],
847 sizeof(struct resource
) * (memno
- next
));
848 hose
->mem_resources
[--memno
].flags
= 0;
852 /* Decide whether to display the domain number in /proc */
853 int pci_proc_domain(struct pci_bus
*bus
)
855 struct pci_controller
*hose
= pci_bus_to_host(bus
);
857 return hose
->buid
!= 0;
859 if (!(ppc_pci_flags
& PPC_PCI_ENABLE_PROC_DOMAINS
))
861 if (ppc_pci_flags
& PPC_PCI_COMPAT_DOMAIN_0
)
862 return hose
->global_number
!= 0;
867 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
868 struct resource
*res
)
870 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
871 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
875 if (res
->flags
& IORESOURCE_IO
) {
876 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
878 } else if (res
->flags
& IORESOURCE_MEM
)
879 offset
= hose
->pci_mem_offset
;
881 region
->start
= (res
->start
- offset
) & mask
;
882 region
->end
= (res
->end
- offset
) & mask
;
884 EXPORT_SYMBOL(pcibios_resource_to_bus
);
886 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
887 struct pci_bus_region
*region
)
889 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
890 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
894 if (res
->flags
& IORESOURCE_IO
) {
895 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
897 } else if (res
->flags
& IORESOURCE_MEM
)
898 offset
= hose
->pci_mem_offset
;
899 res
->start
= (region
->start
+ offset
) & mask
;
900 res
->end
= (region
->end
+ offset
) & mask
;
902 EXPORT_SYMBOL(pcibios_bus_to_resource
);
904 /* Fixup a bus resource into a linux resource */
905 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
907 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
908 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
910 if (res
->flags
& IORESOURCE_IO
) {
911 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
913 } else if (res
->flags
& IORESOURCE_MEM
)
914 offset
= hose
->pci_mem_offset
;
916 res
->start
= (res
->start
+ offset
) & mask
;
917 res
->end
= (res
->end
+ offset
) & mask
;
921 /* This header fixup will do the resource fixup for all devices as they are
922 * probed, but not for bridge ranges
924 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
926 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
930 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
934 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
935 struct resource
*res
= dev
->resource
+ i
;
938 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
939 * consider 0 as an unassigned BAR value. It's technically
940 * a valid value, but linux doesn't like it... so when we can
941 * re-assign things, we do so, but if we can't, we keep it
942 * around and hope for the best...
944 if (res
->start
== 0 && !(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
945 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
947 (unsigned long long)res
->start
,
948 (unsigned long long)res
->end
,
949 (unsigned int)res
->flags
);
950 res
->end
-= res
->start
;
952 res
->flags
|= IORESOURCE_UNSET
;
956 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
958 (unsigned long long)res
->start
,\
959 (unsigned long long)res
->end
,
960 (unsigned int)res
->flags
);
962 fixup_resource(res
, dev
);
964 pr_debug("PCI:%s %016llx-%016llx\n",
966 (unsigned long long)res
->start
,
967 (unsigned long long)res
->end
);
970 /* Call machine specific resource fixup */
971 if (ppc_md
.pcibios_fixup_resources
)
972 ppc_md
.pcibios_fixup_resources(dev
);
974 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
976 /* This function tries to figure out if a bridge resource has been initialized
977 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
978 * things go more smoothly when it gets it right. It should covers cases such
979 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
981 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
982 struct resource
*res
)
984 struct pci_controller
*hose
= pci_bus_to_host(bus
);
985 struct pci_dev
*dev
= bus
->self
;
986 resource_size_t offset
;
990 /* We don't do anything if PCI_PROBE_ONLY is set */
991 if (ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)
994 /* Job is a bit different between memory and IO */
995 if (res
->flags
& IORESOURCE_MEM
) {
996 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
997 * initialized by somebody
999 if (res
->start
!= hose
->pci_mem_offset
)
1002 /* The BAR is 0, let's check if memory decoding is enabled on
1003 * the bridge. If not, we consider it unassigned
1005 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1006 if ((command
& PCI_COMMAND_MEMORY
) == 0)
1009 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
1010 * resources covers that starting address (0 then it's good enough for
1013 for (i
= 0; i
< 3; i
++) {
1014 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
1015 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
1019 /* Well, it starts at 0 and we know it will collide so we may as
1020 * well consider it as unassigned. That covers the Apple case.
1024 /* If the BAR is non-0, then we consider it assigned */
1025 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1026 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
1029 /* Here, we are a bit different than memory as typically IO space
1030 * starting at low addresses -is- valid. What we do instead if that
1031 * we consider as unassigned anything that doesn't have IO enabled
1032 * in the PCI command register, and that's it.
1034 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1035 if (command
& PCI_COMMAND_IO
)
1038 /* It's starting at 0 and IO is disabled in the bridge, consider
1045 /* Fixup resources of a PCI<->PCI bridge */
1046 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1048 struct resource
*res
;
1051 struct pci_dev
*dev
= bus
->self
;
1053 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1054 if ((res
= bus
->resource
[i
]) == NULL
)
1058 if (i
>= 3 && bus
->self
->transparent
)
1061 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1063 (unsigned long long)res
->start
,\
1064 (unsigned long long)res
->end
,
1065 (unsigned int)res
->flags
);
1068 fixup_resource(res
, dev
);
1070 /* Try to detect uninitialized P2P bridge resources,
1071 * and clear them out so they get re-assigned later
1073 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1075 pr_debug("PCI:%s (unassigned)\n", pci_name(dev
));
1078 pr_debug("PCI:%s %016llx-%016llx\n",
1080 (unsigned long long)res
->start
,
1081 (unsigned long long)res
->end
);
1086 static void __devinit
__pcibios_fixup_bus(struct pci_bus
*bus
)
1088 struct pci_dev
*dev
= bus
->self
;
1090 pr_debug("PCI: Fixup bus %d (%s)\n", bus
->number
, dev
? pci_name(dev
) : "PHB");
1092 /* Fixup PCI<->PCI bridges. Host bridges are handled separately, for
1093 * now differently between 32 and 64 bits.
1096 pcibios_fixup_bridge(bus
);
1098 /* Additional setup that is different between 32 and 64 bits for now */
1099 pcibios_do_bus_setup(bus
);
1101 /* Platform specific bus fixups */
1102 if (ppc_md
.pcibios_fixup_bus
)
1103 ppc_md
.pcibios_fixup_bus(bus
);
1105 /* Read default IRQs and fixup if necessary */
1106 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1107 pci_read_irq_line(dev
);
1108 if (ppc_md
.pci_irq_fixup
)
1109 ppc_md
.pci_irq_fixup(dev
);
1113 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1115 /* When called from the generic PCI probe, read PCI<->PCI bridge
1116 * bases before proceeding
1118 if (bus
->self
!= NULL
)
1119 pci_read_bridge_bases(bus
);
1120 __pcibios_fixup_bus(bus
);
1122 EXPORT_SYMBOL(pcibios_fixup_bus
);
1124 /* When building a bus from the OF tree rather than probing, we need a
1125 * slightly different version of the fixup which doesn't read the
1126 * bridge bases using config space accesses
1128 void __devinit
pcibios_fixup_of_probed_bus(struct pci_bus
*bus
)
1130 __pcibios_fixup_bus(bus
);
1133 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1135 if ((ppc_pci_flags
& PPC_PCI_CAN_SKIP_ISA_ALIGN
) &&
1136 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1142 * We need to avoid collisions with `mirrored' VGA ports
1143 * and other strange ISA hardware, so we always want the
1144 * addresses to be allocated in the 0x000-0x0ff region
1147 * Why? Because some silly external IO cards only decode
1148 * the low 10 bits of the IO address. The 0x00-0xff region
1149 * is reserved for motherboard devices that decode all 16
1150 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1151 * but we want to try to avoid allocating at 0x2900-0x2bff
1152 * which might have be mirrored at 0x0100-0x03ff..
1154 void pcibios_align_resource(void *data
, struct resource
*res
,
1155 resource_size_t size
, resource_size_t align
)
1157 struct pci_dev
*dev
= data
;
1159 if (res
->flags
& IORESOURCE_IO
) {
1160 resource_size_t start
= res
->start
;
1162 if (skip_isa_ioresource_align(dev
))
1164 if (start
& 0x300) {
1165 start
= (start
+ 0x3ff) & ~0x3ff;
1170 EXPORT_SYMBOL(pcibios_align_resource
);
1173 * Reparent resource children of pr that conflict with res
1174 * under res, and make res replace those children.
1176 static int __init
reparent_resources(struct resource
*parent
,
1177 struct resource
*res
)
1179 struct resource
*p
, **pp
;
1180 struct resource
**firstpp
= NULL
;
1182 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1183 if (p
->end
< res
->start
)
1185 if (res
->end
< p
->start
)
1187 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1188 return -1; /* not completely contained */
1189 if (firstpp
== NULL
)
1192 if (firstpp
== NULL
)
1193 return -1; /* didn't find any conflicting entries? */
1194 res
->parent
= parent
;
1195 res
->child
= *firstpp
;
1199 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1201 DBG(KERN_INFO
"PCI: reparented %s [%llx..%llx] under %s\n",
1203 (unsigned long long)p
->start
,
1204 (unsigned long long)p
->end
, res
->name
);
1210 * Handle resources of PCI devices. If the world were perfect, we could
1211 * just allocate all the resource regions and do nothing more. It isn't.
1212 * On the other hand, we cannot just re-allocate all devices, as it would
1213 * require us to know lots of host bridge internals. So we attempt to
1214 * keep as much of the original configuration as possible, but tweak it
1215 * when it's found to be wrong.
1217 * Known BIOS problems we have to work around:
1218 * - I/O or memory regions not configured
1219 * - regions configured, but not enabled in the command register
1220 * - bogus I/O addresses above 64K used
1221 * - expansion ROMs left enabled (this may sound harmless, but given
1222 * the fact the PCI specs explicitly allow address decoders to be
1223 * shared between expansion ROMs and other resource regions, it's
1224 * at least dangerous)
1227 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1228 * This gives us fixed barriers on where we can allocate.
1229 * (2) Allocate resources for all enabled devices. If there is
1230 * a collision, just mark the resource as unallocated. Also
1231 * disable expansion ROMs during this step.
1232 * (3) Try to allocate resources for disabled devices. If the
1233 * resources were assigned correctly, everything goes well,
1234 * if they weren't, they won't disturb allocation of other
1236 * (4) Assign new addresses to resources which were either
1237 * not configured at all or misconfigured. If explicitly
1238 * requested by the user, configure expansion ROM address
1242 static void __init
pcibios_allocate_bus_resources(struct list_head
*bus_list
)
1244 struct pci_bus
*bus
;
1246 struct resource
*res
, *pr
;
1248 /* Depth-First Search on bus tree */
1249 list_for_each_entry(bus
, bus_list
, node
) {
1250 for (i
= 0; i
< PCI_BUS_NUM_RESOURCES
; ++i
) {
1251 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
1252 || res
->start
> res
->end
)
1254 if (bus
->parent
== NULL
)
1255 pr
= (res
->flags
& IORESOURCE_IO
) ?
1256 &ioport_resource
: &iomem_resource
;
1258 /* Don't bother with non-root busses when
1259 * re-assigning all resources. We clear the
1260 * resource flags as if they were colliding
1261 * and as such ensure proper re-allocation
1264 if (ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)
1265 goto clear_resource
;
1266 pr
= pci_find_parent_resource(bus
->self
, res
);
1268 /* this happens when the generic PCI
1269 * code (wrongly) decides that this
1270 * bridge is transparent -- paulus
1276 DBG("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1277 "[0x%x], parent %p (%s)\n",
1278 bus
->self
? pci_name(bus
->self
) : "PHB",
1280 (unsigned long long)res
->start
,
1281 (unsigned long long)res
->end
,
1282 (unsigned int)res
->flags
,
1283 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1285 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1286 if (request_resource(pr
, res
) == 0)
1289 * Must be a conflict with an existing entry.
1290 * Move that entry (or entries) under the
1291 * bridge resource and try again.
1293 if (reparent_resources(pr
, res
) == 0)
1297 "PCI: Cannot allocate resource region "
1298 "%d of PCI bridge %d, will remap\n",
1303 pcibios_allocate_bus_resources(&bus
->children
);
1307 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1309 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1311 DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1313 (unsigned long long)r
->start
,
1314 (unsigned long long)r
->end
,
1315 (unsigned int)r
->flags
);
1317 pr
= pci_find_parent_resource(dev
, r
);
1318 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1319 request_resource(pr
, r
) < 0) {
1320 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1321 " of device %s, will remap\n", idx
, pci_name(dev
));
1323 DBG("PCI: parent is %p: %016llx-%016llx [%x]\n", pr
,
1324 (unsigned long long)pr
->start
,
1325 (unsigned long long)pr
->end
,
1326 (unsigned int)pr
->flags
);
1327 /* We'll assign a new address later */
1328 r
->flags
|= IORESOURCE_UNSET
;
1334 static void __init
pcibios_allocate_resources(int pass
)
1336 struct pci_dev
*dev
= NULL
;
1341 for_each_pci_dev(dev
) {
1342 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1343 for (idx
= 0; idx
< 6; idx
++) {
1344 r
= &dev
->resource
[idx
];
1345 if (r
->parent
) /* Already allocated */
1347 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1348 continue; /* Not assigned at all */
1349 if (r
->flags
& IORESOURCE_IO
)
1350 disabled
= !(command
& PCI_COMMAND_IO
);
1352 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1353 if (pass
== disabled
)
1354 alloc_resource(dev
, idx
);
1358 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1359 if (r
->flags
& IORESOURCE_ROM_ENABLE
) {
1360 /* Turn the ROM off, leave the resource region,
1361 * but keep it unregistered.
1364 DBG("PCI: Switching off ROM of %s\n", pci_name(dev
));
1365 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1366 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1367 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1368 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1373 void __init
pcibios_resource_survey(void)
1375 /* Allocate and assign resources. If we re-assign everything, then
1376 * we skip the allocate phase
1378 pcibios_allocate_bus_resources(&pci_root_buses
);
1380 if (!(ppc_pci_flags
& PPC_PCI_REASSIGN_ALL_RSRC
)) {
1381 pcibios_allocate_resources(0);
1382 pcibios_allocate_resources(1);
1385 if (!(ppc_pci_flags
& PPC_PCI_PROBE_ONLY
)) {
1386 DBG("PCI: Assigning unassigned resouces...\n");
1387 pci_assign_unassigned_resources();
1390 /* Call machine dependent fixup */
1391 if (ppc_md
.pcibios_fixup
)
1392 ppc_md
.pcibios_fixup();
1395 #ifdef CONFIG_HOTPLUG
1396 /* This is used by the pSeries hotplug driver to allocate resource
1397 * of newly plugged busses. We can try to consolidate with the
1398 * rest of the code later, for now, keep it as-is
1400 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1402 struct pci_dev
*dev
;
1403 struct pci_bus
*child_bus
;
1405 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1408 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1409 struct resource
*r
= &dev
->resource
[i
];
1411 if (r
->parent
|| !r
->start
|| !r
->flags
)
1413 pci_claim_resource(dev
, i
);
1417 list_for_each_entry(child_bus
, &bus
->children
, node
)
1418 pcibios_claim_one_bus(child_bus
);
1420 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1421 #endif /* CONFIG_HOTPLUG */
1423 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1425 if (ppc_md
.pcibios_enable_device_hook
)
1426 if (ppc_md
.pcibios_enable_device_hook(dev
))
1429 return pci_enable_resources(dev
, mask
);