arch/powerpc/kernel/pci-common.c

   1 /*
   2  * Contains common pci routines for ALL ppc platform
   3  * (based on pci_32.c and pci_64.c)
   4  *
   5  * Port for PPC64 David Engebretsen, IBM Corp.
   6  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   7  *
   8  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *   Rework, based on alpha PCI code.
  10  *
  11  * Common pmac/prep/chrp pci routines. -- Cort
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version
  16  * 2 of the License, or (at your option) any later version.
  17  */
  18
  19 #undef DEBUG
  20
  21 #include <linux/kernel.h>
  22 #include <linux/pci.h>
  23 #include <linux/string.h>
  24 #include <linux/init.h>
  25 #include <linux/bootmem.h>
  26 #include <linux/mm.h>
  27 #include <linux/list.h>
  28 #include <linux/syscalls.h>
  29 #include <linux/irq.h>
  30 #include <linux/vmalloc.h>
  31
  32 #include <asm/processor.h>
  33 #include <asm/io.h>
  34 #include <asm/prom.h>
  35 #include <asm/pci-bridge.h>
  36 #include <asm/byteorder.h>
  37 #include <asm/machdep.h>
  38 #include <asm/ppc-pci.h>
  39 #include <asm/firmware.h>
  40
  41 #ifdef DEBUG
  42 #include <asm/udbg.h>
  43 #define DBG(fmt...) printk(fmt)
  44 #else
  45 #define DBG(fmt...)
  46 #endif
  47
  48 static DEFINE_SPINLOCK(hose_spinlock);
  49
  50 /* XXX kill that some day ... */
  51 static int global_phb_number;           /* Global phb counter */
  52
  53 /*
  54  * pci_controller(phb) initialized common variables.
  55  */
  56 static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
  57 {
  58         memset(hose, 0, sizeof(struct pci_controller));
  59
  60         spin_lock(&hose_spinlock);
  61         hose->global_number = global_phb_number++;
  62         list_add_tail(&hose->list_node, &hose_list);
  63         spin_unlock(&hose_spinlock);
  64 }
  65
  66 struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
  67 {
  68         struct pci_controller *phb;
  69
  70         phb = alloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
  71         if (phb == NULL)
  72                 return NULL;
  73         pci_setup_pci_controller(phb);
  74         phb->arch_data = dev;
  75         phb->is_dynamic = mem_init_done;
  76 #ifdef CONFIG_PPC64
  77         if (dev) {
  78                 int nid = of_node_to_nid(dev);
  79
  80                 if (nid < 0 || !node_online(nid))
  81                         nid = -1;
  82
  83                 PHB_SET_NODE(phb, nid);
  84         }
  85 #endif
  86         return phb;
  87 }
  88
  89 void pcibios_free_controller(struct pci_controller *phb)
  90 {
  91         spin_lock(&hose_spinlock);
  92         list_del(&phb->list_node);
  93         spin_unlock(&hose_spinlock);
  94
  95         if (phb->is_dynamic)
  96                 kfree(phb);
  97 }
  98
  99 int pcibios_vaddr_is_ioport(void __iomem *address)
 100 {
 101         int ret = 0;
 102         struct pci_controller *hose;
 103         unsigned long size;
 104
 105         spin_lock(&hose_spinlock);
 106         list_for_each_entry(hose, &hose_list, list_node) {
 107 #ifdef CONFIG_PPC64
 108                 size = hose->pci_io_size;
 109 #else
 110                 size = hose->io_resource.end - hose->io_resource.start + 1;
 111 #endif
 112                 if (address >= hose->io_base_virt &&
 113                     address < (hose->io_base_virt + size)) {
 114                         ret = 1;
 115                         break;
 116                 }
 117         }
 118         spin_unlock(&hose_spinlock);
 119         return ret;
 120 }
 121
 122 /*
 123  * Return the domain number for this bus.
 124  */
 125 int pci_domain_nr(struct pci_bus *bus)
 126 {
 127         if (firmware_has_feature(FW_FEATURE_ISERIES))
 128                 return 0;
 129         else {
 130                 struct pci_controller *hose = pci_bus_to_host(bus);
 131
 132                 return hose->global_number;
 133         }
 134 }
 135
 136 EXPORT_SYMBOL(pci_domain_nr);
 137
 138 #ifdef CONFIG_PPC_OF
 139
 140 /* This routine is meant to be used early during boot, when the
 141  * PCI bus numbers have not yet been assigned, and you need to
 142  * issue PCI config cycles to an OF device.
 143  * It could also be used to "fix" RTAS config cycles if you want
 144  * to set pci_assign_all_buses to 1 and still use RTAS for PCI
 145  * config cycles.
 146  */
 147 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
 148 {
 149         if (!have_of)
 150                 return NULL;
 151         while(node) {
 152                 struct pci_controller *hose, *tmp;
 153                 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
 154                         if (hose->arch_data == node)
 155                                 return hose;
 156                 node = node->parent;
 157         }
 158         return NULL;
 159 }
 160
 161 static ssize_t pci_show_devspec(struct device *dev,
 162                 struct device_attribute *attr, char *buf)
 163 {
 164         struct pci_dev *pdev;
 165         struct device_node *np;
 166
 167         pdev = to_pci_dev (dev);
 168         np = pci_device_to_OF_node(pdev);
 169         if (np == NULL || np->full_name == NULL)
 170                 return 0;
 171         return sprintf(buf, "%s", np->full_name);
 172 }
 173 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
 174 #endif /* CONFIG_PPC_OF */
 175
 176 /* Add sysfs properties */
 177 int pcibios_add_platform_entries(struct pci_dev *pdev)
 178 {
 179 #ifdef CONFIG_PPC_OF
 180         return device_create_file(&pdev->dev, &dev_attr_devspec);
 181 #else
 182         return 0;
 183 #endif /* CONFIG_PPC_OF */
 184
 185 }
 186
 187 char __devinit *pcibios_setup(char *str)
 188 {
 189         return str;
 190 }
 191
 192 /*
 193  * Reads the interrupt pin to determine if interrupt is use by card.
 194  * If the interrupt is used, then gets the interrupt line from the
 195  * openfirmware and sets it in the pci_dev and pci_config line.
 196  */
 197 int pci_read_irq_line(struct pci_dev *pci_dev)
 198 {
 199         struct of_irq oirq;
 200         unsigned int virq;
 201
 202         DBG("Try to map irq for %s...\n", pci_name(pci_dev));
 203
 204 #ifdef DEBUG
 205         memset(&oirq, 0xff, sizeof(oirq));
 206 #endif
 207         /* Try to get a mapping from the device-tree */
 208         if (of_irq_map_pci(pci_dev, &oirq)) {
 209                 u8 line, pin;
 210
 211                 /* If that fails, lets fallback to what is in the config
 212                  * space and map that through the default controller. We
 213                  * also set the type to level low since that's what PCI
 214                  * interrupts are. If your platform does differently, then
 215                  * either provide a proper interrupt tree or don't use this
 216                  * function.
 217                  */
 218                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
 219                         return -1;
 220                 if (pin == 0)
 221                         return -1;
 222                 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
 223                     line == 0xff) {
 224                         return -1;
 225                 }
 226                 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
 227
 228                 virq = irq_create_mapping(NULL, line);
 229                 if (virq != NO_IRQ)
 230                         set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
 231         } else {
 232                 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
 233                     oirq.size, oirq.specifier[0], oirq.specifier[1],
 234                     oirq.controller->full_name);
 235
 236                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
 237                                              oirq.size);
 238         }
 239         if(virq == NO_IRQ) {
 240                 DBG(" -> failed to map !\n");
 241                 return -1;
 242         }
 243
 244         DBG(" -> mapped to linux irq %d\n", virq);
 245
 246         pci_dev->irq = virq;
 247
 248         return 0;
 249 }
 250 EXPORT_SYMBOL(pci_read_irq_line);
 251
 252 /*
 253  * Platform support for /proc/bus/pci/X/Y mmap()s,
 254  * modelled on the sparc64 implementation by Dave Miller.
 255  *  -- paulus.
 256  */
 257
 258 /*
 259  * Adjust vm_pgoff of VMA such that it is the physical page offset
 260  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
 261  *
 262  * Basically, the user finds the base address for his device which he wishes
 263  * to mmap.  They read the 32-bit value from the config space base register,
 264  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 265  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 266  *
 267  * Returns negative error code on failure, zero on success.
 268  */
 269 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
 270                                                resource_size_t *offset,
 271                                                enum pci_mmap_state mmap_state)
 272 {
 273         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 274         unsigned long io_offset = 0;
 275         int i, res_bit;
 276
 277         if (hose == 0)
 278                 return NULL;            /* should never happen */
 279
 280         /* If memory, add on the PCI bridge address offset */
 281         if (mmap_state == pci_mmap_mem) {
 282 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
 283                 *offset += hose->pci_mem_offset;
 284 #endif
 285                 res_bit = IORESOURCE_MEM;
 286         } else {
 287                 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 288                 *offset += io_offset;
 289                 res_bit = IORESOURCE_IO;
 290         }
 291
 292         /*
 293          * Check that the offset requested corresponds to one of the
 294          * resources of the device.
 295          */
 296         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 297                 struct resource *rp = &dev->resource[i];
 298                 int flags = rp->flags;
 299
 300                 /* treat ROM as memory (should be already) */
 301                 if (i == PCI_ROM_RESOURCE)
 302                         flags |= IORESOURCE_MEM;
 303
 304                 /* Active and same type? */
 305                 if ((flags & res_bit) == 0)
 306                         continue;
 307
 308                 /* In the range of this resource? */
 309                 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
 310                         continue;
 311
 312                 /* found it! construct the final physical address */
 313                 if (mmap_state == pci_mmap_io)
 314                         *offset += hose->io_base_phys - io_offset;
 315                 return rp;
 316         }
 317
 318         return NULL;
 319 }
 320
 321 /*
 322  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 323  * device mapping.
 324  */
 325 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
 326                                       pgprot_t protection,
 327                                       enum pci_mmap_state mmap_state,
 328                                       int write_combine)
 329 {
 330         unsigned long prot = pgprot_val(protection);
 331
 332         /* Write combine is always 0 on non-memory space mappings. On
 333          * memory space, if the user didn't pass 1, we check for a
 334          * "prefetchable" resource. This is a bit hackish, but we use
 335          * this to workaround the inability of /sysfs to provide a write
 336          * combine bit
 337          */
 338         if (mmap_state != pci_mmap_mem)
 339                 write_combine = 0;
 340         else if (write_combine == 0) {
 341                 if (rp->flags & IORESOURCE_PREFETCH)
 342                         write_combine = 1;
 343         }
 344
 345         /* XXX would be nice to have a way to ask for write-through */
 346         prot |= _PAGE_NO_CACHE;
 347         if (write_combine)
 348                 prot &= ~_PAGE_GUARDED;
 349         else
 350                 prot |= _PAGE_GUARDED;
 351
 352         return __pgprot(prot);
 353 }
 354
 355 /*
 356  * This one is used by /dev/mem and fbdev who have no clue about the
 357  * PCI device, it tries to find the PCI device first and calls the
 358  * above routine
 359  */
 360 pgprot_t pci_phys_mem_access_prot(struct file *file,
 361                                   unsigned long pfn,
 362                                   unsigned long size,
 363                                   pgprot_t protection)
 364 {
 365         struct pci_dev *pdev = NULL;
 366         struct resource *found = NULL;
 367         unsigned long prot = pgprot_val(protection);
 368         unsigned long offset = pfn << PAGE_SHIFT;
 369         int i;
 370
 371         if (page_is_ram(pfn))
 372                 return __pgprot(prot);
 373
 374         prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
 375
 376         for_each_pci_dev(pdev) {
 377                 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 378                         struct resource *rp = &pdev->resource[i];
 379                         int flags = rp->flags;
 380
 381                         /* Active and same type? */
 382                         if ((flags & IORESOURCE_MEM) == 0)
 383                                 continue;
 384                         /* In the range of this resource? */
 385                         if (offset < (rp->start & PAGE_MASK) ||
 386                             offset > rp->end)
 387                                 continue;
 388                         found = rp;
 389                         break;
 390                 }
 391                 if (found)
 392                         break;
 393         }
 394         if (found) {
 395                 if (found->flags & IORESOURCE_PREFETCH)
 396                         prot &= ~_PAGE_GUARDED;
 397                 pci_dev_put(pdev);
 398         }
 399
 400         DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
 401
 402         return __pgprot(prot);
 403 }
 404
 405
 406 /*
 407  * Perform the actual remap of the pages for a PCI device mapping, as
 408  * appropriate for this architecture.  The region in the process to map
 409  * is described by vm_start and vm_end members of VMA, the base physical
 410  * address is found in vm_pgoff.
 411  * The pci device structure is provided so that architectures may make mapping
 412  * decisions on a per-device or per-bus basis.
 413  *
 414  * Returns a negative error code on failure, zero on success.
 415  */
 416 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 417                         enum pci_mmap_state mmap_state, int write_combine)
 418 {
 419         resource_size_t offset = vma->vm_pgoff << PAGE_SHIFT;
 420         struct resource *rp;
 421         int ret;
 422
 423         rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
 424         if (rp == NULL)
 425                 return -EINVAL;
 426
 427         vma->vm_pgoff = offset >> PAGE_SHIFT;
 428         vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
 429                                                   vma->vm_page_prot,
 430                                                   mmap_state, write_combine);
 431
 432         ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 433                                vma->vm_end - vma->vm_start, vma->vm_page_prot);
 434
 435         return ret;
 436 }
 437
 438 void pci_resource_to_user(const struct pci_dev *dev, int bar,
 439                           const struct resource *rsrc,
 440                           resource_size_t *start, resource_size_t *end)
 441 {
 442         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 443         resource_size_t offset = 0;
 444
 445         if (hose == NULL)
 446                 return;
 447
 448         if (rsrc->flags & IORESOURCE_IO)
 449                 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 450
 451         /* We pass a fully fixed up address to userland for MMIO instead of
 452          * a BAR value because X is lame and expects to be able to use that
 453          * to pass to /dev/mem !
 454          *
 455          * That means that we'll have potentially 64 bits values where some
 456          * userland apps only expect 32 (like X itself since it thinks only
 457          * Sparc has 64 bits MMIO) but if we don't do that, we break it on
 458          * 32 bits CHRPs :-(
 459          *
 460          * Hopefully, the sysfs insterface is immune to that gunk. Once X
 461          * has been fixed (and the fix spread enough), we can re-enable the
 462          * 2 lines below and pass down a BAR value to userland. In that case
 463          * we'll also have to re-enable the matching code in
 464          * __pci_mmap_make_offset().
 465          *
 466          * BenH.
 467          */
 468 #if 0
 469         else if (rsrc->flags & IORESOURCE_MEM)
 470                 offset = hose->pci_mem_offset;
 471 #endif
 472
 473         *start = rsrc->start - offset;
 474         *end = rsrc->end - offset;
 475 }