arch/powerpc/kernel/pci_64.c

   1 /*
   2  * Port for PPC64 David Engebretsen, IBM Corp.
   3  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   4  *
   5  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   6  *   Rework, based on alpha PCI code.
   7  *
   8  *      This program is free software; you can redistribute it and/or
   9  *      modify it under the terms of the GNU General Public License
  10  *      as published by the Free Software Foundation; either version
  11  *      2 of the License, or (at your option) any later version.
  12  */
  13
  14 #undef DEBUG
  15
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/mm.h>
  22 #include <linux/list.h>
  23 #include <linux/syscalls.h>
  24 #include <linux/irq.h>
  25 #include <linux/vmalloc.h>
  26
  27 #include <asm/processor.h>
  28 #include <asm/io.h>
  29 #include <asm/prom.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/byteorder.h>
  32 #include <asm/machdep.h>
  33 #include <asm/ppc-pci.h>
  34
  35 unsigned long pci_probe_only = 1;
  36
  37 /* pci_io_base -- the base address from which io bars are offsets.
  38  * This is the lowest I/O base address (so bar values are always positive),
  39  * and it *must* be the start of ISA space if an ISA bus exists because
  40  * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
  41  * is mapped on the first 64K of IO space
  42  */
  43 unsigned long pci_io_base = ISA_IO_BASE;
  44 EXPORT_SYMBOL(pci_io_base);
  45
  46 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
  47 {
  48         const u32 *prop;
  49         int len;
  50
  51         prop = of_get_property(np, name, &len);
  52         if (prop && len >= 4)
  53                 return *prop;
  54         return def;
  55 }
  56
  57 static unsigned int pci_parse_of_flags(u32 addr0, int bridge)
  58 {
  59         unsigned int flags = 0;
  60
  61         if (addr0 & 0x02000000) {
  62                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
  63                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
  64                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
  65                 if (addr0 & 0x40000000)
  66                         flags |= IORESOURCE_PREFETCH
  67                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
  68                 /* Note: We don't know whether the ROM has been left enabled
  69                  * by the firmware or not. We mark it as disabled (ie, we do
  70                  * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
  71                  * do a config space read, it will be force-enabled if needed
  72                  */
  73                 if (!bridge && (addr0 & 0xff) == 0x30)
  74                         flags |= IORESOURCE_READONLY;
  75         } else if (addr0 & 0x01000000)
  76                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
  77         if (flags)
  78                 flags |= IORESOURCE_SIZEALIGN;
  79         return flags;
  80 }
  81
  82
  83 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
  84 {
  85         u64 base, size;
  86         unsigned int flags;
  87         struct resource *res;
  88         const u32 *addrs;
  89         u32 i;
  90         int proplen;
  91
  92         addrs = of_get_property(node, "assigned-addresses", &proplen);
  93         if (!addrs)
  94                 return;
  95         pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
  96         for (; proplen >= 20; proplen -= 20, addrs += 5) {
  97                 flags = pci_parse_of_flags(addrs[0], 0);
  98                 if (!flags)
  99                         continue;
 100                 base = of_read_number(&addrs[1], 2);
 101                 size = of_read_number(&addrs[3], 2);
 102                 if (!size)
 103                         continue;
 104                 i = addrs[0] & 0xff;
 105                 pr_debug("  base: %llx, size: %llx, i: %x\n",
 106                          (unsigned long long)base,
 107                          (unsigned long long)size, i);
 108
 109                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 110                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 111                 } else if (i == dev->rom_base_reg) {
 112                         res = &dev->resource[PCI_ROM_RESOURCE];
 113                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 114                 } else {
 115                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 116                         continue;
 117                 }
 118                 res->start = base;
 119                 res->end = base + size - 1;
 120                 res->flags = flags;
 121                 res->name = pci_name(dev);
 122         }
 123 }
 124
 125 struct pci_dev *of_create_pci_dev(struct device_node *node,
 126                                  struct pci_bus *bus, int devfn)
 127 {
 128         struct pci_dev *dev;
 129         const char *type;
 130
 131         dev = alloc_pci_dev();
 132         if (!dev)
 133                 return NULL;
 134         type = of_get_property(node, "device_type", NULL);
 135         if (type == NULL)
 136                 type = "";
 137
 138         pr_debug("    create device, devfn: %x, type: %s\n", devfn, type);
 139
 140         dev->bus = bus;
 141         dev->sysdata = node;
 142         dev->dev.parent = bus->bridge;
 143         dev->dev.bus = &pci_bus_type;
 144         dev->devfn = devfn;
 145         dev->multifunction = 0;         /* maybe a lie? */
 146
 147         dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
 148         dev->device = get_int_prop(node, "device-id", 0xffff);
 149         dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
 150         dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
 151
 152         dev->cfg_size = pci_cfg_space_size(dev);
 153
 154         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 155                 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 156         dev->class = get_int_prop(node, "class-code", 0);
 157         dev->revision = get_int_prop(node, "revision-id", 0);
 158
 159         pr_debug("    class: 0x%x\n", dev->class);
 160         pr_debug("    revision: 0x%x\n", dev->revision);
 161
 162         dev->current_state = 4;         /* unknown power state */
 163         dev->error_state = pci_channel_io_normal;
 164         dev->dma_mask = 0xffffffff;
 165
 166         if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
 167                 /* a PCI-PCI bridge */
 168                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 169                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 170         } else if (!strcmp(type, "cardbus")) {
 171                 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 172         } else {
 173                 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 174                 dev->rom_base_reg = PCI_ROM_ADDRESS;
 175                 /* Maybe do a default OF mapping here */
 176                 dev->irq = NO_IRQ;
 177         }
 178
 179         pci_parse_of_addrs(node, dev);
 180
 181         pr_debug("    adding to system ...\n");
 182
 183         pci_device_add(dev, bus);
 184
 185         return dev;
 186 }
 187 EXPORT_SYMBOL(of_create_pci_dev);
 188
 189 static void __devinit __of_scan_bus(struct device_node *node,
 190                                     struct pci_bus *bus, int rescan_existing)
 191 {
 192         struct device_node *child;
 193         const u32 *reg;
 194         int reglen, devfn;
 195         struct pci_dev *dev;
 196
 197         pr_debug("of_scan_bus(%s) bus no %d... \n",
 198                  node->full_name, bus->number);
 199
 200         /* Scan direct children */
 201         for_each_child_of_node(node, child) {
 202                 pr_debug("  * %s\n", child->full_name);
 203                 reg = of_get_property(child, "reg", &reglen);
 204                 if (reg == NULL || reglen < 20)
 205                         continue;
 206                 devfn = (reg[0] >> 8) & 0xff;
 207
 208                 /* create a new pci_dev for this device */
 209                 dev = of_create_pci_dev(child, bus, devfn);
 210                 if (!dev)
 211                         continue;
 212                 pr_debug("    dev header type: %x\n", dev->hdr_type);
 213         }
 214
 215         /* Apply all fixups necessary. We don't fixup the bus "self"
 216          * for an existing bridge that is being rescanned
 217          */
 218         if (!rescan_existing)
 219                 pcibios_setup_bus_self(bus);
 220         pcibios_setup_bus_devices(bus);
 221
 222         /* Now scan child busses */
 223         list_for_each_entry(dev, &bus->devices, bus_list) {
 224                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 225                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
 226                         struct device_node *child = pci_device_to_OF_node(dev);
 227                         if (dev)
 228                                 of_scan_pci_bridge(child, dev);
 229                 }
 230         }
 231 }
 232
 233 void __devinit of_scan_bus(struct device_node *node,
 234                            struct pci_bus *bus)
 235 {
 236         __of_scan_bus(node, bus, 0);
 237 }
 238 EXPORT_SYMBOL_GPL(of_scan_bus);
 239
 240 void __devinit of_rescan_bus(struct device_node *node,
 241                              struct pci_bus *bus)
 242 {
 243         __of_scan_bus(node, bus, 1);
 244 }
 245 EXPORT_SYMBOL_GPL(of_rescan_bus);
 246
 247 void __devinit of_scan_pci_bridge(struct device_node *node,
 248                                   struct pci_dev *dev)
 249 {
 250         struct pci_bus *bus;
 251         const u32 *busrange, *ranges;
 252         int len, i, mode;
 253         struct resource *res;
 254         unsigned int flags;
 255         u64 size;
 256
 257         pr_debug("of_scan_pci_bridge(%s)\n", node->full_name);
 258
 259         /* parse bus-range property */
 260         busrange = of_get_property(node, "bus-range", &len);
 261         if (busrange == NULL || len != 8) {
 262                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 263                        node->full_name);
 264                 return;
 265         }
 266         ranges = of_get_property(node, "ranges", &len);
 267         if (ranges == NULL) {
 268                 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
 269                        node->full_name);
 270                 return;
 271         }
 272
 273         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 274         if (!bus) {
 275                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 276                        node->full_name);
 277                 return;
 278         }
 279
 280         bus->primary = dev->bus->number;
 281         bus->subordinate = busrange[1];
 282         bus->bridge_ctl = 0;
 283         bus->sysdata = node;
 284
 285         /* parse ranges property */
 286         /* PCI #address-cells == 3 and #size-cells == 2 always */
 287         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 288         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 289                 res->flags = 0;
 290                 bus->resource[i] = res;
 291                 ++res;
 292         }
 293         i = 1;
 294         for (; len >= 32; len -= 32, ranges += 8) {
 295                 flags = pci_parse_of_flags(ranges[0], 1);
 296                 size = of_read_number(&ranges[6], 2);
 297                 if (flags == 0 || size == 0)
 298                         continue;
 299                 if (flags & IORESOURCE_IO) {
 300                         res = bus->resource[0];
 301                         if (res->flags) {
 302                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 303                                        " for bridge %s\n", node->full_name);
 304                                 continue;
 305                         }
 306                 } else {
 307                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 308                                 printk(KERN_ERR "PCI: too many memory ranges"
 309                                        " for bridge %s\n", node->full_name);
 310                                 continue;
 311                         }
 312                         res = bus->resource[i];
 313                         ++i;
 314                 }
 315                 res->start = of_read_number(&ranges[1], 2);
 316                 res->end = res->start + size - 1;
 317                 res->flags = flags;
 318         }
 319         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 320                 bus->number);
 321         pr_debug("    bus name: %s\n", bus->name);
 322
 323         mode = PCI_PROBE_NORMAL;
 324         if (ppc_md.pci_probe_mode)
 325                 mode = ppc_md.pci_probe_mode(bus);
 326         pr_debug("    probe mode: %d\n", mode);
 327
 328         if (mode == PCI_PROBE_DEVTREE)
 329                 of_scan_bus(node, bus);
 330         else if (mode == PCI_PROBE_NORMAL)
 331                 pci_scan_child_bus(bus);
 332 }
 333 EXPORT_SYMBOL(of_scan_pci_bridge);
 334
 335 void __devinit scan_phb(struct pci_controller *hose)
 336 {
 337         struct pci_bus *bus;
 338         struct device_node *node = hose->dn;
 339         int mode;
 340
 341         pr_debug("PCI: Scanning PHB %s\n",
 342                  node ? node->full_name : "<NO NAME>");
 343
 344         /* Create an empty bus for the toplevel */
 345         bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
 346         if (bus == NULL) {
 347                 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
 348                        hose->global_number);
 349                 return;
 350         }
 351         bus->secondary = hose->first_busno;
 352         hose->bus = bus;
 353
 354         /* Get some IO space for the new PHB */
 355         pcibios_map_io_space(bus);
 356
 357         /* Wire up PHB bus resources */
 358         pcibios_setup_phb_resources(hose);
 359
 360         /* Get probe mode and perform scan */
 361         mode = PCI_PROBE_NORMAL;
 362         if (node && ppc_md.pci_probe_mode)
 363                 mode = ppc_md.pci_probe_mode(bus);
 364         pr_debug("    probe mode: %d\n", mode);
 365         if (mode == PCI_PROBE_DEVTREE) {
 366                 bus->subordinate = hose->last_busno;
 367                 of_scan_bus(node, bus);
 368         }
 369
 370         if (mode == PCI_PROBE_NORMAL)
 371                 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
 372 }
 373
 374 static int __init pcibios_init(void)
 375 {
 376         struct pci_controller *hose, *tmp;
 377
 378         printk(KERN_INFO "PCI: Probing PCI hardware\n");
 379
 380         /* For now, override phys_mem_access_prot. If we need it,g
 381          * later, we may move that initialization to each ppc_md
 382          */
 383         ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
 384
 385         if (pci_probe_only)
 386                 ppc_pci_flags |= PPC_PCI_PROBE_ONLY;
 387
 388         /* On ppc64, we always enable PCI domains and we keep domain 0
 389          * backward compatible in /proc for video cards
 390          */
 391         ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
 392
 393         /* Scan all of the recorded PCI controllers.  */
 394         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 395                 scan_phb(hose);
 396                 pci_bus_add_devices(hose->bus);
 397         }
 398
 399         /* Call common code to handle resource allocation */
 400         pcibios_resource_survey();
 401
 402         printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
 403
 404         return 0;
 405 }
 406
 407 subsys_initcall(pcibios_init);
 408
 409 #ifdef CONFIG_HOTPLUG
 410
 411 int pcibios_unmap_io_space(struct pci_bus *bus)
 412 {
 413         struct pci_controller *hose;
 414
 415         WARN_ON(bus == NULL);
 416
 417         /* If this is not a PHB, we only flush the hash table over
 418          * the area mapped by this bridge. We don't play with the PTE
 419          * mappings since we might have to deal with sub-page alignemnts
 420          * so flushing the hash table is the only sane way to make sure
 421          * that no hash entries are covering that removed bridge area
 422          * while still allowing other busses overlapping those pages
 423          *
 424          * Note: If we ever support P2P hotplug on Book3E, we'll have
 425          * to do an appropriate TLB flush here too
 426          */
 427         if (bus->self) {
 428                 struct resource *res = bus->resource[0];
 429
 430                 pr_debug("IO unmapping for PCI-PCI bridge %s\n",
 431                          pci_name(bus->self));
 432
 433 #ifdef CONFIG_PPC_STD_MMU_64
 434                 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
 435                                          res->end + _IO_BASE + 1);
 436 #endif
 437                 return 0;
 438         }
 439
 440         /* Get the host bridge */
 441         hose = pci_bus_to_host(bus);
 442
 443         /* Check if we have IOs allocated */
 444         if (hose->io_base_alloc == 0)
 445                 return 0;
 446
 447         pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
 448         pr_debug("  alloc=0x%p\n", hose->io_base_alloc);
 449
 450         /* This is a PHB, we fully unmap the IO area */
 451         vunmap(hose->io_base_alloc);
 452
 453         return 0;
 454 }
 455 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
 456
 457 #endif /* CONFIG_HOTPLUG */
 458
 459 int __devinit pcibios_map_io_space(struct pci_bus *bus)
 460 {
 461         struct vm_struct *area;
 462         unsigned long phys_page;
 463         unsigned long size_page;
 464         unsigned long io_virt_offset;
 465         struct pci_controller *hose;
 466
 467         WARN_ON(bus == NULL);
 468
 469         /* If this not a PHB, nothing to do, page tables still exist and
 470          * thus HPTEs will be faulted in when needed
 471          */
 472         if (bus->self) {
 473                 pr_debug("IO mapping for PCI-PCI bridge %s\n",
 474                          pci_name(bus->self));
 475                 pr_debug("  virt=0x%016llx...0x%016llx\n",
 476                          bus->resource[0]->start + _IO_BASE,
 477                          bus->resource[0]->end + _IO_BASE);
 478                 return 0;
 479         }
 480
 481         /* Get the host bridge */
 482         hose = pci_bus_to_host(bus);
 483         phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
 484         size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
 485
 486         /* Make sure IO area address is clear */
 487         hose->io_base_alloc = NULL;
 488
 489         /* If there's no IO to map on that bus, get away too */
 490         if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
 491                 return 0;
 492
 493         /* Let's allocate some IO space for that guy. We don't pass
 494          * VM_IOREMAP because we don't care about alignment tricks that
 495          * the core does in that case. Maybe we should due to stupid card
 496          * with incomplete address decoding but I'd rather not deal with
 497          * those outside of the reserved 64K legacy region.
 498          */
 499         area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
 500         if (area == NULL)
 501                 return -ENOMEM;
 502         hose->io_base_alloc = area->addr;
 503         hose->io_base_virt = (void __iomem *)(area->addr +
 504                                               hose->io_base_phys - phys_page);
 505
 506         pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
 507         pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
 508                  hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
 509         pr_debug("  size=0x%016lx (alloc=0x%016lx)\n",
 510                  hose->pci_io_size, size_page);
 511
 512         /* Establish the mapping */
 513         if (__ioremap_at(phys_page, area->addr, size_page,
 514                          _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
 515                 return -ENOMEM;
 516
 517         /* Fixup hose IO resource */
 518         io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 519         hose->io_resource.start += io_virt_offset;
 520         hose->io_resource.end += io_virt_offset;
 521
 522         pr_debug("  hose->io_resource=0x%016llx...0x%016llx\n",
 523                  hose->io_resource.start, hose->io_resource.end);
 524
 525         return 0;
 526 }
 527 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
 528
 529 #define IOBASE_BRIDGE_NUMBER    0
 530 #define IOBASE_MEMORY           1
 531 #define IOBASE_IO               2
 532 #define IOBASE_ISA_IO           3
 533 #define IOBASE_ISA_MEM          4
 534
 535 long sys_pciconfig_iobase(long which, unsigned long in_bus,
 536                           unsigned long in_devfn)
 537 {
 538         struct pci_controller* hose;
 539         struct list_head *ln;
 540         struct pci_bus *bus = NULL;
 541         struct device_node *hose_node;
 542
 543         /* Argh ! Please forgive me for that hack, but that's the
 544          * simplest way to get existing XFree to not lockup on some
 545          * G5 machines... So when something asks for bus 0 io base
 546          * (bus 0 is HT root), we return the AGP one instead.
 547          */
 548         if (in_bus == 0 && machine_is_compatible("MacRISC4")) {
 549                 struct device_node *agp;
 550
 551                 agp = of_find_compatible_node(NULL, NULL, "u3-agp");
 552                 if (agp)
 553                         in_bus = 0xf0;
 554                 of_node_put(agp);
 555         }
 556
 557         /* That syscall isn't quite compatible with PCI domains, but it's
 558          * used on pre-domains setup. We return the first match
 559          */
 560
 561         for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
 562                 bus = pci_bus_b(ln);
 563                 if (in_bus >= bus->number && in_bus <= bus->subordinate)
 564                         break;
 565                 bus = NULL;
 566         }
 567         if (bus == NULL || bus->sysdata == NULL)
 568                 return -ENODEV;
 569
 570         hose_node = (struct device_node *)bus->sysdata;
 571         hose = PCI_DN(hose_node)->phb;
 572
 573         switch (which) {
 574         case IOBASE_BRIDGE_NUMBER:
 575                 return (long)hose->first_busno;
 576         case IOBASE_MEMORY:
 577                 return (long)hose->pci_mem_offset;
 578         case IOBASE_IO:
 579                 return (long)hose->io_base_phys;
 580         case IOBASE_ISA_IO:
 581                 return (long)isa_io_base;
 582         case IOBASE_ISA_MEM:
 583                 return -EINVAL;
 584         }
 585
 586         return -EOPNOTSUPP;
 587 }
 588
 589 #ifdef CONFIG_NUMA
 590 int pcibus_to_node(struct pci_bus *bus)
 591 {
 592         struct pci_controller *phb = pci_bus_to_host(bus);
 593         return phb->node;
 594 }
 595 EXPORT_SYMBOL(pcibus_to_node);
 596 #endif