2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) udbg_printf(fmt)
42 unsigned long pci_probe_only
= 1;
43 int pci_assign_all_buses
= 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask
;
51 EXPORT_SYMBOL(io_page_mask
);
53 #ifdef CONFIG_PPC_MULTIPLATFORM
54 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
55 static void do_bus_setup(struct pci_bus
*bus
);
58 /* pci_io_base -- the base address from which io bars are offsets.
59 * This is the lowest I/O base address (so bar values are always positive),
60 * and it *must* be the start of ISA space if an ISA bus exists because
61 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
62 * page is mapped and isa_io_limit prevents access to it.
64 unsigned long isa_io_base
; /* NULL if no ISA bus */
65 EXPORT_SYMBOL(isa_io_base
);
66 unsigned long pci_io_base
;
67 EXPORT_SYMBOL(pci_io_base
);
69 void iSeries_pcibios_init(void);
73 struct dma_mapping_ops pci_dma_ops
;
74 EXPORT_SYMBOL(pci_dma_ops
);
76 int global_phb_number
; /* Global phb counter */
78 /* Cached ISA bridge dev. */
79 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
81 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
83 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
84 dev
->vendor
= PCI_VENDOR_ID_AMD
;
85 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
88 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
90 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
93 unsigned long offset
= 0;
94 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
99 if (res
->flags
& IORESOURCE_IO
)
100 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
102 if (res
->flags
& IORESOURCE_MEM
)
103 offset
= hose
->pci_mem_offset
;
105 region
->start
= res
->start
- offset
;
106 region
->end
= res
->end
- offset
;
109 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
110 struct pci_bus_region
*region
)
112 unsigned long offset
= 0;
113 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
118 if (res
->flags
& IORESOURCE_IO
)
119 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
121 if (res
->flags
& IORESOURCE_MEM
)
122 offset
= hose
->pci_mem_offset
;
124 res
->start
= region
->start
+ offset
;
125 res
->end
= region
->end
+ offset
;
128 #ifdef CONFIG_HOTPLUG
129 EXPORT_SYMBOL(pcibios_resource_to_bus
);
130 EXPORT_SYMBOL(pcibios_bus_to_resource
);
134 * We need to avoid collisions with `mirrored' VGA ports
135 * and other strange ISA hardware, so we always want the
136 * addresses to be allocated in the 0x000-0x0ff region
139 * Why? Because some silly external IO cards only decode
140 * the low 10 bits of the IO address. The 0x00-0xff region
141 * is reserved for motherboard devices that decode all 16
142 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
143 * but we want to try to avoid allocating at 0x2900-0x2bff
144 * which might have be mirrored at 0x0100-0x03ff..
146 void pcibios_align_resource(void *data
, struct resource
*res
,
147 unsigned long size
, unsigned long align
)
149 struct pci_dev
*dev
= data
;
150 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
151 unsigned long start
= res
->start
;
152 unsigned long alignto
;
154 if (res
->flags
& IORESOURCE_IO
) {
155 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
157 /* Make sure we start at our min on all hoses */
158 if (start
- offset
< PCIBIOS_MIN_IO
)
159 start
= PCIBIOS_MIN_IO
+ offset
;
162 * Put everything into 0x00-0xff region modulo 0x400
165 start
= (start
+ 0x3ff) & ~0x3ff;
167 } else if (res
->flags
& IORESOURCE_MEM
) {
168 /* Make sure we start at our min on all hoses */
169 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
170 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
172 /* Align to multiple of size of minimum base. */
173 alignto
= max(0x1000UL
, align
);
174 start
= ALIGN(start
, alignto
);
180 static DEFINE_SPINLOCK(hose_spinlock
);
183 * pci_controller(phb) initialized common variables.
185 static void __devinit
pci_setup_pci_controller(struct pci_controller
*hose
)
187 memset(hose
, 0, sizeof(struct pci_controller
));
189 spin_lock(&hose_spinlock
);
190 hose
->global_number
= global_phb_number
++;
191 list_add_tail(&hose
->list_node
, &hose_list
);
192 spin_unlock(&hose_spinlock
);
195 static void add_linux_pci_domain(struct device_node
*dev
,
196 struct pci_controller
*phb
)
198 struct property
*of_prop
;
201 of_prop
= (struct property
*)
202 get_property(dev
, "linux,pci-domain", &size
);
205 WARN_ON(of_prop
&& size
< sizeof(int));
206 if (of_prop
&& size
< sizeof(int))
208 size
= sizeof(struct property
) + sizeof(int);
209 if (of_prop
== NULL
) {
211 of_prop
= kmalloc(size
, GFP_KERNEL
);
213 of_prop
= alloc_bootmem(size
);
215 memset(of_prop
, 0, sizeof(struct property
));
216 of_prop
->name
= "linux,pci-domain";
217 of_prop
->length
= sizeof(int);
218 of_prop
->value
= (unsigned char *)&of_prop
[1];
219 *((int *)of_prop
->value
) = phb
->global_number
;
220 prom_add_property(dev
, of_prop
);
223 struct pci_controller
* pcibios_alloc_controller(struct device_node
*dev
)
225 struct pci_controller
*phb
;
228 phb
= kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
230 phb
= alloc_bootmem(sizeof (struct pci_controller
));
233 pci_setup_pci_controller(phb
);
234 phb
->arch_data
= dev
;
235 phb
->is_dynamic
= mem_init_done
;
237 add_linux_pci_domain(dev
, phb
);
241 void pcibios_free_controller(struct pci_controller
*phb
)
243 if (phb
->arch_data
) {
244 struct device_node
*np
= phb
->arch_data
;
245 int *domain
= (int *)get_property(np
,
246 "linux,pci-domain", NULL
);
254 void __devinit
pcibios_claim_one_bus(struct pci_bus
*b
)
257 struct pci_bus
*child_bus
;
259 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
262 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
263 struct resource
*r
= &dev
->resource
[i
];
265 if (r
->parent
|| !r
->start
|| !r
->flags
)
267 pci_claim_resource(dev
, i
);
271 list_for_each_entry(child_bus
, &b
->children
, node
)
272 pcibios_claim_one_bus(child_bus
);
275 #ifndef CONFIG_PPC_ISERIES
276 static void __init
pcibios_claim_of_setup(void)
280 list_for_each_entry(b
, &pci_root_buses
, node
)
281 pcibios_claim_one_bus(b
);
285 #ifdef CONFIG_PPC_MULTIPLATFORM
286 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
291 prop
= (u32
*) get_property(np
, name
, &len
);
292 if (prop
&& len
>= 4)
297 static unsigned int pci_parse_of_flags(u32 addr0
)
299 unsigned int flags
= 0;
301 if (addr0
& 0x02000000) {
302 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
303 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
304 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
305 if (addr0
& 0x40000000)
306 flags
|= IORESOURCE_PREFETCH
307 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
308 } else if (addr0
& 0x01000000)
309 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
313 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
315 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
319 struct resource
*res
;
323 addrs
= (u32
*) get_property(node
, "assigned-addresses", &proplen
);
326 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
327 flags
= pci_parse_of_flags(addrs
[0]);
330 base
= GET_64BIT(addrs
, 1);
331 size
= GET_64BIT(addrs
, 3);
335 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
336 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
337 } else if (i
== dev
->rom_base_reg
) {
338 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
339 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
341 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
345 res
->end
= base
+ size
- 1;
347 res
->name
= pci_name(dev
);
348 fixup_resource(res
, dev
);
352 struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
353 struct pci_bus
*bus
, int devfn
)
358 dev
= kmalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
361 type
= get_property(node
, "device_type", NULL
);
365 memset(dev
, 0, sizeof(struct pci_dev
));
368 dev
->dev
.parent
= bus
->bridge
;
369 dev
->dev
.bus
= &pci_bus_type
;
371 dev
->multifunction
= 0; /* maybe a lie? */
373 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
374 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
375 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
376 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
378 dev
->cfg_size
= 256; /*pci_cfg_space_size(dev);*/
380 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
381 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
382 dev
->class = get_int_prop(node
, "class-code", 0);
384 dev
->current_state
= 4; /* unknown power state */
386 if (!strcmp(type
, "pci")) {
387 /* a PCI-PCI bridge */
388 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
389 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
390 } else if (!strcmp(type
, "cardbus")) {
391 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
393 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
394 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
396 if (node
->n_intrs
> 0) {
397 dev
->irq
= node
->intrs
[0].line
;
398 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
,
403 pci_parse_of_addrs(node
, dev
);
405 pci_device_add(dev
, bus
);
407 /* XXX pci_scan_msi_device(dev); */
411 EXPORT_SYMBOL(of_create_pci_dev
);
413 void __devinit
of_scan_bus(struct device_node
*node
,
416 struct device_node
*child
= NULL
;
421 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
422 reg
= (u32
*) get_property(child
, "reg", ®len
);
423 if (reg
== NULL
|| reglen
< 20)
425 devfn
= (reg
[0] >> 8) & 0xff;
426 /* create a new pci_dev for this device */
427 dev
= of_create_pci_dev(child
, bus
, devfn
);
430 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
431 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
432 of_scan_pci_bridge(child
, dev
);
437 EXPORT_SYMBOL(of_scan_bus
);
439 void __devinit
of_scan_pci_bridge(struct device_node
*node
,
443 u32
*busrange
, *ranges
;
445 struct resource
*res
;
449 /* parse bus-range property */
450 busrange
= (u32
*) get_property(node
, "bus-range", &len
);
451 if (busrange
== NULL
|| len
!= 8) {
452 printk(KERN_ERR
"Can't get bus-range for PCI-PCI bridge %s\n",
456 ranges
= (u32
*) get_property(node
, "ranges", &len
);
457 if (ranges
== NULL
) {
458 printk(KERN_ERR
"Can't get ranges for PCI-PCI bridge %s\n",
463 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
465 printk(KERN_ERR
"Failed to create pci bus for %s\n",
470 bus
->primary
= dev
->bus
->number
;
471 bus
->subordinate
= busrange
[1];
475 /* parse ranges property */
476 /* PCI #address-cells == 3 and #size-cells == 2 always */
477 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
478 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
480 bus
->resource
[i
] = res
;
484 for (; len
>= 32; len
-= 32, ranges
+= 8) {
485 flags
= pci_parse_of_flags(ranges
[0]);
486 size
= GET_64BIT(ranges
, 6);
487 if (flags
== 0 || size
== 0)
489 if (flags
& IORESOURCE_IO
) {
490 res
= bus
->resource
[0];
492 printk(KERN_ERR
"PCI: ignoring extra I/O range"
493 " for bridge %s\n", node
->full_name
);
497 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
498 printk(KERN_ERR
"PCI: too many memory ranges"
499 " for bridge %s\n", node
->full_name
);
502 res
= bus
->resource
[i
];
505 res
->start
= GET_64BIT(ranges
, 1);
506 res
->end
= res
->start
+ size
- 1;
508 fixup_resource(res
, dev
);
510 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
513 mode
= PCI_PROBE_NORMAL
;
514 if (ppc_md
.pci_probe_mode
)
515 mode
= ppc_md
.pci_probe_mode(bus
);
516 if (mode
== PCI_PROBE_DEVTREE
)
517 of_scan_bus(node
, bus
);
518 else if (mode
== PCI_PROBE_NORMAL
)
519 pci_scan_child_bus(bus
);
521 EXPORT_SYMBOL(of_scan_pci_bridge
);
522 #endif /* CONFIG_PPC_MULTIPLATFORM */
524 void __devinit
scan_phb(struct pci_controller
*hose
)
527 struct device_node
*node
= hose
->arch_data
;
529 struct resource
*res
;
531 bus
= pci_create_bus(NULL
, hose
->first_busno
, hose
->ops
, node
);
533 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
534 hose
->global_number
);
537 bus
->secondary
= hose
->first_busno
;
540 bus
->resource
[0] = res
= &hose
->io_resource
;
541 if (res
->flags
&& request_resource(&ioport_resource
, res
))
542 printk(KERN_ERR
"Failed to request PCI IO region "
543 "on PCI domain %04x\n", hose
->global_number
);
545 for (i
= 0; i
< 3; ++i
) {
546 res
= &hose
->mem_resources
[i
];
547 bus
->resource
[i
+1] = res
;
548 if (res
->flags
&& request_resource(&iomem_resource
, res
))
549 printk(KERN_ERR
"Failed to request PCI memory region "
550 "on PCI domain %04x\n", hose
->global_number
);
553 mode
= PCI_PROBE_NORMAL
;
554 #ifdef CONFIG_PPC_MULTIPLATFORM
555 if (ppc_md
.pci_probe_mode
)
556 mode
= ppc_md
.pci_probe_mode(bus
);
557 if (mode
== PCI_PROBE_DEVTREE
) {
558 bus
->subordinate
= hose
->last_busno
;
559 of_scan_bus(node
, bus
);
561 #endif /* CONFIG_PPC_MULTIPLATFORM */
562 if (mode
== PCI_PROBE_NORMAL
)
563 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
564 pci_bus_add_devices(bus
);
567 static int __init
pcibios_init(void)
569 struct pci_controller
*hose
, *tmp
;
571 /* For now, override phys_mem_access_prot. If we need it,
572 * later, we may move that initialization to each ppc_md
574 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
576 #ifdef CONFIG_PPC_ISERIES
577 iSeries_pcibios_init();
580 printk("PCI: Probing PCI hardware\n");
582 /* Scan all of the recorded PCI controllers. */
583 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
586 #ifndef CONFIG_PPC_ISERIES
588 pcibios_claim_of_setup();
590 /* FIXME: `else' will be removed when
591 pci_assign_unassigned_resources() is able to work
592 correctly with [partially] allocated PCI tree. */
593 pci_assign_unassigned_resources();
594 #endif /* !CONFIG_PPC_ISERIES */
596 /* Call machine dependent final fixup */
597 if (ppc_md
.pcibios_fixup
)
598 ppc_md
.pcibios_fixup();
600 /* Cache the location of the ISA bridge (if we have one) */
601 ppc64_isabridge_dev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
602 if (ppc64_isabridge_dev
!= NULL
)
603 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev
));
605 #ifdef CONFIG_PPC_MULTIPLATFORM
606 /* map in PCI I/O space */
610 printk("PCI: Probing PCI hardware done\n");
615 subsys_initcall(pcibios_init
);
617 char __init
*pcibios_setup(char *str
)
622 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
627 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
630 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
631 struct resource
*res
= &dev
->resource
[i
];
633 /* Only set up the requested stuff */
634 if (!(mask
& (1<<i
)))
637 if (res
->flags
& IORESOURCE_IO
)
638 cmd
|= PCI_COMMAND_IO
;
639 if (res
->flags
& IORESOURCE_MEM
)
640 cmd
|= PCI_COMMAND_MEMORY
;
644 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
646 /* Enable the appropriate bits in the PCI command register. */
647 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
653 * Return the domain number for this bus.
655 int pci_domain_nr(struct pci_bus
*bus
)
657 #ifdef CONFIG_PPC_ISERIES
660 struct pci_controller
*hose
= pci_bus_to_host(bus
);
662 return hose
->global_number
;
666 EXPORT_SYMBOL(pci_domain_nr
);
668 /* Decide whether to display the domain number in /proc */
669 int pci_proc_domain(struct pci_bus
*bus
)
671 #ifdef CONFIG_PPC_ISERIES
674 struct pci_controller
*hose
= pci_bus_to_host(bus
);
680 * Platform support for /proc/bus/pci/X/Y mmap()s,
681 * modelled on the sparc64 implementation by Dave Miller.
686 * Adjust vm_pgoff of VMA such that it is the physical page offset
687 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
689 * Basically, the user finds the base address for his device which he wishes
690 * to mmap. They read the 32-bit value from the config space base register,
691 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
692 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
694 * Returns negative error code on failure, zero on success.
696 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
697 unsigned long *offset
,
698 enum pci_mmap_state mmap_state
)
700 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
701 unsigned long io_offset
= 0;
705 return NULL
; /* should never happen */
707 /* If memory, add on the PCI bridge address offset */
708 if (mmap_state
== pci_mmap_mem
) {
709 *offset
+= hose
->pci_mem_offset
;
710 res_bit
= IORESOURCE_MEM
;
712 io_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
713 *offset
+= io_offset
;
714 res_bit
= IORESOURCE_IO
;
718 * Check that the offset requested corresponds to one of the
719 * resources of the device.
721 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
722 struct resource
*rp
= &dev
->resource
[i
];
723 int flags
= rp
->flags
;
725 /* treat ROM as memory (should be already) */
726 if (i
== PCI_ROM_RESOURCE
)
727 flags
|= IORESOURCE_MEM
;
729 /* Active and same type? */
730 if ((flags
& res_bit
) == 0)
733 /* In the range of this resource? */
734 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
737 /* found it! construct the final physical address */
738 if (mmap_state
== pci_mmap_io
)
739 *offset
+= hose
->io_base_phys
- io_offset
;
747 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
750 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
752 enum pci_mmap_state mmap_state
,
755 unsigned long prot
= pgprot_val(protection
);
757 /* Write combine is always 0 on non-memory space mappings. On
758 * memory space, if the user didn't pass 1, we check for a
759 * "prefetchable" resource. This is a bit hackish, but we use
760 * this to workaround the inability of /sysfs to provide a write
763 if (mmap_state
!= pci_mmap_mem
)
765 else if (write_combine
== 0) {
766 if (rp
->flags
& IORESOURCE_PREFETCH
)
770 /* XXX would be nice to have a way to ask for write-through */
771 prot
|= _PAGE_NO_CACHE
;
773 prot
&= ~_PAGE_GUARDED
;
775 prot
|= _PAGE_GUARDED
;
777 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev
), rp
->start
,
780 return __pgprot(prot
);
784 * This one is used by /dev/mem and fbdev who have no clue about the
785 * PCI device, it tries to find the PCI device first and calls the
788 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
793 struct pci_dev
*pdev
= NULL
;
794 struct resource
*found
= NULL
;
795 unsigned long prot
= pgprot_val(protection
);
796 unsigned long offset
= pfn
<< PAGE_SHIFT
;
799 if (page_is_ram(pfn
))
800 return __pgprot(prot
);
802 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
804 for_each_pci_dev(pdev
) {
805 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
806 struct resource
*rp
= &pdev
->resource
[i
];
807 int flags
= rp
->flags
;
809 /* Active and same type? */
810 if ((flags
& IORESOURCE_MEM
) == 0)
812 /* In the range of this resource? */
813 if (offset
< (rp
->start
& PAGE_MASK
) ||
823 if (found
->flags
& IORESOURCE_PREFETCH
)
824 prot
&= ~_PAGE_GUARDED
;
828 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
830 return __pgprot(prot
);
835 * Perform the actual remap of the pages for a PCI device mapping, as
836 * appropriate for this architecture. The region in the process to map
837 * is described by vm_start and vm_end members of VMA, the base physical
838 * address is found in vm_pgoff.
839 * The pci device structure is provided so that architectures may make mapping
840 * decisions on a per-device or per-bus basis.
842 * Returns a negative error code on failure, zero on success.
844 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
845 enum pci_mmap_state mmap_state
,
848 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
852 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
856 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
857 vma
->vm_flags
|= VM_SHM
| VM_LOCKED
| VM_IO
;
858 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
860 mmap_state
, write_combine
);
862 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
863 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
868 #ifdef CONFIG_PPC_MULTIPLATFORM
869 static ssize_t
pci_show_devspec(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
871 struct pci_dev
*pdev
;
872 struct device_node
*np
;
874 pdev
= to_pci_dev (dev
);
875 np
= pci_device_to_OF_node(pdev
);
876 if (np
== NULL
|| np
->full_name
== NULL
)
878 return sprintf(buf
, "%s", np
->full_name
);
880 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
881 #endif /* CONFIG_PPC_MULTIPLATFORM */
883 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
885 #ifdef CONFIG_PPC_MULTIPLATFORM
886 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
887 #endif /* CONFIG_PPC_MULTIPLATFORM */
890 #ifdef CONFIG_PPC_MULTIPLATFORM
892 #define ISA_SPACE_MASK 0x1
893 #define ISA_SPACE_IO 0x1
895 static void __devinit
pci_process_ISA_OF_ranges(struct device_node
*isa_node
,
896 unsigned long phb_io_base_phys
,
897 void __iomem
* phb_io_base_virt
)
899 /* Remove these asap */
913 struct isa_address isa_addr
;
914 struct pci_address pci_addr
;
918 struct isa_range
*range
;
919 unsigned long pci_addr
;
920 unsigned int isa_addr
;
924 range
= (struct isa_range
*) get_property(isa_node
, "ranges", &rlen
);
925 if (range
== NULL
|| (rlen
< sizeof(struct isa_range
))) {
926 printk(KERN_ERR
"no ISA ranges or unexpected isa range size,"
928 __ioremap_explicit(phb_io_base_phys
,
929 (unsigned long)phb_io_base_virt
,
930 0x10000, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
934 /* From "ISA Binding to 1275"
935 * The ranges property is laid out as an array of elements,
936 * each of which comprises:
937 * cells 0 - 1: an ISA address
938 * cells 2 - 4: a PCI address
939 * (size depending on dev->n_addr_cells)
940 * cell 5: the size of the range
942 if ((range
->isa_addr
.a_hi
&& ISA_SPACE_MASK
) == ISA_SPACE_IO
) {
943 isa_addr
= range
->isa_addr
.a_lo
;
944 pci_addr
= (unsigned long) range
->pci_addr
.a_mid
<< 32 |
945 range
->pci_addr
.a_lo
;
947 /* Assume these are both zero */
948 if ((pci_addr
!= 0) || (isa_addr
!= 0)) {
949 printk(KERN_ERR
"unexpected isa to pci mapping: %s\n",
954 size
= PAGE_ALIGN(range
->size
);
956 __ioremap_explicit(phb_io_base_phys
,
957 (unsigned long) phb_io_base_virt
,
958 size
, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
962 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
963 struct device_node
*dev
, int prim
)
965 unsigned int *ranges
, pci_space
;
969 struct resource
*res
;
970 int np
, na
= prom_n_addr_cells(dev
);
971 unsigned long pci_addr
, cpu_phys_addr
;
975 /* From "PCI Binding to 1275"
976 * The ranges property is laid out as an array of elements,
977 * each of which comprises:
978 * cells 0 - 2: a PCI address
979 * cells 3 or 3+4: a CPU physical address
980 * (size depending on dev->n_addr_cells)
981 * cells 4+5 or 5+6: the size of the range
983 ranges
= (unsigned int *) get_property(dev
, "ranges", &rlen
);
986 hose
->io_base_phys
= 0;
987 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
989 pci_space
= ranges
[0];
990 pci_addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
992 cpu_phys_addr
= ranges
[3];
994 cpu_phys_addr
= (cpu_phys_addr
<< 32) | ranges
[4];
996 size
= ((unsigned long)ranges
[na
+3] << 32) | ranges
[na
+4];
1001 /* Now consume following elements while they are contiguous */
1002 while (rlen
>= np
* sizeof(unsigned int)) {
1003 unsigned long addr
, phys
;
1005 if (ranges
[0] != pci_space
)
1007 addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1010 phys
= (phys
<< 32) | ranges
[4];
1011 if (addr
!= pci_addr
+ size
||
1012 phys
!= cpu_phys_addr
+ size
)
1015 size
+= ((unsigned long)ranges
[na
+3] << 32)
1018 rlen
-= np
* sizeof(unsigned int);
1021 switch ((pci_space
>> 24) & 0x3) {
1022 case 1: /* I/O space */
1023 hose
->io_base_phys
= cpu_phys_addr
;
1024 hose
->pci_io_size
= size
;
1026 res
= &hose
->io_resource
;
1027 res
->flags
= IORESOURCE_IO
;
1028 res
->start
= pci_addr
;
1029 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
1030 res
->start
, res
->start
+ size
- 1);
1032 case 2: /* memory space */
1034 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
1038 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
1040 res
= &hose
->mem_resources
[memno
];
1041 res
->flags
= IORESOURCE_MEM
;
1042 res
->start
= cpu_phys_addr
;
1043 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
1044 res
->start
, res
->start
+ size
- 1);
1049 res
->name
= dev
->full_name
;
1050 res
->end
= res
->start
+ size
- 1;
1052 res
->sibling
= NULL
;
1058 void __init
pci_setup_phb_io(struct pci_controller
*hose
, int primary
)
1060 unsigned long size
= hose
->pci_io_size
;
1061 unsigned long io_virt_offset
;
1062 struct resource
*res
;
1063 struct device_node
*isa_dn
;
1065 hose
->io_base_virt
= reserve_phb_iospace(size
);
1066 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1067 hose
->global_number
, hose
->io_base_phys
,
1068 (unsigned long) hose
->io_base_virt
);
1071 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1072 isa_dn
= of_find_node_by_type(NULL
, "isa");
1074 isa_io_base
= pci_io_base
;
1075 pci_process_ISA_OF_ranges(isa_dn
, hose
->io_base_phys
,
1076 hose
->io_base_virt
);
1077 of_node_put(isa_dn
);
1083 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1084 res
= &hose
->io_resource
;
1085 res
->start
+= io_virt_offset
;
1086 res
->end
+= io_virt_offset
;
1089 void __devinit
pci_setup_phb_io_dynamic(struct pci_controller
*hose
,
1092 unsigned long size
= hose
->pci_io_size
;
1093 unsigned long io_virt_offset
;
1094 struct resource
*res
;
1096 hose
->io_base_virt
= __ioremap(hose
->io_base_phys
, size
,
1097 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
1098 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1099 hose
->global_number
, hose
->io_base_phys
,
1100 (unsigned long) hose
->io_base_virt
);
1103 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1105 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1106 res
= &hose
->io_resource
;
1107 res
->start
+= io_virt_offset
;
1108 res
->end
+= io_virt_offset
;
1112 static int get_bus_io_range(struct pci_bus
*bus
, unsigned long *start_phys
,
1113 unsigned long *start_virt
, unsigned long *size
)
1115 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1116 struct pci_bus_region region
;
1117 struct resource
*res
;
1120 res
= bus
->resource
[0];
1121 pcibios_resource_to_bus(bus
->self
, ®ion
, res
);
1122 *start_phys
= hose
->io_base_phys
+ region
.start
;
1123 *start_virt
= (unsigned long) hose
->io_base_virt
+
1125 if (region
.end
> region
.start
)
1126 *size
= region
.end
- region
.start
+ 1;
1128 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1129 __FUNCTION__
, region
.start
, region
.end
);
1135 res
= &hose
->io_resource
;
1136 *start_phys
= hose
->io_base_phys
;
1137 *start_virt
= (unsigned long) hose
->io_base_virt
;
1138 if (res
->end
> res
->start
)
1139 *size
= res
->end
- res
->start
+ 1;
1141 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1142 __FUNCTION__
, res
->start
, res
->end
);
1150 int unmap_bus_range(struct pci_bus
*bus
)
1152 unsigned long start_phys
;
1153 unsigned long start_virt
;
1157 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1161 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1163 if (iounmap_explicit((void __iomem
*) start_virt
, size
))
1168 EXPORT_SYMBOL(unmap_bus_range
);
1170 int remap_bus_range(struct pci_bus
*bus
)
1172 unsigned long start_phys
;
1173 unsigned long start_virt
;
1177 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1182 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1184 if (start_phys
== 0)
1186 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys
, start_virt
, size
);
1187 if (__ioremap_explicit(start_phys
, start_virt
, size
,
1188 _PAGE_NO_CACHE
| _PAGE_GUARDED
))
1193 EXPORT_SYMBOL(remap_bus_range
);
1195 void phbs_remap_io(void)
1197 struct pci_controller
*hose
, *tmp
;
1199 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1200 remap_bus_range(hose
->bus
);
1203 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
1205 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1206 unsigned long start
, end
, mask
, offset
;
1208 if (res
->flags
& IORESOURCE_IO
) {
1209 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1211 start
= res
->start
+= offset
;
1212 end
= res
->end
+= offset
;
1214 /* Need to allow IO access to pages that are in the
1216 if (start
< MAX_ISA_PORT
) {
1217 if (end
> MAX_ISA_PORT
)
1220 start
>>= PAGE_SHIFT
;
1223 /* get the range of pages for the map */
1224 mask
= ((1 << (end
+1)) - 1) ^ ((1 << start
) - 1);
1225 io_page_mask
|= mask
;
1227 } else if (res
->flags
& IORESOURCE_MEM
) {
1228 res
->start
+= hose
->pci_mem_offset
;
1229 res
->end
+= hose
->pci_mem_offset
;
1233 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
1234 struct pci_bus
*bus
)
1236 /* Update device resources. */
1239 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1240 if (dev
->resource
[i
].flags
)
1241 fixup_resource(&dev
->resource
[i
], dev
);
1243 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
1246 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
1248 struct pci_dev
*dev
;
1250 ppc_md
.iommu_bus_setup(bus
);
1252 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1253 ppc_md
.iommu_dev_setup(dev
);
1255 if (ppc_md
.irq_bus_setup
)
1256 ppc_md
.irq_bus_setup(bus
);
1259 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1261 struct pci_dev
*dev
= bus
->self
;
1263 if (dev
&& pci_probe_only
&&
1264 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1265 /* This is a subordinate bridge */
1267 pci_read_bridge_bases(bus
);
1268 pcibios_fixup_device_resources(dev
, bus
);
1273 if (!pci_probe_only
)
1276 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1277 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1278 pcibios_fixup_device_resources(dev
, bus
);
1280 EXPORT_SYMBOL(pcibios_fixup_bus
);
1283 * Reads the interrupt pin to determine if interrupt is use by card.
1284 * If the interrupt is used, then gets the interrupt line from the
1285 * openfirmware and sets it in the pci_dev and pci_config line.
1287 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1290 struct device_node
*node
;
1292 pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &intpin
);
1296 node
= pci_device_to_OF_node(pci_dev
);
1300 if (node
->n_intrs
== 0)
1303 pci_dev
->irq
= node
->intrs
[0].line
;
1305 pci_write_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, pci_dev
->irq
);
1309 EXPORT_SYMBOL(pci_read_irq_line
);
1311 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1312 const struct resource
*rsrc
,
1313 u64
*start
, u64
*end
)
1315 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1316 unsigned long offset
= 0;
1321 if (rsrc
->flags
& IORESOURCE_IO
)
1322 offset
= pci_io_base
- (unsigned long)hose
->io_base_virt
+
1325 *start
= rsrc
->start
+ offset
;
1326 *end
= rsrc
->end
+ offset
;
1329 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
1334 struct pci_controller
*hose
, *tmp
;
1335 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1336 if (hose
->arch_data
== node
)
1338 node
= node
->parent
;
1343 #endif /* CONFIG_PPC_MULTIPLATFORM */
1345 unsigned int pci_address_to_pio(phys_addr_t address
)
1347 struct pci_controller
*hose
, *tmp
;
1349 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1350 if (address
>= hose
->io_base_phys
&&
1351 address
< (hose
->io_base_phys
+ hose
->pci_io_size
))
1352 return (unsigned int)
1353 ((unsigned long)hose
->io_base_virt
+
1354 (address
- hose
->io_base_phys
));
1356 return (unsigned int)-1;
1358 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
1361 #define IOBASE_BRIDGE_NUMBER 0
1362 #define IOBASE_MEMORY 1
1364 #define IOBASE_ISA_IO 3
1365 #define IOBASE_ISA_MEM 4
1367 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
1368 unsigned long in_devfn
)
1370 struct pci_controller
* hose
;
1371 struct list_head
*ln
;
1372 struct pci_bus
*bus
= NULL
;
1373 struct device_node
*hose_node
;
1375 /* Argh ! Please forgive me for that hack, but that's the
1376 * simplest way to get existing XFree to not lockup on some
1377 * G5 machines... So when something asks for bus 0 io base
1378 * (bus 0 is HT root), we return the AGP one instead.
1380 if (machine_is_compatible("MacRISC4"))
1384 /* That syscall isn't quite compatible with PCI domains, but it's
1385 * used on pre-domains setup. We return the first match
1388 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
1389 bus
= pci_bus_b(ln
);
1390 if (in_bus
>= bus
->number
&& in_bus
< (bus
->number
+ bus
->subordinate
))
1394 if (bus
== NULL
|| bus
->sysdata
== NULL
)
1397 hose_node
= (struct device_node
*)bus
->sysdata
;
1398 hose
= PCI_DN(hose_node
)->phb
;
1401 case IOBASE_BRIDGE_NUMBER
:
1402 return (long)hose
->first_busno
;
1404 return (long)hose
->pci_mem_offset
;
1406 return (long)hose
->io_base_phys
;
1408 return (long)isa_io_base
;
1409 case IOBASE_ISA_MEM
: