2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only
= 1;
43 int pci_assign_all_buses
= 0;
45 #ifdef CONFIG_PPC_MULTIPLATFORM
46 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
47 static void do_bus_setup(struct pci_bus
*bus
);
48 static void phbs_remap_io(void);
51 /* pci_io_base -- the base address from which io bars are offsets.
52 * This is the lowest I/O base address (so bar values are always positive),
53 * and it *must* be the start of ISA space if an ISA bus exists because
54 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
55 * page is mapped and isa_io_limit prevents access to it.
57 unsigned long isa_io_base
; /* NULL if no ISA bus */
58 EXPORT_SYMBOL(isa_io_base
);
59 unsigned long pci_io_base
;
60 EXPORT_SYMBOL(pci_io_base
);
62 void iSeries_pcibios_init(void);
66 struct dma_mapping_ops pci_dma_ops
;
67 EXPORT_SYMBOL(pci_dma_ops
);
69 int global_phb_number
; /* Global phb counter */
71 /* Cached ISA bridge dev. */
72 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
73 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev
);
75 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
77 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
78 dev
->vendor
= PCI_VENDOR_ID_AMD
;
79 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
82 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
84 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
87 unsigned long offset
= 0;
88 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
93 if (res
->flags
& IORESOURCE_IO
)
94 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
96 if (res
->flags
& IORESOURCE_MEM
)
97 offset
= hose
->pci_mem_offset
;
99 region
->start
= res
->start
- offset
;
100 region
->end
= res
->end
- offset
;
103 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
104 struct pci_bus_region
*region
)
106 unsigned long offset
= 0;
107 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
112 if (res
->flags
& IORESOURCE_IO
)
113 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
115 if (res
->flags
& IORESOURCE_MEM
)
116 offset
= hose
->pci_mem_offset
;
118 res
->start
= region
->start
+ offset
;
119 res
->end
= region
->end
+ offset
;
122 #ifdef CONFIG_HOTPLUG
123 EXPORT_SYMBOL(pcibios_resource_to_bus
);
124 EXPORT_SYMBOL(pcibios_bus_to_resource
);
128 * We need to avoid collisions with `mirrored' VGA ports
129 * and other strange ISA hardware, so we always want the
130 * addresses to be allocated in the 0x000-0x0ff region
133 * Why? Because some silly external IO cards only decode
134 * the low 10 bits of the IO address. The 0x00-0xff region
135 * is reserved for motherboard devices that decode all 16
136 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
137 * but we want to try to avoid allocating at 0x2900-0x2bff
138 * which might have be mirrored at 0x0100-0x03ff..
140 void pcibios_align_resource(void *data
, struct resource
*res
,
141 unsigned long size
, unsigned long align
)
143 struct pci_dev
*dev
= data
;
144 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
145 unsigned long start
= res
->start
;
146 unsigned long alignto
;
148 if (res
->flags
& IORESOURCE_IO
) {
149 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
151 /* Make sure we start at our min on all hoses */
152 if (start
- offset
< PCIBIOS_MIN_IO
)
153 start
= PCIBIOS_MIN_IO
+ offset
;
156 * Put everything into 0x00-0xff region modulo 0x400
159 start
= (start
+ 0x3ff) & ~0x3ff;
161 } else if (res
->flags
& IORESOURCE_MEM
) {
162 /* Make sure we start at our min on all hoses */
163 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
164 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
166 /* Align to multiple of size of minimum base. */
167 alignto
= max(0x1000UL
, align
);
168 start
= ALIGN(start
, alignto
);
174 static DEFINE_SPINLOCK(hose_spinlock
);
177 * pci_controller(phb) initialized common variables.
179 static void __devinit
pci_setup_pci_controller(struct pci_controller
*hose
)
181 memset(hose
, 0, sizeof(struct pci_controller
));
183 spin_lock(&hose_spinlock
);
184 hose
->global_number
= global_phb_number
++;
185 list_add_tail(&hose
->list_node
, &hose_list
);
186 spin_unlock(&hose_spinlock
);
189 static void add_linux_pci_domain(struct device_node
*dev
,
190 struct pci_controller
*phb
)
192 struct property
*of_prop
;
195 of_prop
= (struct property
*)
196 get_property(dev
, "linux,pci-domain", &size
);
199 WARN_ON(of_prop
&& size
< sizeof(int));
200 if (of_prop
&& size
< sizeof(int))
202 size
= sizeof(struct property
) + sizeof(int);
203 if (of_prop
== NULL
) {
205 of_prop
= kmalloc(size
, GFP_KERNEL
);
207 of_prop
= alloc_bootmem(size
);
209 memset(of_prop
, 0, sizeof(struct property
));
210 of_prop
->name
= "linux,pci-domain";
211 of_prop
->length
= sizeof(int);
212 of_prop
->value
= (unsigned char *)&of_prop
[1];
213 *((int *)of_prop
->value
) = phb
->global_number
;
214 prom_add_property(dev
, of_prop
);
217 struct pci_controller
* pcibios_alloc_controller(struct device_node
*dev
)
219 struct pci_controller
*phb
;
222 phb
= kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
224 phb
= alloc_bootmem(sizeof (struct pci_controller
));
227 pci_setup_pci_controller(phb
);
228 phb
->arch_data
= dev
;
229 phb
->is_dynamic
= mem_init_done
;
231 PHB_SET_NODE(phb
, of_node_to_nid(dev
));
232 add_linux_pci_domain(dev
, phb
);
237 void pcibios_free_controller(struct pci_controller
*phb
)
239 if (phb
->arch_data
) {
240 struct device_node
*np
= phb
->arch_data
;
241 int *domain
= (int *)get_property(np
,
242 "linux,pci-domain", NULL
);
250 #ifndef CONFIG_PPC_ISERIES
251 void __devinit
pcibios_claim_one_bus(struct pci_bus
*b
)
254 struct pci_bus
*child_bus
;
256 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
259 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
260 struct resource
*r
= &dev
->resource
[i
];
262 if (r
->parent
|| !r
->start
|| !r
->flags
)
264 pci_claim_resource(dev
, i
);
268 list_for_each_entry(child_bus
, &b
->children
, node
)
269 pcibios_claim_one_bus(child_bus
);
271 #ifdef CONFIG_HOTPLUG
272 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
275 static void __init
pcibios_claim_of_setup(void)
279 list_for_each_entry(b
, &pci_root_buses
, node
)
280 pcibios_claim_one_bus(b
);
284 #ifdef CONFIG_PPC_MULTIPLATFORM
285 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
290 prop
= (u32
*) get_property(np
, name
, &len
);
291 if (prop
&& len
>= 4)
296 static unsigned int pci_parse_of_flags(u32 addr0
)
298 unsigned int flags
= 0;
300 if (addr0
& 0x02000000) {
301 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
302 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
303 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
304 if (addr0
& 0x40000000)
305 flags
|= IORESOURCE_PREFETCH
306 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
307 } else if (addr0
& 0x01000000)
308 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
312 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
314 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
318 struct resource
*res
;
322 addrs
= (u32
*) get_property(node
, "assigned-addresses", &proplen
);
325 DBG(" parse addresses (%d bytes) @ %p\n", proplen
, addrs
);
326 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
327 flags
= pci_parse_of_flags(addrs
[0]);
330 base
= GET_64BIT(addrs
, 1);
331 size
= GET_64BIT(addrs
, 3);
335 DBG(" base: %llx, size: %llx, i: %x\n",
336 (unsigned long long)base
, (unsigned long long)size
, i
);
338 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
339 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
340 } else if (i
== dev
->rom_base_reg
) {
341 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
342 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
344 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
348 res
->end
= base
+ size
- 1;
350 res
->name
= pci_name(dev
);
351 fixup_resource(res
, dev
);
355 struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
356 struct pci_bus
*bus
, int devfn
)
361 dev
= kmalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
364 type
= get_property(node
, "device_type", NULL
);
368 DBG(" create device, devfn: %x, type: %s\n", devfn
, type
);
370 memset(dev
, 0, sizeof(struct pci_dev
));
373 dev
->dev
.parent
= bus
->bridge
;
374 dev
->dev
.bus
= &pci_bus_type
;
376 dev
->multifunction
= 0; /* maybe a lie? */
378 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
379 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
380 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
381 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
383 dev
->cfg_size
= pci_cfg_space_size(dev
);
385 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
386 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
387 dev
->class = get_int_prop(node
, "class-code", 0);
389 DBG(" class: 0x%x\n", dev
->class);
391 dev
->current_state
= 4; /* unknown power state */
393 if (!strcmp(type
, "pci") || !strcmp(type
, "pciex")) {
394 /* a PCI-PCI bridge */
395 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
396 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
397 } else if (!strcmp(type
, "cardbus")) {
398 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
400 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
401 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
403 if (node
->n_intrs
> 0) {
404 dev
->irq
= node
->intrs
[0].line
;
405 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
,
410 pci_parse_of_addrs(node
, dev
);
412 DBG(" adding to system ...\n");
414 pci_device_add(dev
, bus
);
416 /* XXX pci_scan_msi_device(dev); */
420 EXPORT_SYMBOL(of_create_pci_dev
);
422 void __devinit
of_scan_bus(struct device_node
*node
,
425 struct device_node
*child
= NULL
;
430 DBG("of_scan_bus(%s) bus no %d... \n", node
->full_name
, bus
->number
);
432 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
433 DBG(" * %s\n", child
->full_name
);
434 reg
= (u32
*) get_property(child
, "reg", ®len
);
435 if (reg
== NULL
|| reglen
< 20)
437 devfn
= (reg
[0] >> 8) & 0xff;
439 /* create a new pci_dev for this device */
440 dev
= of_create_pci_dev(child
, bus
, devfn
);
443 DBG("dev header type: %x\n", dev
->hdr_type
);
445 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
446 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
447 of_scan_pci_bridge(child
, dev
);
452 EXPORT_SYMBOL(of_scan_bus
);
454 void __devinit
of_scan_pci_bridge(struct device_node
*node
,
458 u32
*busrange
, *ranges
;
460 struct resource
*res
;
464 DBG("of_scan_pci_bridge(%s)\n", node
->full_name
);
466 /* parse bus-range property */
467 busrange
= (u32
*) get_property(node
, "bus-range", &len
);
468 if (busrange
== NULL
|| len
!= 8) {
469 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
473 ranges
= (u32
*) get_property(node
, "ranges", &len
);
474 if (ranges
== NULL
) {
475 printk(KERN_DEBUG
"Can't get ranges for PCI-PCI bridge %s\n",
480 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
482 printk(KERN_ERR
"Failed to create pci bus for %s\n",
487 bus
->primary
= dev
->bus
->number
;
488 bus
->subordinate
= busrange
[1];
492 /* parse ranges property */
493 /* PCI #address-cells == 3 and #size-cells == 2 always */
494 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
495 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
497 bus
->resource
[i
] = res
;
501 for (; len
>= 32; len
-= 32, ranges
+= 8) {
502 flags
= pci_parse_of_flags(ranges
[0]);
503 size
= GET_64BIT(ranges
, 6);
504 if (flags
== 0 || size
== 0)
506 if (flags
& IORESOURCE_IO
) {
507 res
= bus
->resource
[0];
509 printk(KERN_ERR
"PCI: ignoring extra I/O range"
510 " for bridge %s\n", node
->full_name
);
514 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
515 printk(KERN_ERR
"PCI: too many memory ranges"
516 " for bridge %s\n", node
->full_name
);
519 res
= bus
->resource
[i
];
522 res
->start
= GET_64BIT(ranges
, 1);
523 res
->end
= res
->start
+ size
- 1;
525 fixup_resource(res
, dev
);
527 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
529 DBG(" bus name: %s\n", bus
->name
);
531 mode
= PCI_PROBE_NORMAL
;
532 if (ppc_md
.pci_probe_mode
)
533 mode
= ppc_md
.pci_probe_mode(bus
);
534 DBG(" probe mode: %d\n", mode
);
536 if (mode
== PCI_PROBE_DEVTREE
)
537 of_scan_bus(node
, bus
);
538 else if (mode
== PCI_PROBE_NORMAL
)
539 pci_scan_child_bus(bus
);
541 EXPORT_SYMBOL(of_scan_pci_bridge
);
542 #endif /* CONFIG_PPC_MULTIPLATFORM */
544 void __devinit
scan_phb(struct pci_controller
*hose
)
547 struct device_node
*node
= hose
->arch_data
;
549 struct resource
*res
;
551 DBG("Scanning PHB %s\n", node
? node
->full_name
: "<NO NAME>");
553 bus
= pci_create_bus(NULL
, hose
->first_busno
, hose
->ops
, node
);
555 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
556 hose
->global_number
);
559 bus
->secondary
= hose
->first_busno
;
562 bus
->resource
[0] = res
= &hose
->io_resource
;
563 if (res
->flags
&& request_resource(&ioport_resource
, res
))
564 printk(KERN_ERR
"Failed to request PCI IO region "
565 "on PCI domain %04x\n", hose
->global_number
);
567 for (i
= 0; i
< 3; ++i
) {
568 res
= &hose
->mem_resources
[i
];
569 bus
->resource
[i
+1] = res
;
570 if (res
->flags
&& request_resource(&iomem_resource
, res
))
571 printk(KERN_ERR
"Failed to request PCI memory region "
572 "on PCI domain %04x\n", hose
->global_number
);
575 mode
= PCI_PROBE_NORMAL
;
576 #ifdef CONFIG_PPC_MULTIPLATFORM
577 if (node
&& ppc_md
.pci_probe_mode
)
578 mode
= ppc_md
.pci_probe_mode(bus
);
579 DBG(" probe mode: %d\n", mode
);
580 if (mode
== PCI_PROBE_DEVTREE
) {
581 bus
->subordinate
= hose
->last_busno
;
582 of_scan_bus(node
, bus
);
584 #endif /* CONFIG_PPC_MULTIPLATFORM */
585 if (mode
== PCI_PROBE_NORMAL
)
586 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
589 static int __init
pcibios_init(void)
591 struct pci_controller
*hose
, *tmp
;
593 /* For now, override phys_mem_access_prot. If we need it,
594 * later, we may move that initialization to each ppc_md
596 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
598 #ifdef CONFIG_PPC_ISERIES
599 iSeries_pcibios_init();
602 printk(KERN_DEBUG
"PCI: Probing PCI hardware\n");
604 /* Scan all of the recorded PCI controllers. */
605 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
607 pci_bus_add_devices(hose
->bus
);
610 #ifndef CONFIG_PPC_ISERIES
612 pcibios_claim_of_setup();
614 /* FIXME: `else' will be removed when
615 pci_assign_unassigned_resources() is able to work
616 correctly with [partially] allocated PCI tree. */
617 pci_assign_unassigned_resources();
618 #endif /* !CONFIG_PPC_ISERIES */
620 /* Call machine dependent final fixup */
621 if (ppc_md
.pcibios_fixup
)
622 ppc_md
.pcibios_fixup();
624 /* Cache the location of the ISA bridge (if we have one) */
625 ppc64_isabridge_dev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
626 if (ppc64_isabridge_dev
!= NULL
)
627 printk(KERN_DEBUG
"ISA bridge at %s\n", pci_name(ppc64_isabridge_dev
));
629 #ifdef CONFIG_PPC_MULTIPLATFORM
630 /* map in PCI I/O space */
634 printk(KERN_DEBUG
"PCI: Probing PCI hardware done\n");
639 subsys_initcall(pcibios_init
);
641 char __init
*pcibios_setup(char *str
)
646 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
651 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
654 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
655 struct resource
*res
= &dev
->resource
[i
];
657 /* Only set up the requested stuff */
658 if (!(mask
& (1<<i
)))
661 if (res
->flags
& IORESOURCE_IO
)
662 cmd
|= PCI_COMMAND_IO
;
663 if (res
->flags
& IORESOURCE_MEM
)
664 cmd
|= PCI_COMMAND_MEMORY
;
668 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
670 /* Enable the appropriate bits in the PCI command register. */
671 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
677 * Return the domain number for this bus.
679 int pci_domain_nr(struct pci_bus
*bus
)
681 #ifdef CONFIG_PPC_ISERIES
684 struct pci_controller
*hose
= pci_bus_to_host(bus
);
686 return hose
->global_number
;
690 EXPORT_SYMBOL(pci_domain_nr
);
692 /* Decide whether to display the domain number in /proc */
693 int pci_proc_domain(struct pci_bus
*bus
)
695 #ifdef CONFIG_PPC_ISERIES
698 struct pci_controller
*hose
= pci_bus_to_host(bus
);
704 * Platform support for /proc/bus/pci/X/Y mmap()s,
705 * modelled on the sparc64 implementation by Dave Miller.
710 * Adjust vm_pgoff of VMA such that it is the physical page offset
711 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
713 * Basically, the user finds the base address for his device which he wishes
714 * to mmap. They read the 32-bit value from the config space base register,
715 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
716 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
718 * Returns negative error code on failure, zero on success.
720 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
721 unsigned long *offset
,
722 enum pci_mmap_state mmap_state
)
724 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
725 unsigned long io_offset
= 0;
729 return NULL
; /* should never happen */
731 /* If memory, add on the PCI bridge address offset */
732 if (mmap_state
== pci_mmap_mem
) {
733 *offset
+= hose
->pci_mem_offset
;
734 res_bit
= IORESOURCE_MEM
;
736 io_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
737 *offset
+= io_offset
;
738 res_bit
= IORESOURCE_IO
;
742 * Check that the offset requested corresponds to one of the
743 * resources of the device.
745 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
746 struct resource
*rp
= &dev
->resource
[i
];
747 int flags
= rp
->flags
;
749 /* treat ROM as memory (should be already) */
750 if (i
== PCI_ROM_RESOURCE
)
751 flags
|= IORESOURCE_MEM
;
753 /* Active and same type? */
754 if ((flags
& res_bit
) == 0)
757 /* In the range of this resource? */
758 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
761 /* found it! construct the final physical address */
762 if (mmap_state
== pci_mmap_io
)
763 *offset
+= hose
->io_base_phys
- io_offset
;
771 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
774 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
776 enum pci_mmap_state mmap_state
,
779 unsigned long prot
= pgprot_val(protection
);
781 /* Write combine is always 0 on non-memory space mappings. On
782 * memory space, if the user didn't pass 1, we check for a
783 * "prefetchable" resource. This is a bit hackish, but we use
784 * this to workaround the inability of /sysfs to provide a write
787 if (mmap_state
!= pci_mmap_mem
)
789 else if (write_combine
== 0) {
790 if (rp
->flags
& IORESOURCE_PREFETCH
)
794 /* XXX would be nice to have a way to ask for write-through */
795 prot
|= _PAGE_NO_CACHE
;
797 prot
&= ~_PAGE_GUARDED
;
799 prot
|= _PAGE_GUARDED
;
801 printk(KERN_DEBUG
"PCI map for %s:%lx, prot: %lx\n", pci_name(dev
), rp
->start
,
804 return __pgprot(prot
);
808 * This one is used by /dev/mem and fbdev who have no clue about the
809 * PCI device, it tries to find the PCI device first and calls the
812 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
817 struct pci_dev
*pdev
= NULL
;
818 struct resource
*found
= NULL
;
819 unsigned long prot
= pgprot_val(protection
);
820 unsigned long offset
= pfn
<< PAGE_SHIFT
;
823 if (page_is_ram(pfn
))
824 return __pgprot(prot
);
826 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
828 for_each_pci_dev(pdev
) {
829 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
830 struct resource
*rp
= &pdev
->resource
[i
];
831 int flags
= rp
->flags
;
833 /* Active and same type? */
834 if ((flags
& IORESOURCE_MEM
) == 0)
836 /* In the range of this resource? */
837 if (offset
< (rp
->start
& PAGE_MASK
) ||
847 if (found
->flags
& IORESOURCE_PREFETCH
)
848 prot
&= ~_PAGE_GUARDED
;
852 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
854 return __pgprot(prot
);
859 * Perform the actual remap of the pages for a PCI device mapping, as
860 * appropriate for this architecture. The region in the process to map
861 * is described by vm_start and vm_end members of VMA, the base physical
862 * address is found in vm_pgoff.
863 * The pci device structure is provided so that architectures may make mapping
864 * decisions on a per-device or per-bus basis.
866 * Returns a negative error code on failure, zero on success.
868 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
869 enum pci_mmap_state mmap_state
, int write_combine
)
871 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
875 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
879 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
880 vma
->vm_flags
|= VM_SHM
| VM_LOCKED
| VM_IO
;
881 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
883 mmap_state
, write_combine
);
885 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
886 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
891 static ssize_t
pci_show_devspec(struct device
*dev
,
892 struct device_attribute
*attr
, char *buf
)
894 struct pci_dev
*pdev
;
895 struct device_node
*np
;
897 pdev
= to_pci_dev (dev
);
898 np
= pci_device_to_OF_node(pdev
);
899 if (np
== NULL
|| np
->full_name
== NULL
)
901 return sprintf(buf
, "%s", np
->full_name
);
903 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
905 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
907 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
910 #ifdef CONFIG_PPC_MULTIPLATFORM
912 #define ISA_SPACE_MASK 0x1
913 #define ISA_SPACE_IO 0x1
915 static void __devinit
pci_process_ISA_OF_ranges(struct device_node
*isa_node
,
916 unsigned long phb_io_base_phys
,
917 void __iomem
* phb_io_base_virt
)
919 /* Remove these asap */
933 struct isa_address isa_addr
;
934 struct pci_address pci_addr
;
938 struct isa_range
*range
;
939 unsigned long pci_addr
;
940 unsigned int isa_addr
;
944 range
= (struct isa_range
*) get_property(isa_node
, "ranges", &rlen
);
945 if (range
== NULL
|| (rlen
< sizeof(struct isa_range
))) {
946 printk(KERN_ERR
"no ISA ranges or unexpected isa range size,"
948 __ioremap_explicit(phb_io_base_phys
,
949 (unsigned long)phb_io_base_virt
,
950 0x10000, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
954 /* From "ISA Binding to 1275"
955 * The ranges property is laid out as an array of elements,
956 * each of which comprises:
957 * cells 0 - 1: an ISA address
958 * cells 2 - 4: a PCI address
959 * (size depending on dev->n_addr_cells)
960 * cell 5: the size of the range
962 if ((range
->isa_addr
.a_hi
&& ISA_SPACE_MASK
) == ISA_SPACE_IO
) {
963 isa_addr
= range
->isa_addr
.a_lo
;
964 pci_addr
= (unsigned long) range
->pci_addr
.a_mid
<< 32 |
965 range
->pci_addr
.a_lo
;
967 /* Assume these are both zero */
968 if ((pci_addr
!= 0) || (isa_addr
!= 0)) {
969 printk(KERN_ERR
"unexpected isa to pci mapping: %s\n",
974 size
= PAGE_ALIGN(range
->size
);
976 __ioremap_explicit(phb_io_base_phys
,
977 (unsigned long) phb_io_base_virt
,
978 size
, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
982 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
983 struct device_node
*dev
, int prim
)
985 unsigned int *ranges
, pci_space
;
989 struct resource
*res
;
990 int np
, na
= prom_n_addr_cells(dev
);
991 unsigned long pci_addr
, cpu_phys_addr
;
995 /* From "PCI Binding to 1275"
996 * The ranges property is laid out as an array of elements,
997 * each of which comprises:
998 * cells 0 - 2: a PCI address
999 * cells 3 or 3+4: a CPU physical address
1000 * (size depending on dev->n_addr_cells)
1001 * cells 4+5 or 5+6: the size of the range
1003 ranges
= (unsigned int *) get_property(dev
, "ranges", &rlen
);
1006 hose
->io_base_phys
= 0;
1007 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
1009 pci_space
= ranges
[0];
1010 pci_addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1012 cpu_phys_addr
= ranges
[3];
1014 cpu_phys_addr
= (cpu_phys_addr
<< 32) | ranges
[4];
1016 size
= ((unsigned long)ranges
[na
+3] << 32) | ranges
[na
+4];
1021 /* Now consume following elements while they are contiguous */
1022 while (rlen
>= np
* sizeof(unsigned int)) {
1023 unsigned long addr
, phys
;
1025 if (ranges
[0] != pci_space
)
1027 addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1030 phys
= (phys
<< 32) | ranges
[4];
1031 if (addr
!= pci_addr
+ size
||
1032 phys
!= cpu_phys_addr
+ size
)
1035 size
+= ((unsigned long)ranges
[na
+3] << 32)
1038 rlen
-= np
* sizeof(unsigned int);
1041 switch ((pci_space
>> 24) & 0x3) {
1042 case 1: /* I/O space */
1043 hose
->io_base_phys
= cpu_phys_addr
;
1044 hose
->pci_io_size
= size
;
1046 res
= &hose
->io_resource
;
1047 res
->flags
= IORESOURCE_IO
;
1048 res
->start
= pci_addr
;
1049 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
1050 res
->start
, res
->start
+ size
- 1);
1052 case 2: /* memory space */
1054 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
1058 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
1060 res
= &hose
->mem_resources
[memno
];
1061 res
->flags
= IORESOURCE_MEM
;
1062 res
->start
= cpu_phys_addr
;
1063 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
1064 res
->start
, res
->start
+ size
- 1);
1069 res
->name
= dev
->full_name
;
1070 res
->end
= res
->start
+ size
- 1;
1072 res
->sibling
= NULL
;
1078 void __init
pci_setup_phb_io(struct pci_controller
*hose
, int primary
)
1080 unsigned long size
= hose
->pci_io_size
;
1081 unsigned long io_virt_offset
;
1082 struct resource
*res
;
1083 struct device_node
*isa_dn
;
1085 hose
->io_base_virt
= reserve_phb_iospace(size
);
1086 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1087 hose
->global_number
, hose
->io_base_phys
,
1088 (unsigned long) hose
->io_base_virt
);
1091 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1092 isa_dn
= of_find_node_by_type(NULL
, "isa");
1094 isa_io_base
= pci_io_base
;
1095 pci_process_ISA_OF_ranges(isa_dn
, hose
->io_base_phys
,
1096 hose
->io_base_virt
);
1097 of_node_put(isa_dn
);
1101 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1102 res
= &hose
->io_resource
;
1103 res
->start
+= io_virt_offset
;
1104 res
->end
+= io_virt_offset
;
1107 void __devinit
pci_setup_phb_io_dynamic(struct pci_controller
*hose
,
1110 unsigned long size
= hose
->pci_io_size
;
1111 unsigned long io_virt_offset
;
1112 struct resource
*res
;
1114 hose
->io_base_virt
= __ioremap(hose
->io_base_phys
, size
,
1115 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
1116 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1117 hose
->global_number
, hose
->io_base_phys
,
1118 (unsigned long) hose
->io_base_virt
);
1121 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1123 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1124 res
= &hose
->io_resource
;
1125 res
->start
+= io_virt_offset
;
1126 res
->end
+= io_virt_offset
;
1130 static int get_bus_io_range(struct pci_bus
*bus
, unsigned long *start_phys
,
1131 unsigned long *start_virt
, unsigned long *size
)
1133 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1134 struct pci_bus_region region
;
1135 struct resource
*res
;
1138 res
= bus
->resource
[0];
1139 pcibios_resource_to_bus(bus
->self
, ®ion
, res
);
1140 *start_phys
= hose
->io_base_phys
+ region
.start
;
1141 *start_virt
= (unsigned long) hose
->io_base_virt
+
1143 if (region
.end
> region
.start
)
1144 *size
= region
.end
- region
.start
+ 1;
1146 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1147 __FUNCTION__
, region
.start
, region
.end
);
1153 res
= &hose
->io_resource
;
1154 *start_phys
= hose
->io_base_phys
;
1155 *start_virt
= (unsigned long) hose
->io_base_virt
;
1156 if (res
->end
> res
->start
)
1157 *size
= res
->end
- res
->start
+ 1;
1159 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1160 __FUNCTION__
, res
->start
, res
->end
);
1168 int unmap_bus_range(struct pci_bus
*bus
)
1170 unsigned long start_phys
;
1171 unsigned long start_virt
;
1175 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1179 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1181 if (iounmap_explicit((void __iomem
*) start_virt
, size
))
1186 EXPORT_SYMBOL(unmap_bus_range
);
1188 int remap_bus_range(struct pci_bus
*bus
)
1190 unsigned long start_phys
;
1191 unsigned long start_virt
;
1195 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1200 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1202 if (start_phys
== 0)
1204 printk(KERN_DEBUG
"mapping IO %lx -> %lx, size: %lx\n", start_phys
, start_virt
, size
);
1205 if (__ioremap_explicit(start_phys
, start_virt
, size
,
1206 _PAGE_NO_CACHE
| _PAGE_GUARDED
))
1211 EXPORT_SYMBOL(remap_bus_range
);
1213 static void phbs_remap_io(void)
1215 struct pci_controller
*hose
, *tmp
;
1217 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1218 remap_bus_range(hose
->bus
);
1221 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
1223 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1224 unsigned long offset
;
1226 if (res
->flags
& IORESOURCE_IO
) {
1227 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1229 res
->start
+= offset
;
1231 } else if (res
->flags
& IORESOURCE_MEM
) {
1232 res
->start
+= hose
->pci_mem_offset
;
1233 res
->end
+= hose
->pci_mem_offset
;
1237 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
1238 struct pci_bus
*bus
)
1240 /* Update device resources. */
1243 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1244 if (dev
->resource
[i
].flags
)
1245 fixup_resource(&dev
->resource
[i
], dev
);
1247 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
1250 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
1252 struct pci_dev
*dev
;
1254 ppc_md
.iommu_bus_setup(bus
);
1256 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1257 ppc_md
.iommu_dev_setup(dev
);
1259 if (ppc_md
.irq_bus_setup
)
1260 ppc_md
.irq_bus_setup(bus
);
1263 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1265 struct pci_dev
*dev
= bus
->self
;
1267 if (dev
&& pci_probe_only
&&
1268 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1269 /* This is a subordinate bridge */
1271 pci_read_bridge_bases(bus
);
1272 pcibios_fixup_device_resources(dev
, bus
);
1277 if (!pci_probe_only
)
1280 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1281 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1282 pcibios_fixup_device_resources(dev
, bus
);
1284 EXPORT_SYMBOL(pcibios_fixup_bus
);
1287 * Reads the interrupt pin to determine if interrupt is use by card.
1288 * If the interrupt is used, then gets the interrupt line from the
1289 * openfirmware and sets it in the pci_dev and pci_config line.
1291 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1294 struct device_node
*node
;
1296 pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &intpin
);
1300 node
= pci_device_to_OF_node(pci_dev
);
1304 if (node
->n_intrs
== 0)
1307 pci_dev
->irq
= node
->intrs
[0].line
;
1309 pci_write_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, pci_dev
->irq
);
1313 EXPORT_SYMBOL(pci_read_irq_line
);
1315 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1316 const struct resource
*rsrc
,
1317 u64
*start
, u64
*end
)
1319 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1320 unsigned long offset
= 0;
1325 if (rsrc
->flags
& IORESOURCE_IO
)
1326 offset
= pci_io_base
- (unsigned long)hose
->io_base_virt
+
1329 *start
= rsrc
->start
+ offset
;
1330 *end
= rsrc
->end
+ offset
;
1333 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
1338 struct pci_controller
*hose
, *tmp
;
1339 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1340 if (hose
->arch_data
== node
)
1342 node
= node
->parent
;
1347 #endif /* CONFIG_PPC_MULTIPLATFORM */
1349 unsigned long pci_address_to_pio(phys_addr_t address
)
1351 struct pci_controller
*hose
, *tmp
;
1353 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1354 if (address
>= hose
->io_base_phys
&&
1355 address
< (hose
->io_base_phys
+ hose
->pci_io_size
)) {
1356 unsigned long base
=
1357 (unsigned long)hose
->io_base_virt
- pci_io_base
;
1358 return base
+ (address
- hose
->io_base_phys
);
1361 return (unsigned int)-1;
1363 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
1366 #define IOBASE_BRIDGE_NUMBER 0
1367 #define IOBASE_MEMORY 1
1369 #define IOBASE_ISA_IO 3
1370 #define IOBASE_ISA_MEM 4
1372 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
1373 unsigned long in_devfn
)
1375 struct pci_controller
* hose
;
1376 struct list_head
*ln
;
1377 struct pci_bus
*bus
= NULL
;
1378 struct device_node
*hose_node
;
1380 /* Argh ! Please forgive me for that hack, but that's the
1381 * simplest way to get existing XFree to not lockup on some
1382 * G5 machines... So when something asks for bus 0 io base
1383 * (bus 0 is HT root), we return the AGP one instead.
1385 if (machine_is_compatible("MacRISC4"))
1389 /* That syscall isn't quite compatible with PCI domains, but it's
1390 * used on pre-domains setup. We return the first match
1393 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
1394 bus
= pci_bus_b(ln
);
1395 if (in_bus
>= bus
->number
&& in_bus
< (bus
->number
+ bus
->subordinate
))
1399 if (bus
== NULL
|| bus
->sysdata
== NULL
)
1402 hose_node
= (struct device_node
*)bus
->sysdata
;
1403 hose
= PCI_DN(hose_node
)->phb
;
1406 case IOBASE_BRIDGE_NUMBER
:
1407 return (long)hose
->first_busno
;
1409 return (long)hose
->pci_mem_offset
;
1411 return (long)hose
->io_base_phys
;
1413 return (long)isa_io_base
;
1414 case IOBASE_ISA_MEM
:
1422 int pcibus_to_node(struct pci_bus
*bus
)
1424 struct pci_controller
*phb
= pci_bus_to_host(bus
);
1427 EXPORT_SYMBOL(pcibus_to_node
);