arch/powerpc/kernel/pci_64.c

   1 /*
   2  * Port for PPC64 David Engebretsen, IBM Corp.
   3  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   4  *
   5  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   6  *   Rework, based on alpha PCI code.
   7  *
   8  *      This program is free software; you can redistribute it and/or
   9  *      modify it under the terms of the GNU General Public License
  10  *      as published by the Free Software Foundation; either version
  11  *      2 of the License, or (at your option) any later version.
  12  */
  13
  14 #undef DEBUG
  15
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/mm.h>
  22 #include <linux/list.h>
  23 #include <linux/syscalls.h>
  24 #include <linux/irq.h>
  25 #include <linux/vmalloc.h>
  26
  27 #include <asm/processor.h>
  28 #include <asm/io.h>
  29 #include <asm/prom.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/byteorder.h>
  32 #include <asm/machdep.h>
  33 #include <asm/ppc-pci.h>
  34
  35 #ifdef DEBUG
  36 #include <asm/udbg.h>
  37 #define DBG(fmt...) printk(fmt)
  38 #else
  39 #define DBG(fmt...)
  40 #endif
  41
  42 unsigned long pci_probe_only = 1;
  43
  44 /* pci_io_base -- the base address from which io bars are offsets.
  45  * This is the lowest I/O base address (so bar values are always positive),
  46  * and it *must* be the start of ISA space if an ISA bus exists because
  47  * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
  48  * is mapped on the first 64K of IO space
  49  */
  50 unsigned long pci_io_base = ISA_IO_BASE;
  51 EXPORT_SYMBOL(pci_io_base);
  52
  53 LIST_HEAD(hose_list);
  54
  55 static void fixup_broken_pcnet32(struct pci_dev* dev)
  56 {
  57         if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
  58                 dev->vendor = PCI_VENDOR_ID_AMD;
  59                 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
  60         }
  61 }
  62 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
  63
  64
  65 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
  66 {
  67         const u32 *prop;
  68         int len;
  69
  70         prop = of_get_property(np, name, &len);
  71         if (prop && len >= 4)
  72                 return *prop;
  73         return def;
  74 }
  75
  76 static unsigned int pci_parse_of_flags(u32 addr0)
  77 {
  78         unsigned int flags = 0;
  79
  80         if (addr0 & 0x02000000) {
  81                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
  82                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
  83                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
  84                 if (addr0 & 0x40000000)
  85                         flags |= IORESOURCE_PREFETCH
  86                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
  87         } else if (addr0 & 0x01000000)
  88                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
  89         return flags;
  90 }
  91
  92
  93 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
  94 {
  95         u64 base, size;
  96         unsigned int flags;
  97         struct resource *res;
  98         const u32 *addrs;
  99         u32 i;
 100         int proplen;
 101
 102         addrs = of_get_property(node, "assigned-addresses", &proplen);
 103         if (!addrs)
 104                 return;
 105         DBG("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
 106         for (; proplen >= 20; proplen -= 20, addrs += 5) {
 107                 flags = pci_parse_of_flags(addrs[0]);
 108                 if (!flags)
 109                         continue;
 110                 base = of_read_number(&addrs[1], 2);
 111                 size = of_read_number(&addrs[3], 2);
 112                 if (!size)
 113                         continue;
 114                 i = addrs[0] & 0xff;
 115                 DBG("  base: %llx, size: %llx, i: %x\n",
 116                     (unsigned long long)base, (unsigned long long)size, i);
 117
 118                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 119                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 120                 } else if (i == dev->rom_base_reg) {
 121                         res = &dev->resource[PCI_ROM_RESOURCE];
 122                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 123                 } else {
 124                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 125                         continue;
 126                 }
 127                 res->start = base;
 128                 res->end = base + size - 1;
 129                 res->flags = flags;
 130                 res->name = pci_name(dev);
 131         }
 132 }
 133
 134 struct pci_dev *of_create_pci_dev(struct device_node *node,
 135                                  struct pci_bus *bus, int devfn)
 136 {
 137         struct pci_dev *dev;
 138         const char *type;
 139
 140         dev = alloc_pci_dev();
 141         if (!dev)
 142                 return NULL;
 143         type = of_get_property(node, "device_type", NULL);
 144         if (type == NULL)
 145                 type = "";
 146
 147         DBG("    create device, devfn: %x, type: %s\n", devfn, type);
 148
 149         dev->bus = bus;
 150         dev->sysdata = node;
 151         dev->dev.parent = bus->bridge;
 152         dev->dev.bus = &pci_bus_type;
 153         dev->devfn = devfn;
 154         dev->multifunction = 0;         /* maybe a lie? */
 155
 156         dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
 157         dev->device = get_int_prop(node, "device-id", 0xffff);
 158         dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
 159         dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
 160
 161         dev->cfg_size = pci_cfg_space_size(dev);
 162
 163         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 164                 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 165         dev->class = get_int_prop(node, "class-code", 0);
 166         dev->revision = get_int_prop(node, "revision-id", 0);
 167
 168         DBG("    class: 0x%x\n", dev->class);
 169         DBG("    revision: 0x%x\n", dev->revision);
 170
 171         dev->current_state = 4;         /* unknown power state */
 172         dev->error_state = pci_channel_io_normal;
 173         dev->dma_mask = 0xffffffff;
 174
 175         if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
 176                 /* a PCI-PCI bridge */
 177                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 178                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 179         } else if (!strcmp(type, "cardbus")) {
 180                 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 181         } else {
 182                 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 183                 dev->rom_base_reg = PCI_ROM_ADDRESS;
 184                 /* Maybe do a default OF mapping here */
 185                 dev->irq = NO_IRQ;
 186         }
 187
 188         pci_parse_of_addrs(node, dev);
 189
 190         DBG("    adding to system ...\n");
 191
 192         pci_device_add(dev, bus);
 193
 194         return dev;
 195 }
 196 EXPORT_SYMBOL(of_create_pci_dev);
 197
 198 void __devinit of_scan_bus(struct device_node *node,
 199                            struct pci_bus *bus)
 200 {
 201         struct device_node *child;
 202         const u32 *reg;
 203         int reglen, devfn;
 204         struct pci_dev *dev;
 205
 206         DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
 207
 208         /* Scan direct children */
 209         for_each_child_of_node(node, child) {
 210                 DBG("  * %s\n", child->full_name);
 211                 reg = of_get_property(child, "reg", &reglen);
 212                 if (reg == NULL || reglen < 20)
 213                         continue;
 214                 devfn = (reg[0] >> 8) & 0xff;
 215
 216                 /* create a new pci_dev for this device */
 217                 dev = of_create_pci_dev(child, bus, devfn);
 218                 if (!dev)
 219                         continue;
 220                 DBG("    dev header type: %x\n", dev->hdr_type);
 221         }
 222
 223         /* Ally all fixups */
 224         pcibios_fixup_of_probed_bus(bus);
 225
 226         /* Now scan child busses */
 227         list_for_each_entry(dev, &bus->devices, bus_list) {
 228                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 229                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
 230                         struct device_node *child = pci_device_to_OF_node(dev);
 231                         if (dev)
 232                                 of_scan_pci_bridge(child, dev);
 233                 }
 234         }
 235 }
 236 EXPORT_SYMBOL(of_scan_bus);
 237
 238 void __devinit of_scan_pci_bridge(struct device_node *node,
 239                                   struct pci_dev *dev)
 240 {
 241         struct pci_bus *bus;
 242         const u32 *busrange, *ranges;
 243         int len, i, mode;
 244         struct resource *res;
 245         unsigned int flags;
 246         u64 size;
 247
 248         DBG("of_scan_pci_bridge(%s)\n", node->full_name);
 249
 250         /* parse bus-range property */
 251         busrange = of_get_property(node, "bus-range", &len);
 252         if (busrange == NULL || len != 8) {
 253                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 254                        node->full_name);
 255                 return;
 256         }
 257         ranges = of_get_property(node, "ranges", &len);
 258         if (ranges == NULL) {
 259                 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
 260                        node->full_name);
 261                 return;
 262         }
 263
 264         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 265         if (!bus) {
 266                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 267                        node->full_name);
 268                 return;
 269         }
 270
 271         bus->primary = dev->bus->number;
 272         bus->subordinate = busrange[1];
 273         bus->bridge_ctl = 0;
 274         bus->sysdata = node;
 275
 276         /* parse ranges property */
 277         /* PCI #address-cells == 3 and #size-cells == 2 always */
 278         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 279         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 280                 res->flags = 0;
 281                 bus->resource[i] = res;
 282                 ++res;
 283         }
 284         i = 1;
 285         for (; len >= 32; len -= 32, ranges += 8) {
 286                 flags = pci_parse_of_flags(ranges[0]);
 287                 size = of_read_number(&ranges[6], 2);
 288                 if (flags == 0 || size == 0)
 289                         continue;
 290                 if (flags & IORESOURCE_IO) {
 291                         res = bus->resource[0];
 292                         if (res->flags) {
 293                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 294                                        " for bridge %s\n", node->full_name);
 295                                 continue;
 296                         }
 297                 } else {
 298                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 299                                 printk(KERN_ERR "PCI: too many memory ranges"
 300                                        " for bridge %s\n", node->full_name);
 301                                 continue;
 302                         }
 303                         res = bus->resource[i];
 304                         ++i;
 305                 }
 306                 res->start = of_read_number(&ranges[1], 2);
 307                 res->end = res->start + size - 1;
 308                 res->flags = flags;
 309         }
 310         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 311                 bus->number);
 312         DBG("    bus name: %s\n", bus->name);
 313
 314         mode = PCI_PROBE_NORMAL;
 315         if (ppc_md.pci_probe_mode)
 316                 mode = ppc_md.pci_probe_mode(bus);
 317         DBG("    probe mode: %d\n", mode);
 318
 319         if (mode == PCI_PROBE_DEVTREE)
 320                 of_scan_bus(node, bus);
 321         else if (mode == PCI_PROBE_NORMAL)
 322                 pci_scan_child_bus(bus);
 323 }
 324 EXPORT_SYMBOL(of_scan_pci_bridge);
 325
 326 void __devinit scan_phb(struct pci_controller *hose)
 327 {
 328         struct pci_bus *bus;
 329         struct device_node *node = hose->dn;
 330         int i, mode;
 331
 332         DBG("PCI: Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
 333
 334         /* Create an empty bus for the toplevel */
 335         bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
 336         if (bus == NULL) {
 337                 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
 338                        hose->global_number);
 339                 return;
 340         }
 341         bus->secondary = hose->first_busno;
 342         hose->bus = bus;
 343
 344         /* Get some IO space for the new PHB */
 345         pcibios_map_io_space(bus);
 346
 347         /* Wire up PHB bus resources */
 348         DBG("PCI: PHB IO resource    = %016lx-%016lx [%lx]\n",
 349             hose->io_resource.start, hose->io_resource.end,
 350             hose->io_resource.flags);
 351         bus->resource[0] = &hose->io_resource;
 352         for (i = 0; i < 3; ++i) {
 353                 DBG("PCI: PHB MEM resource %d = %016lx-%016lx [%lx]\n", i,
 354                     hose->mem_resources[i].start,
 355                     hose->mem_resources[i].end,
 356                     hose->mem_resources[i].flags);
 357                 bus->resource[i+1] = &hose->mem_resources[i];
 358         }
 359         DBG("PCI: PHB MEM offset     = %016lx\n", hose->pci_mem_offset);
 360         DBG("PCI: PHB IO  offset     = %08lx\n",
 361             (unsigned long)hose->io_base_virt - _IO_BASE);
 362
 363         /* Get probe mode and perform scan */
 364         mode = PCI_PROBE_NORMAL;
 365         if (node && ppc_md.pci_probe_mode)
 366                 mode = ppc_md.pci_probe_mode(bus);
 367         DBG("    probe mode: %d\n", mode);
 368         if (mode == PCI_PROBE_DEVTREE) {
 369                 bus->subordinate = hose->last_busno;
 370                 of_scan_bus(node, bus);
 371         }
 372
 373         if (mode == PCI_PROBE_NORMAL)
 374                 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
 375 }
 376
 377 static int __init pcibios_init(void)
 378 {
 379         struct pci_controller *hose, *tmp;
 380
 381         printk(KERN_INFO "PCI: Probing PCI hardware\n");
 382
 383         /* For now, override phys_mem_access_prot. If we need it,
 384          * later, we may move that initialization to each ppc_md
 385          */
 386         ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
 387
 388         if (pci_probe_only)
 389                 ppc_pci_flags |= PPC_PCI_PROBE_ONLY;
 390
 391         /* On ppc64, we always enable PCI domains and we keep domain 0
 392          * backward compatible in /proc for video cards
 393          */
 394         ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
 395
 396         /* Scan all of the recorded PCI controllers.  */
 397         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 398                 scan_phb(hose);
 399                 pci_bus_add_devices(hose->bus);
 400         }
 401
 402         /* Call common code to handle resource allocation */
 403         pcibios_resource_survey();
 404
 405         printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
 406
 407         return 0;
 408 }
 409
 410 subsys_initcall(pcibios_init);
 411
 412 #ifdef CONFIG_HOTPLUG
 413
 414 int pcibios_unmap_io_space(struct pci_bus *bus)
 415 {
 416         struct pci_controller *hose;
 417
 418         WARN_ON(bus == NULL);
 419
 420         /* If this is not a PHB, we only flush the hash table over
 421          * the area mapped by this bridge. We don't play with the PTE
 422          * mappings since we might have to deal with sub-page alignemnts
 423          * so flushing the hash table is the only sane way to make sure
 424          * that no hash entries are covering that removed bridge area
 425          * while still allowing other busses overlapping those pages
 426          */
 427         if (bus->self) {
 428                 struct resource *res = bus->resource[0];
 429
 430                 DBG("IO unmapping for PCI-PCI bridge %s\n",
 431                     pci_name(bus->self));
 432
 433                 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
 434                                          res->end + _IO_BASE + 1);
 435                 return 0;
 436         }
 437
 438         /* Get the host bridge */
 439         hose = pci_bus_to_host(bus);
 440
 441         /* Check if we have IOs allocated */
 442         if (hose->io_base_alloc == 0)
 443                 return 0;
 444
 445         DBG("IO unmapping for PHB %s\n", hose->dn->full_name);
 446         DBG("  alloc=0x%p\n", hose->io_base_alloc);
 447
 448         /* This is a PHB, we fully unmap the IO area */
 449         vunmap(hose->io_base_alloc);
 450
 451         return 0;
 452 }
 453 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
 454
 455 #endif /* CONFIG_HOTPLUG */
 456
 457 int __devinit pcibios_map_io_space(struct pci_bus *bus)
 458 {
 459         struct vm_struct *area;
 460         unsigned long phys_page;
 461         unsigned long size_page;
 462         unsigned long io_virt_offset;
 463         struct pci_controller *hose;
 464
 465         WARN_ON(bus == NULL);
 466
 467         /* If this not a PHB, nothing to do, page tables still exist and
 468          * thus HPTEs will be faulted in when needed
 469          */
 470         if (bus->self) {
 471                 DBG("IO mapping for PCI-PCI bridge %s\n",
 472                     pci_name(bus->self));
 473                 DBG("  virt=0x%016lx...0x%016lx\n",
 474                     bus->resource[0]->start + _IO_BASE,
 475                     bus->resource[0]->end + _IO_BASE);
 476                 return 0;
 477         }
 478
 479         /* Get the host bridge */
 480         hose = pci_bus_to_host(bus);
 481         phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
 482         size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
 483
 484         /* Make sure IO area address is clear */
 485         hose->io_base_alloc = NULL;
 486
 487         /* If there's no IO to map on that bus, get away too */
 488         if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
 489                 return 0;
 490
 491         /* Let's allocate some IO space for that guy. We don't pass
 492          * VM_IOREMAP because we don't care about alignment tricks that
 493          * the core does in that case. Maybe we should due to stupid card
 494          * with incomplete address decoding but I'd rather not deal with
 495          * those outside of the reserved 64K legacy region.
 496          */
 497         area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
 498         if (area == NULL)
 499                 return -ENOMEM;
 500         hose->io_base_alloc = area->addr;
 501         hose->io_base_virt = (void __iomem *)(area->addr +
 502                                               hose->io_base_phys - phys_page);
 503
 504         DBG("IO mapping for PHB %s\n", hose->dn->full_name);
 505         DBG("  phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
 506             hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
 507         DBG("  size=0x%016lx (alloc=0x%016lx)\n",
 508             hose->pci_io_size, size_page);
 509
 510         /* Establish the mapping */
 511         if (__ioremap_at(phys_page, area->addr, size_page,
 512                          _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
 513                 return -ENOMEM;
 514
 515         /* Fixup hose IO resource */
 516         io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 517         hose->io_resource.start += io_virt_offset;
 518         hose->io_resource.end += io_virt_offset;
 519
 520         DBG("  hose->io_resource=0x%016lx...0x%016lx\n",
 521             hose->io_resource.start, hose->io_resource.end);
 522
 523         return 0;
 524 }
 525 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
 526
 527 void __devinit pcibios_do_bus_setup(struct pci_bus *bus)
 528 {
 529         struct pci_dev *dev;
 530
 531         if (ppc_md.pci_dma_bus_setup)
 532                 ppc_md.pci_dma_bus_setup(bus);
 533
 534         list_for_each_entry(dev, &bus->devices, bus_list)
 535                 pcibios_setup_new_device(dev);
 536 }
 537
 538 unsigned long pci_address_to_pio(phys_addr_t address)
 539 {
 540         struct pci_controller *hose, *tmp;
 541
 542         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 543                 if (address >= hose->io_base_phys &&
 544                     address < (hose->io_base_phys + hose->pci_io_size)) {
 545                         unsigned long base =
 546                                 (unsigned long)hose->io_base_virt - _IO_BASE;
 547                         return base + (address - hose->io_base_phys);
 548                 }
 549         }
 550         return (unsigned int)-1;
 551 }
 552 EXPORT_SYMBOL_GPL(pci_address_to_pio);
 553
 554
 555 #define IOBASE_BRIDGE_NUMBER    0
 556 #define IOBASE_MEMORY           1
 557 #define IOBASE_IO               2
 558 #define IOBASE_ISA_IO           3
 559 #define IOBASE_ISA_MEM          4
 560
 561 long sys_pciconfig_iobase(long which, unsigned long in_bus,
 562                           unsigned long in_devfn)
 563 {
 564         struct pci_controller* hose;
 565         struct list_head *ln;
 566         struct pci_bus *bus = NULL;
 567         struct device_node *hose_node;
 568
 569         /* Argh ! Please forgive me for that hack, but that's the
 570          * simplest way to get existing XFree to not lockup on some
 571          * G5 machines... So when something asks for bus 0 io base
 572          * (bus 0 is HT root), we return the AGP one instead.
 573          */
 574         if (machine_is_compatible("MacRISC4"))
 575                 if (in_bus == 0)
 576                         in_bus = 0xf0;
 577
 578         /* That syscall isn't quite compatible with PCI domains, but it's
 579          * used on pre-domains setup. We return the first match
 580          */
 581
 582         for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
 583                 bus = pci_bus_b(ln);
 584                 if (in_bus >= bus->number && in_bus <= bus->subordinate)
 585                         break;
 586                 bus = NULL;
 587         }
 588         if (bus == NULL || bus->sysdata == NULL)
 589                 return -ENODEV;
 590
 591         hose_node = (struct device_node *)bus->sysdata;
 592         hose = PCI_DN(hose_node)->phb;
 593
 594         switch (which) {
 595         case IOBASE_BRIDGE_NUMBER:
 596                 return (long)hose->first_busno;
 597         case IOBASE_MEMORY:
 598                 return (long)hose->pci_mem_offset;
 599         case IOBASE_IO:
 600                 return (long)hose->io_base_phys;
 601         case IOBASE_ISA_IO:
 602                 return (long)isa_io_base;
 603         case IOBASE_ISA_MEM:
 604                 return -EINVAL;
 605         }
 606
 607         return -EOPNOTSUPP;
 608 }
 609
 610 #ifdef CONFIG_NUMA
 611 int pcibus_to_node(struct pci_bus *bus)
 612 {
 613         struct pci_controller *phb = pci_bus_to_host(bus);
 614         return phb->node;
 615 }
 616 EXPORT_SYMBOL(pcibus_to_node);
 617 #endif