arch/powerpc/kernel/pci_64.c

   1 /*
   2  * Port for PPC64 David Engebretsen, IBM Corp.
   3  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   4  *
   5  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   6  *   Rework, based on alpha PCI code.
   7  *
   8  *      This program is free software; you can redistribute it and/or
   9  *      modify it under the terms of the GNU General Public License
  10  *      as published by the Free Software Foundation; either version
  11  *      2 of the License, or (at your option) any later version.
  12  */
  13
  14 #undef DEBUG
  15
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/mm.h>
  22 #include <linux/list.h>
  23 #include <linux/syscalls.h>
  24 #include <linux/irq.h>
  25 #include <linux/vmalloc.h>
  26
  27 #include <asm/processor.h>
  28 #include <asm/io.h>
  29 #include <asm/prom.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/byteorder.h>
  32 #include <asm/machdep.h>
  33 #include <asm/ppc-pci.h>
  34
  35 unsigned long pci_probe_only = 1;
  36
  37 /* pci_io_base -- the base address from which io bars are offsets.
  38  * This is the lowest I/O base address (so bar values are always positive),
  39  * and it *must* be the start of ISA space if an ISA bus exists because
  40  * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
  41  * is mapped on the first 64K of IO space
  42  */
  43 unsigned long pci_io_base = ISA_IO_BASE;
  44 EXPORT_SYMBOL(pci_io_base);
  45
  46 LIST_HEAD(hose_list);
  47
  48 static void fixup_broken_pcnet32(struct pci_dev* dev)
  49 {
  50         if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
  51                 dev->vendor = PCI_VENDOR_ID_AMD;
  52                 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
  53         }
  54 }
  55 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
  56
  57
  58 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
  59 {
  60         const u32 *prop;
  61         int len;
  62
  63         prop = of_get_property(np, name, &len);
  64         if (prop && len >= 4)
  65                 return *prop;
  66         return def;
  67 }
  68
  69 static unsigned int pci_parse_of_flags(u32 addr0)
  70 {
  71         unsigned int flags = 0;
  72
  73         if (addr0 & 0x02000000) {
  74                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
  75                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
  76                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
  77                 if (addr0 & 0x40000000)
  78                         flags |= IORESOURCE_PREFETCH
  79                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
  80         } else if (addr0 & 0x01000000)
  81                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
  82         return flags;
  83 }
  84
  85
  86 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
  87 {
  88         u64 base, size;
  89         unsigned int flags;
  90         struct resource *res;
  91         const u32 *addrs;
  92         u32 i;
  93         int proplen;
  94
  95         addrs = of_get_property(node, "assigned-addresses", &proplen);
  96         if (!addrs)
  97                 return;
  98         pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
  99         for (; proplen >= 20; proplen -= 20, addrs += 5) {
 100                 flags = pci_parse_of_flags(addrs[0]);
 101                 if (!flags)
 102                         continue;
 103                 base = of_read_number(&addrs[1], 2);
 104                 size = of_read_number(&addrs[3], 2);
 105                 if (!size)
 106                         continue;
 107                 i = addrs[0] & 0xff;
 108                 pr_debug("  base: %llx, size: %llx, i: %x\n",
 109                          (unsigned long long)base,
 110                          (unsigned long long)size, i);
 111
 112                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 113                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 114                 } else if (i == dev->rom_base_reg) {
 115                         res = &dev->resource[PCI_ROM_RESOURCE];
 116                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 117                 } else {
 118                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 119                         continue;
 120                 }
 121                 res->start = base;
 122                 res->end = base + size - 1;
 123                 res->flags = flags;
 124                 res->name = pci_name(dev);
 125         }
 126 }
 127
 128 struct pci_dev *of_create_pci_dev(struct device_node *node,
 129                                  struct pci_bus *bus, int devfn)
 130 {
 131         struct pci_dev *dev;
 132         const char *type;
 133
 134         dev = alloc_pci_dev();
 135         if (!dev)
 136                 return NULL;
 137         type = of_get_property(node, "device_type", NULL);
 138         if (type == NULL)
 139                 type = "";
 140
 141         pr_debug("    create device, devfn: %x, type: %s\n", devfn, type);
 142
 143         dev->bus = bus;
 144         dev->sysdata = node;
 145         dev->dev.parent = bus->bridge;
 146         dev->dev.bus = &pci_bus_type;
 147         dev->devfn = devfn;
 148         dev->multifunction = 0;         /* maybe a lie? */
 149
 150         dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
 151         dev->device = get_int_prop(node, "device-id", 0xffff);
 152         dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
 153         dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
 154
 155         dev->cfg_size = pci_cfg_space_size(dev);
 156
 157         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 158                 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 159         dev->class = get_int_prop(node, "class-code", 0);
 160         dev->revision = get_int_prop(node, "revision-id", 0);
 161
 162         pr_debug("    class: 0x%x\n", dev->class);
 163         pr_debug("    revision: 0x%x\n", dev->revision);
 164
 165         dev->current_state = 4;         /* unknown power state */
 166         dev->error_state = pci_channel_io_normal;
 167         dev->dma_mask = 0xffffffff;
 168
 169         if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
 170                 /* a PCI-PCI bridge */
 171                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 172                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 173         } else if (!strcmp(type, "cardbus")) {
 174                 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 175         } else {
 176                 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 177                 dev->rom_base_reg = PCI_ROM_ADDRESS;
 178                 /* Maybe do a default OF mapping here */
 179                 dev->irq = NO_IRQ;
 180         }
 181
 182         pci_parse_of_addrs(node, dev);
 183
 184         pr_debug("    adding to system ...\n");
 185
 186         pci_device_add(dev, bus);
 187
 188         return dev;
 189 }
 190 EXPORT_SYMBOL(of_create_pci_dev);
 191
 192 static void __devinit __of_scan_bus(struct device_node *node,
 193                                     struct pci_bus *bus, int rescan_existing)
 194 {
 195         struct device_node *child;
 196         const u32 *reg;
 197         int reglen, devfn;
 198         struct pci_dev *dev;
 199
 200         pr_debug("of_scan_bus(%s) bus no %d... \n",
 201                  node->full_name, bus->number);
 202
 203         /* Scan direct children */
 204         for_each_child_of_node(node, child) {
 205                 pr_debug("  * %s\n", child->full_name);
 206                 reg = of_get_property(child, "reg", &reglen);
 207                 if (reg == NULL || reglen < 20)
 208                         continue;
 209                 devfn = (reg[0] >> 8) & 0xff;
 210
 211                 /* create a new pci_dev for this device */
 212                 dev = of_create_pci_dev(child, bus, devfn);
 213                 if (!dev)
 214                         continue;
 215                 pr_debug("    dev header type: %x\n", dev->hdr_type);
 216         }
 217
 218         /* Apply all fixups necessary. We don't fixup the bus "self"
 219          * for an existing bridge that is being rescanned
 220          */
 221         if (!rescan_existing)
 222                 pcibios_setup_bus_self(bus);
 223         pcibios_setup_bus_devices(bus);
 224
 225         /* Now scan child busses */
 226         list_for_each_entry(dev, &bus->devices, bus_list) {
 227                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 228                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
 229                         struct device_node *child = pci_device_to_OF_node(dev);
 230                         if (dev)
 231                                 of_scan_pci_bridge(child, dev);
 232                 }
 233         }
 234 }
 235
 236 void __devinit of_scan_bus(struct device_node *node,
 237                            struct pci_bus *bus)
 238 {
 239         __of_scan_bus(node, bus, 0);
 240 }
 241 EXPORT_SYMBOL_GPL(of_scan_bus);
 242
 243 void __devinit of_rescan_bus(struct device_node *node,
 244                              struct pci_bus *bus)
 245 {
 246         __of_scan_bus(node, bus, 1);
 247 }
 248 EXPORT_SYMBOL_GPL(of_rescan_bus);
 249
 250 void __devinit of_scan_pci_bridge(struct device_node *node,
 251                                   struct pci_dev *dev)
 252 {
 253         struct pci_bus *bus;
 254         const u32 *busrange, *ranges;
 255         int len, i, mode;
 256         struct resource *res;
 257         unsigned int flags;
 258         u64 size;
 259
 260         pr_debug("of_scan_pci_bridge(%s)\n", node->full_name);
 261
 262         /* parse bus-range property */
 263         busrange = of_get_property(node, "bus-range", &len);
 264         if (busrange == NULL || len != 8) {
 265                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 266                        node->full_name);
 267                 return;
 268         }
 269         ranges = of_get_property(node, "ranges", &len);
 270         if (ranges == NULL) {
 271                 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
 272                        node->full_name);
 273                 return;
 274         }
 275
 276         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 277         if (!bus) {
 278                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 279                        node->full_name);
 280                 return;
 281         }
 282
 283         bus->primary = dev->bus->number;
 284         bus->subordinate = busrange[1];
 285         bus->bridge_ctl = 0;
 286         bus->sysdata = node;
 287
 288         /* parse ranges property */
 289         /* PCI #address-cells == 3 and #size-cells == 2 always */
 290         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 291         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 292                 res->flags = 0;
 293                 bus->resource[i] = res;
 294                 ++res;
 295         }
 296         i = 1;
 297         for (; len >= 32; len -= 32, ranges += 8) {
 298                 flags = pci_parse_of_flags(ranges[0]);
 299                 size = of_read_number(&ranges[6], 2);
 300                 if (flags == 0 || size == 0)
 301                         continue;
 302                 if (flags & IORESOURCE_IO) {
 303                         res = bus->resource[0];
 304                         if (res->flags) {
 305                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 306                                        " for bridge %s\n", node->full_name);
 307                                 continue;
 308                         }
 309                 } else {
 310                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 311                                 printk(KERN_ERR "PCI: too many memory ranges"
 312                                        " for bridge %s\n", node->full_name);
 313                                 continue;
 314                         }
 315                         res = bus->resource[i];
 316                         ++i;
 317                 }
 318                 res->start = of_read_number(&ranges[1], 2);
 319                 res->end = res->start + size - 1;
 320                 res->flags = flags;
 321         }
 322         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 323                 bus->number);
 324         pr_debug("    bus name: %s\n", bus->name);
 325
 326         mode = PCI_PROBE_NORMAL;
 327         if (ppc_md.pci_probe_mode)
 328                 mode = ppc_md.pci_probe_mode(bus);
 329         pr_debug("    probe mode: %d\n", mode);
 330
 331         if (mode == PCI_PROBE_DEVTREE)
 332                 of_scan_bus(node, bus);
 333         else if (mode == PCI_PROBE_NORMAL)
 334                 pci_scan_child_bus(bus);
 335 }
 336 EXPORT_SYMBOL(of_scan_pci_bridge);
 337
 338 void __devinit scan_phb(struct pci_controller *hose)
 339 {
 340         struct pci_bus *bus;
 341         struct device_node *node = hose->dn;
 342         int mode;
 343
 344         pr_debug("PCI: Scanning PHB %s\n",
 345                  node ? node->full_name : "<NO NAME>");
 346
 347         /* Create an empty bus for the toplevel */
 348         bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
 349         if (bus == NULL) {
 350                 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
 351                        hose->global_number);
 352                 return;
 353         }
 354         bus->secondary = hose->first_busno;
 355         hose->bus = bus;
 356
 357         /* Get some IO space for the new PHB */
 358         pcibios_map_io_space(bus);
 359
 360         /* Wire up PHB bus resources */
 361         pcibios_setup_phb_resources(hose);
 362
 363         /* Get probe mode and perform scan */
 364         mode = PCI_PROBE_NORMAL;
 365         if (node && ppc_md.pci_probe_mode)
 366                 mode = ppc_md.pci_probe_mode(bus);
 367         pr_debug("    probe mode: %d\n", mode);
 368         if (mode == PCI_PROBE_DEVTREE) {
 369                 bus->subordinate = hose->last_busno;
 370                 of_scan_bus(node, bus);
 371         }
 372
 373         if (mode == PCI_PROBE_NORMAL)
 374                 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
 375 }
 376
 377 static int __init pcibios_init(void)
 378 {
 379         struct pci_controller *hose, *tmp;
 380
 381         printk(KERN_INFO "PCI: Probing PCI hardware\n");
 382
 383         /* For now, override phys_mem_access_prot. If we need it,g
 384          * later, we may move that initialization to each ppc_md
 385          */
 386         ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
 387
 388         if (pci_probe_only)
 389                 ppc_pci_flags |= PPC_PCI_PROBE_ONLY;
 390
 391         /* On ppc64, we always enable PCI domains and we keep domain 0
 392          * backward compatible in /proc for video cards
 393          */
 394         ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
 395
 396         /* Scan all of the recorded PCI controllers.  */
 397         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 398                 scan_phb(hose);
 399                 pci_bus_add_devices(hose->bus);
 400         }
 401
 402         /* Call common code to handle resource allocation */
 403         pcibios_resource_survey();
 404
 405         printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
 406
 407         return 0;
 408 }
 409
 410 subsys_initcall(pcibios_init);
 411
 412 #ifdef CONFIG_HOTPLUG
 413
 414 int pcibios_unmap_io_space(struct pci_bus *bus)
 415 {
 416         struct pci_controller *hose;
 417
 418         WARN_ON(bus == NULL);
 419
 420         /* If this is not a PHB, we only flush the hash table over
 421          * the area mapped by this bridge. We don't play with the PTE
 422          * mappings since we might have to deal with sub-page alignemnts
 423          * so flushing the hash table is the only sane way to make sure
 424          * that no hash entries are covering that removed bridge area
 425          * while still allowing other busses overlapping those pages
 426          */
 427         if (bus->self) {
 428                 struct resource *res = bus->resource[0];
 429
 430                 pr_debug("IO unmapping for PCI-PCI bridge %s\n",
 431                          pci_name(bus->self));
 432
 433                 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
 434                                          res->end + _IO_BASE + 1);
 435                 return 0;
 436         }
 437
 438         /* Get the host bridge */
 439         hose = pci_bus_to_host(bus);
 440
 441         /* Check if we have IOs allocated */
 442         if (hose->io_base_alloc == 0)
 443                 return 0;
 444
 445         pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
 446         pr_debug("  alloc=0x%p\n", hose->io_base_alloc);
 447
 448         /* This is a PHB, we fully unmap the IO area */
 449         vunmap(hose->io_base_alloc);
 450
 451         return 0;
 452 }
 453 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
 454
 455 #endif /* CONFIG_HOTPLUG */
 456
 457 int __devinit pcibios_map_io_space(struct pci_bus *bus)
 458 {
 459         struct vm_struct *area;
 460         unsigned long phys_page;
 461         unsigned long size_page;
 462         unsigned long io_virt_offset;
 463         struct pci_controller *hose;
 464
 465         WARN_ON(bus == NULL);
 466
 467         /* If this not a PHB, nothing to do, page tables still exist and
 468          * thus HPTEs will be faulted in when needed
 469          */
 470         if (bus->self) {
 471                 pr_debug("IO mapping for PCI-PCI bridge %s\n",
 472                          pci_name(bus->self));
 473                 pr_debug("  virt=0x%016llx...0x%016llx\n",
 474                          bus->resource[0]->start + _IO_BASE,
 475                          bus->resource[0]->end + _IO_BASE);
 476                 return 0;
 477         }
 478
 479         /* Get the host bridge */
 480         hose = pci_bus_to_host(bus);
 481         phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
 482         size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
 483
 484         /* Make sure IO area address is clear */
 485         hose->io_base_alloc = NULL;
 486
 487         /* If there's no IO to map on that bus, get away too */
 488         if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
 489                 return 0;
 490
 491         /* Let's allocate some IO space for that guy. We don't pass
 492          * VM_IOREMAP because we don't care about alignment tricks that
 493          * the core does in that case. Maybe we should due to stupid card
 494          * with incomplete address decoding but I'd rather not deal with
 495          * those outside of the reserved 64K legacy region.
 496          */
 497         area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
 498         if (area == NULL)
 499                 return -ENOMEM;
 500         hose->io_base_alloc = area->addr;
 501         hose->io_base_virt = (void __iomem *)(area->addr +
 502                                               hose->io_base_phys - phys_page);
 503
 504         pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
 505         pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
 506                  hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
 507         pr_debug("  size=0x%016lx (alloc=0x%016lx)\n",
 508                  hose->pci_io_size, size_page);
 509
 510         /* Establish the mapping */
 511         if (__ioremap_at(phys_page, area->addr, size_page,
 512                          _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
 513                 return -ENOMEM;
 514
 515         /* Fixup hose IO resource */
 516         io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 517         hose->io_resource.start += io_virt_offset;
 518         hose->io_resource.end += io_virt_offset;
 519
 520         pr_debug("  hose->io_resource=0x%016llx...0x%016llx\n",
 521                  hose->io_resource.start, hose->io_resource.end);
 522
 523         return 0;
 524 }
 525 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
 526
 527 unsigned long pci_address_to_pio(phys_addr_t address)
 528 {
 529         struct pci_controller *hose, *tmp;
 530
 531         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 532                 if (address >= hose->io_base_phys &&
 533                     address < (hose->io_base_phys + hose->pci_io_size)) {
 534                         unsigned long base =
 535                                 (unsigned long)hose->io_base_virt - _IO_BASE;
 536                         return base + (address - hose->io_base_phys);
 537                 }
 538         }
 539         return (unsigned int)-1;
 540 }
 541 EXPORT_SYMBOL_GPL(pci_address_to_pio);
 542
 543
 544 #define IOBASE_BRIDGE_NUMBER    0
 545 #define IOBASE_MEMORY           1
 546 #define IOBASE_IO               2
 547 #define IOBASE_ISA_IO           3
 548 #define IOBASE_ISA_MEM          4
 549
 550 long sys_pciconfig_iobase(long which, unsigned long in_bus,
 551                           unsigned long in_devfn)
 552 {
 553         struct pci_controller* hose;
 554         struct list_head *ln;
 555         struct pci_bus *bus = NULL;
 556         struct device_node *hose_node;
 557
 558         /* Argh ! Please forgive me for that hack, but that's the
 559          * simplest way to get existing XFree to not lockup on some
 560          * G5 machines... So when something asks for bus 0 io base
 561          * (bus 0 is HT root), we return the AGP one instead.
 562          */
 563         if (in_bus == 0 && machine_is_compatible("MacRISC4")) {
 564                 struct device_node *agp;
 565
 566                 agp = of_find_compatible_node(NULL, NULL, "u3-agp");
 567                 if (agp)
 568                         in_bus = 0xf0;
 569                 of_node_put(agp);
 570         }
 571
 572         /* That syscall isn't quite compatible with PCI domains, but it's
 573          * used on pre-domains setup. We return the first match
 574          */
 575
 576         for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
 577                 bus = pci_bus_b(ln);
 578                 if (in_bus >= bus->number && in_bus <= bus->subordinate)
 579                         break;
 580                 bus = NULL;
 581         }
 582         if (bus == NULL || bus->sysdata == NULL)
 583                 return -ENODEV;
 584
 585         hose_node = (struct device_node *)bus->sysdata;
 586         hose = PCI_DN(hose_node)->phb;
 587
 588         switch (which) {
 589         case IOBASE_BRIDGE_NUMBER:
 590                 return (long)hose->first_busno;
 591         case IOBASE_MEMORY:
 592                 return (long)hose->pci_mem_offset;
 593         case IOBASE_IO:
 594                 return (long)hose->io_base_phys;
 595         case IOBASE_ISA_IO:
 596                 return (long)isa_io_base;
 597         case IOBASE_ISA_MEM:
 598                 return -EINVAL;
 599         }
 600
 601         return -EOPNOTSUPP;
 602 }
 603
 604 #ifdef CONFIG_NUMA
 605 int pcibus_to_node(struct pci_bus *bus)
 606 {
 607         struct pci_controller *phb = pci_bus_to_host(bus);
 608         return phb->node;
 609 }
 610 EXPORT_SYMBOL(pcibus_to_node);
 611 #endif