2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only
= 1;
43 int pci_assign_all_buses
= 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask
;
51 EXPORT_SYMBOL(io_page_mask
);
53 #ifdef CONFIG_PPC_MULTIPLATFORM
54 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
55 static void do_bus_setup(struct pci_bus
*bus
);
56 static void phbs_remap_io(void);
59 /* pci_io_base -- the base address from which io bars are offsets.
60 * This is the lowest I/O base address (so bar values are always positive),
61 * and it *must* be the start of ISA space if an ISA bus exists because
62 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
63 * page is mapped and isa_io_limit prevents access to it.
65 unsigned long isa_io_base
; /* NULL if no ISA bus */
66 EXPORT_SYMBOL(isa_io_base
);
67 unsigned long pci_io_base
;
68 EXPORT_SYMBOL(pci_io_base
);
70 void iSeries_pcibios_init(void);
74 struct dma_mapping_ops pci_dma_ops
;
75 EXPORT_SYMBOL(pci_dma_ops
);
77 int global_phb_number
; /* Global phb counter */
79 /* Cached ISA bridge dev. */
80 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
82 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
84 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
85 dev
->vendor
= PCI_VENDOR_ID_AMD
;
86 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
89 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
91 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
94 unsigned long offset
= 0;
95 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
100 if (res
->flags
& IORESOURCE_IO
)
101 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
103 if (res
->flags
& IORESOURCE_MEM
)
104 offset
= hose
->pci_mem_offset
;
106 region
->start
= res
->start
- offset
;
107 region
->end
= res
->end
- offset
;
110 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
111 struct pci_bus_region
*region
)
113 unsigned long offset
= 0;
114 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
119 if (res
->flags
& IORESOURCE_IO
)
120 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
122 if (res
->flags
& IORESOURCE_MEM
)
123 offset
= hose
->pci_mem_offset
;
125 res
->start
= region
->start
+ offset
;
126 res
->end
= region
->end
+ offset
;
129 #ifdef CONFIG_HOTPLUG
130 EXPORT_SYMBOL(pcibios_resource_to_bus
);
131 EXPORT_SYMBOL(pcibios_bus_to_resource
);
135 * We need to avoid collisions with `mirrored' VGA ports
136 * and other strange ISA hardware, so we always want the
137 * addresses to be allocated in the 0x000-0x0ff region
140 * Why? Because some silly external IO cards only decode
141 * the low 10 bits of the IO address. The 0x00-0xff region
142 * is reserved for motherboard devices that decode all 16
143 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
144 * but we want to try to avoid allocating at 0x2900-0x2bff
145 * which might have be mirrored at 0x0100-0x03ff..
147 void pcibios_align_resource(void *data
, struct resource
*res
,
148 unsigned long size
, unsigned long align
)
150 struct pci_dev
*dev
= data
;
151 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
152 unsigned long start
= res
->start
;
153 unsigned long alignto
;
155 if (res
->flags
& IORESOURCE_IO
) {
156 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
158 /* Make sure we start at our min on all hoses */
159 if (start
- offset
< PCIBIOS_MIN_IO
)
160 start
= PCIBIOS_MIN_IO
+ offset
;
163 * Put everything into 0x00-0xff region modulo 0x400
166 start
= (start
+ 0x3ff) & ~0x3ff;
168 } else if (res
->flags
& IORESOURCE_MEM
) {
169 /* Make sure we start at our min on all hoses */
170 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
171 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
173 /* Align to multiple of size of minimum base. */
174 alignto
= max(0x1000UL
, align
);
175 start
= ALIGN(start
, alignto
);
181 static DEFINE_SPINLOCK(hose_spinlock
);
184 * pci_controller(phb) initialized common variables.
186 static void __devinit
pci_setup_pci_controller(struct pci_controller
*hose
)
188 memset(hose
, 0, sizeof(struct pci_controller
));
190 spin_lock(&hose_spinlock
);
191 hose
->global_number
= global_phb_number
++;
192 list_add_tail(&hose
->list_node
, &hose_list
);
193 spin_unlock(&hose_spinlock
);
196 static void add_linux_pci_domain(struct device_node
*dev
,
197 struct pci_controller
*phb
)
199 struct property
*of_prop
;
202 of_prop
= (struct property
*)
203 get_property(dev
, "linux,pci-domain", &size
);
206 WARN_ON(of_prop
&& size
< sizeof(int));
207 if (of_prop
&& size
< sizeof(int))
209 size
= sizeof(struct property
) + sizeof(int);
210 if (of_prop
== NULL
) {
212 of_prop
= kmalloc(size
, GFP_KERNEL
);
214 of_prop
= alloc_bootmem(size
);
216 memset(of_prop
, 0, sizeof(struct property
));
217 of_prop
->name
= "linux,pci-domain";
218 of_prop
->length
= sizeof(int);
219 of_prop
->value
= (unsigned char *)&of_prop
[1];
220 *((int *)of_prop
->value
) = phb
->global_number
;
221 prom_add_property(dev
, of_prop
);
224 struct pci_controller
* pcibios_alloc_controller(struct device_node
*dev
)
226 struct pci_controller
*phb
;
229 phb
= kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
231 phb
= alloc_bootmem(sizeof (struct pci_controller
));
234 pci_setup_pci_controller(phb
);
235 phb
->arch_data
= dev
;
236 phb
->is_dynamic
= mem_init_done
;
238 add_linux_pci_domain(dev
, phb
);
242 void pcibios_free_controller(struct pci_controller
*phb
)
244 if (phb
->arch_data
) {
245 struct device_node
*np
= phb
->arch_data
;
246 int *domain
= (int *)get_property(np
,
247 "linux,pci-domain", NULL
);
255 #ifndef CONFIG_PPC_ISERIES
256 void __devinit
pcibios_claim_one_bus(struct pci_bus
*b
)
259 struct pci_bus
*child_bus
;
261 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
264 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
265 struct resource
*r
= &dev
->resource
[i
];
267 if (r
->parent
|| !r
->start
|| !r
->flags
)
269 pci_claim_resource(dev
, i
);
273 list_for_each_entry(child_bus
, &b
->children
, node
)
274 pcibios_claim_one_bus(child_bus
);
276 #ifdef CONFIG_HOTPLUG
277 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
280 static void __init
pcibios_claim_of_setup(void)
284 list_for_each_entry(b
, &pci_root_buses
, node
)
285 pcibios_claim_one_bus(b
);
289 #ifdef CONFIG_PPC_MULTIPLATFORM
290 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
295 prop
= (u32
*) get_property(np
, name
, &len
);
296 if (prop
&& len
>= 4)
301 static unsigned int pci_parse_of_flags(u32 addr0
)
303 unsigned int flags
= 0;
305 if (addr0
& 0x02000000) {
306 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
307 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
308 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
309 if (addr0
& 0x40000000)
310 flags
|= IORESOURCE_PREFETCH
311 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
312 } else if (addr0
& 0x01000000)
313 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
317 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
319 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
323 struct resource
*res
;
327 addrs
= (u32
*) get_property(node
, "assigned-addresses", &proplen
);
330 DBG(" parse addresses (%d bytes) @ %p\n", proplen
, addrs
);
331 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
332 flags
= pci_parse_of_flags(addrs
[0]);
335 base
= GET_64BIT(addrs
, 1);
336 size
= GET_64BIT(addrs
, 3);
340 DBG(" base: %llx, size: %llx, i: %x\n",
341 (unsigned long long)base
, (unsigned long long)size
, i
);
343 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
344 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
345 } else if (i
== dev
->rom_base_reg
) {
346 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
347 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
349 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
353 res
->end
= base
+ size
- 1;
355 res
->name
= pci_name(dev
);
356 fixup_resource(res
, dev
);
360 struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
361 struct pci_bus
*bus
, int devfn
)
366 dev
= kmalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
369 type
= get_property(node
, "device_type", NULL
);
373 DBG(" create device, devfn: %x, type: %s\n", devfn
, type
);
375 memset(dev
, 0, sizeof(struct pci_dev
));
378 dev
->dev
.parent
= bus
->bridge
;
379 dev
->dev
.bus
= &pci_bus_type
;
381 dev
->multifunction
= 0; /* maybe a lie? */
383 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
384 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
385 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
386 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
388 dev
->cfg_size
= pci_cfg_space_size(dev
);
390 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
391 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
392 dev
->class = get_int_prop(node
, "class-code", 0);
394 DBG(" class: 0x%x\n", dev
->class);
396 dev
->current_state
= 4; /* unknown power state */
398 if (!strcmp(type
, "pci")) {
399 /* a PCI-PCI bridge */
400 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
401 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
402 } else if (!strcmp(type
, "cardbus")) {
403 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
405 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
406 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
408 if (node
->n_intrs
> 0) {
409 dev
->irq
= node
->intrs
[0].line
;
410 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
,
415 pci_parse_of_addrs(node
, dev
);
417 DBG(" adding to system ...\n");
419 pci_device_add(dev
, bus
);
421 /* XXX pci_scan_msi_device(dev); */
425 EXPORT_SYMBOL(of_create_pci_dev
);
427 void __devinit
of_scan_bus(struct device_node
*node
,
430 struct device_node
*child
= NULL
;
435 DBG("of_scan_bus(%s) bus no %d... \n", node
->full_name
, bus
->number
);
437 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
438 DBG(" * %s\n", child
->full_name
);
439 reg
= (u32
*) get_property(child
, "reg", ®len
);
440 if (reg
== NULL
|| reglen
< 20)
442 devfn
= (reg
[0] >> 8) & 0xff;
444 /* create a new pci_dev for this device */
445 dev
= of_create_pci_dev(child
, bus
, devfn
);
448 DBG("dev header type: %x\n", dev
->hdr_type
);
450 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
451 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
452 of_scan_pci_bridge(child
, dev
);
457 EXPORT_SYMBOL(of_scan_bus
);
459 void __devinit
of_scan_pci_bridge(struct device_node
*node
,
463 u32
*busrange
, *ranges
;
465 struct resource
*res
;
469 DBG("of_scan_pci_bridge(%s)\n", node
->full_name
);
471 /* parse bus-range property */
472 busrange
= (u32
*) get_property(node
, "bus-range", &len
);
473 if (busrange
== NULL
|| len
!= 8) {
474 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
478 ranges
= (u32
*) get_property(node
, "ranges", &len
);
479 if (ranges
== NULL
) {
480 printk(KERN_DEBUG
"Can't get ranges for PCI-PCI bridge %s\n",
485 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
487 printk(KERN_ERR
"Failed to create pci bus for %s\n",
492 bus
->primary
= dev
->bus
->number
;
493 bus
->subordinate
= busrange
[1];
497 /* parse ranges property */
498 /* PCI #address-cells == 3 and #size-cells == 2 always */
499 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
500 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
502 bus
->resource
[i
] = res
;
506 for (; len
>= 32; len
-= 32, ranges
+= 8) {
507 flags
= pci_parse_of_flags(ranges
[0]);
508 size
= GET_64BIT(ranges
, 6);
509 if (flags
== 0 || size
== 0)
511 if (flags
& IORESOURCE_IO
) {
512 res
= bus
->resource
[0];
514 printk(KERN_ERR
"PCI: ignoring extra I/O range"
515 " for bridge %s\n", node
->full_name
);
519 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
520 printk(KERN_ERR
"PCI: too many memory ranges"
521 " for bridge %s\n", node
->full_name
);
524 res
= bus
->resource
[i
];
527 res
->start
= GET_64BIT(ranges
, 1);
528 res
->end
= res
->start
+ size
- 1;
530 fixup_resource(res
, dev
);
532 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
534 DBG(" bus name: %s\n", bus
->name
);
536 mode
= PCI_PROBE_NORMAL
;
537 if (ppc_md
.pci_probe_mode
)
538 mode
= ppc_md
.pci_probe_mode(bus
);
539 DBG(" probe mode: %d\n", mode
);
541 if (mode
== PCI_PROBE_DEVTREE
)
542 of_scan_bus(node
, bus
);
543 else if (mode
== PCI_PROBE_NORMAL
)
544 pci_scan_child_bus(bus
);
546 EXPORT_SYMBOL(of_scan_pci_bridge
);
547 #endif /* CONFIG_PPC_MULTIPLATFORM */
549 void __devinit
scan_phb(struct pci_controller
*hose
)
552 struct device_node
*node
= hose
->arch_data
;
554 struct resource
*res
;
556 DBG("Scanning PHB %s\n", node
? node
->full_name
: "<NO NAME>");
558 bus
= pci_create_bus(NULL
, hose
->first_busno
, hose
->ops
, node
);
560 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
561 hose
->global_number
);
564 bus
->secondary
= hose
->first_busno
;
567 bus
->resource
[0] = res
= &hose
->io_resource
;
568 if (res
->flags
&& request_resource(&ioport_resource
, res
))
569 printk(KERN_ERR
"Failed to request PCI IO region "
570 "on PCI domain %04x\n", hose
->global_number
);
572 for (i
= 0; i
< 3; ++i
) {
573 res
= &hose
->mem_resources
[i
];
574 bus
->resource
[i
+1] = res
;
575 if (res
->flags
&& request_resource(&iomem_resource
, res
))
576 printk(KERN_ERR
"Failed to request PCI memory region "
577 "on PCI domain %04x\n", hose
->global_number
);
580 mode
= PCI_PROBE_NORMAL
;
581 #ifdef CONFIG_PPC_MULTIPLATFORM
582 if (node
&& ppc_md
.pci_probe_mode
)
583 mode
= ppc_md
.pci_probe_mode(bus
);
584 DBG(" probe mode: %d\n", mode
);
585 if (mode
== PCI_PROBE_DEVTREE
) {
586 bus
->subordinate
= hose
->last_busno
;
587 of_scan_bus(node
, bus
);
589 #endif /* CONFIG_PPC_MULTIPLATFORM */
590 if (mode
== PCI_PROBE_NORMAL
)
591 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
594 static int __init
pcibios_init(void)
596 struct pci_controller
*hose
, *tmp
;
598 /* For now, override phys_mem_access_prot. If we need it,
599 * later, we may move that initialization to each ppc_md
601 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
603 #ifdef CONFIG_PPC_ISERIES
604 iSeries_pcibios_init();
607 printk("PCI: Probing PCI hardware\n");
609 /* Scan all of the recorded PCI controllers. */
610 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
612 pci_bus_add_devices(hose
->bus
);
615 #ifndef CONFIG_PPC_ISERIES
617 pcibios_claim_of_setup();
619 /* FIXME: `else' will be removed when
620 pci_assign_unassigned_resources() is able to work
621 correctly with [partially] allocated PCI tree. */
622 pci_assign_unassigned_resources();
623 #endif /* !CONFIG_PPC_ISERIES */
625 /* Call machine dependent final fixup */
626 if (ppc_md
.pcibios_fixup
)
627 ppc_md
.pcibios_fixup();
629 /* Cache the location of the ISA bridge (if we have one) */
630 ppc64_isabridge_dev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
631 if (ppc64_isabridge_dev
!= NULL
)
632 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev
));
634 #ifdef CONFIG_PPC_MULTIPLATFORM
635 /* map in PCI I/O space */
639 printk("PCI: Probing PCI hardware done\n");
644 subsys_initcall(pcibios_init
);
646 char __init
*pcibios_setup(char *str
)
651 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
656 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
659 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
660 struct resource
*res
= &dev
->resource
[i
];
662 /* Only set up the requested stuff */
663 if (!(mask
& (1<<i
)))
666 if (res
->flags
& IORESOURCE_IO
)
667 cmd
|= PCI_COMMAND_IO
;
668 if (res
->flags
& IORESOURCE_MEM
)
669 cmd
|= PCI_COMMAND_MEMORY
;
673 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
675 /* Enable the appropriate bits in the PCI command register. */
676 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
682 * Return the domain number for this bus.
684 int pci_domain_nr(struct pci_bus
*bus
)
686 #ifdef CONFIG_PPC_ISERIES
689 struct pci_controller
*hose
= pci_bus_to_host(bus
);
691 return hose
->global_number
;
695 EXPORT_SYMBOL(pci_domain_nr
);
697 /* Decide whether to display the domain number in /proc */
698 int pci_proc_domain(struct pci_bus
*bus
)
700 #ifdef CONFIG_PPC_ISERIES
703 struct pci_controller
*hose
= pci_bus_to_host(bus
);
709 * Platform support for /proc/bus/pci/X/Y mmap()s,
710 * modelled on the sparc64 implementation by Dave Miller.
715 * Adjust vm_pgoff of VMA such that it is the physical page offset
716 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
718 * Basically, the user finds the base address for his device which he wishes
719 * to mmap. They read the 32-bit value from the config space base register,
720 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
721 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
723 * Returns negative error code on failure, zero on success.
725 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
726 unsigned long *offset
,
727 enum pci_mmap_state mmap_state
)
729 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
730 unsigned long io_offset
= 0;
734 return NULL
; /* should never happen */
736 /* If memory, add on the PCI bridge address offset */
737 if (mmap_state
== pci_mmap_mem
) {
738 *offset
+= hose
->pci_mem_offset
;
739 res_bit
= IORESOURCE_MEM
;
741 io_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
742 *offset
+= io_offset
;
743 res_bit
= IORESOURCE_IO
;
747 * Check that the offset requested corresponds to one of the
748 * resources of the device.
750 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
751 struct resource
*rp
= &dev
->resource
[i
];
752 int flags
= rp
->flags
;
754 /* treat ROM as memory (should be already) */
755 if (i
== PCI_ROM_RESOURCE
)
756 flags
|= IORESOURCE_MEM
;
758 /* Active and same type? */
759 if ((flags
& res_bit
) == 0)
762 /* In the range of this resource? */
763 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
766 /* found it! construct the final physical address */
767 if (mmap_state
== pci_mmap_io
)
768 *offset
+= hose
->io_base_phys
- io_offset
;
776 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
779 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
781 enum pci_mmap_state mmap_state
,
784 unsigned long prot
= pgprot_val(protection
);
786 /* Write combine is always 0 on non-memory space mappings. On
787 * memory space, if the user didn't pass 1, we check for a
788 * "prefetchable" resource. This is a bit hackish, but we use
789 * this to workaround the inability of /sysfs to provide a write
792 if (mmap_state
!= pci_mmap_mem
)
794 else if (write_combine
== 0) {
795 if (rp
->flags
& IORESOURCE_PREFETCH
)
799 /* XXX would be nice to have a way to ask for write-through */
800 prot
|= _PAGE_NO_CACHE
;
802 prot
&= ~_PAGE_GUARDED
;
804 prot
|= _PAGE_GUARDED
;
806 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev
), rp
->start
,
809 return __pgprot(prot
);
813 * This one is used by /dev/mem and fbdev who have no clue about the
814 * PCI device, it tries to find the PCI device first and calls the
817 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
822 struct pci_dev
*pdev
= NULL
;
823 struct resource
*found
= NULL
;
824 unsigned long prot
= pgprot_val(protection
);
825 unsigned long offset
= pfn
<< PAGE_SHIFT
;
828 if (page_is_ram(pfn
))
829 return __pgprot(prot
);
831 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
833 for_each_pci_dev(pdev
) {
834 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
835 struct resource
*rp
= &pdev
->resource
[i
];
836 int flags
= rp
->flags
;
838 /* Active and same type? */
839 if ((flags
& IORESOURCE_MEM
) == 0)
841 /* In the range of this resource? */
842 if (offset
< (rp
->start
& PAGE_MASK
) ||
852 if (found
->flags
& IORESOURCE_PREFETCH
)
853 prot
&= ~_PAGE_GUARDED
;
857 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
859 return __pgprot(prot
);
864 * Perform the actual remap of the pages for a PCI device mapping, as
865 * appropriate for this architecture. The region in the process to map
866 * is described by vm_start and vm_end members of VMA, the base physical
867 * address is found in vm_pgoff.
868 * The pci device structure is provided so that architectures may make mapping
869 * decisions on a per-device or per-bus basis.
871 * Returns a negative error code on failure, zero on success.
873 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
874 enum pci_mmap_state mmap_state
, int write_combine
)
876 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
880 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
884 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
885 vma
->vm_flags
|= VM_SHM
| VM_LOCKED
| VM_IO
;
886 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
888 mmap_state
, write_combine
);
890 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
891 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
896 #ifdef CONFIG_PPC_MULTIPLATFORM
897 static ssize_t
pci_show_devspec(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
899 struct pci_dev
*pdev
;
900 struct device_node
*np
;
902 pdev
= to_pci_dev (dev
);
903 np
= pci_device_to_OF_node(pdev
);
904 if (np
== NULL
|| np
->full_name
== NULL
)
906 return sprintf(buf
, "%s", np
->full_name
);
908 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
909 #endif /* CONFIG_PPC_MULTIPLATFORM */
911 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
913 #ifdef CONFIG_PPC_MULTIPLATFORM
914 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
915 #endif /* CONFIG_PPC_MULTIPLATFORM */
918 #ifdef CONFIG_PPC_MULTIPLATFORM
920 #define ISA_SPACE_MASK 0x1
921 #define ISA_SPACE_IO 0x1
923 static void __devinit
pci_process_ISA_OF_ranges(struct device_node
*isa_node
,
924 unsigned long phb_io_base_phys
,
925 void __iomem
* phb_io_base_virt
)
927 /* Remove these asap */
941 struct isa_address isa_addr
;
942 struct pci_address pci_addr
;
946 struct isa_range
*range
;
947 unsigned long pci_addr
;
948 unsigned int isa_addr
;
952 range
= (struct isa_range
*) get_property(isa_node
, "ranges", &rlen
);
953 if (range
== NULL
|| (rlen
< sizeof(struct isa_range
))) {
954 printk(KERN_ERR
"no ISA ranges or unexpected isa range size,"
956 __ioremap_explicit(phb_io_base_phys
,
957 (unsigned long)phb_io_base_virt
,
958 0x10000, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
962 /* From "ISA Binding to 1275"
963 * The ranges property is laid out as an array of elements,
964 * each of which comprises:
965 * cells 0 - 1: an ISA address
966 * cells 2 - 4: a PCI address
967 * (size depending on dev->n_addr_cells)
968 * cell 5: the size of the range
970 if ((range
->isa_addr
.a_hi
&& ISA_SPACE_MASK
) == ISA_SPACE_IO
) {
971 isa_addr
= range
->isa_addr
.a_lo
;
972 pci_addr
= (unsigned long) range
->pci_addr
.a_mid
<< 32 |
973 range
->pci_addr
.a_lo
;
975 /* Assume these are both zero */
976 if ((pci_addr
!= 0) || (isa_addr
!= 0)) {
977 printk(KERN_ERR
"unexpected isa to pci mapping: %s\n",
982 size
= PAGE_ALIGN(range
->size
);
984 __ioremap_explicit(phb_io_base_phys
,
985 (unsigned long) phb_io_base_virt
,
986 size
, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
990 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
991 struct device_node
*dev
, int prim
)
993 unsigned int *ranges
, pci_space
;
997 struct resource
*res
;
998 int np
, na
= prom_n_addr_cells(dev
);
999 unsigned long pci_addr
, cpu_phys_addr
;
1003 /* From "PCI Binding to 1275"
1004 * The ranges property is laid out as an array of elements,
1005 * each of which comprises:
1006 * cells 0 - 2: a PCI address
1007 * cells 3 or 3+4: a CPU physical address
1008 * (size depending on dev->n_addr_cells)
1009 * cells 4+5 or 5+6: the size of the range
1011 ranges
= (unsigned int *) get_property(dev
, "ranges", &rlen
);
1014 hose
->io_base_phys
= 0;
1015 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
1017 pci_space
= ranges
[0];
1018 pci_addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1020 cpu_phys_addr
= ranges
[3];
1022 cpu_phys_addr
= (cpu_phys_addr
<< 32) | ranges
[4];
1024 size
= ((unsigned long)ranges
[na
+3] << 32) | ranges
[na
+4];
1029 /* Now consume following elements while they are contiguous */
1030 while (rlen
>= np
* sizeof(unsigned int)) {
1031 unsigned long addr
, phys
;
1033 if (ranges
[0] != pci_space
)
1035 addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1038 phys
= (phys
<< 32) | ranges
[4];
1039 if (addr
!= pci_addr
+ size
||
1040 phys
!= cpu_phys_addr
+ size
)
1043 size
+= ((unsigned long)ranges
[na
+3] << 32)
1046 rlen
-= np
* sizeof(unsigned int);
1049 switch ((pci_space
>> 24) & 0x3) {
1050 case 1: /* I/O space */
1051 hose
->io_base_phys
= cpu_phys_addr
;
1052 hose
->pci_io_size
= size
;
1054 res
= &hose
->io_resource
;
1055 res
->flags
= IORESOURCE_IO
;
1056 res
->start
= pci_addr
;
1057 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
1058 res
->start
, res
->start
+ size
- 1);
1060 case 2: /* memory space */
1062 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
1066 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
1068 res
= &hose
->mem_resources
[memno
];
1069 res
->flags
= IORESOURCE_MEM
;
1070 res
->start
= cpu_phys_addr
;
1071 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
1072 res
->start
, res
->start
+ size
- 1);
1077 res
->name
= dev
->full_name
;
1078 res
->end
= res
->start
+ size
- 1;
1080 res
->sibling
= NULL
;
1086 void __init
pci_setup_phb_io(struct pci_controller
*hose
, int primary
)
1088 unsigned long size
= hose
->pci_io_size
;
1089 unsigned long io_virt_offset
;
1090 struct resource
*res
;
1091 struct device_node
*isa_dn
;
1093 hose
->io_base_virt
= reserve_phb_iospace(size
);
1094 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1095 hose
->global_number
, hose
->io_base_phys
,
1096 (unsigned long) hose
->io_base_virt
);
1099 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1100 isa_dn
= of_find_node_by_type(NULL
, "isa");
1102 isa_io_base
= pci_io_base
;
1103 pci_process_ISA_OF_ranges(isa_dn
, hose
->io_base_phys
,
1104 hose
->io_base_virt
);
1105 of_node_put(isa_dn
);
1111 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1112 res
= &hose
->io_resource
;
1113 res
->start
+= io_virt_offset
;
1114 res
->end
+= io_virt_offset
;
1117 void __devinit
pci_setup_phb_io_dynamic(struct pci_controller
*hose
,
1120 unsigned long size
= hose
->pci_io_size
;
1121 unsigned long io_virt_offset
;
1122 struct resource
*res
;
1124 hose
->io_base_virt
= __ioremap(hose
->io_base_phys
, size
,
1125 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
1126 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1127 hose
->global_number
, hose
->io_base_phys
,
1128 (unsigned long) hose
->io_base_virt
);
1131 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1133 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1134 res
= &hose
->io_resource
;
1135 res
->start
+= io_virt_offset
;
1136 res
->end
+= io_virt_offset
;
1140 static int get_bus_io_range(struct pci_bus
*bus
, unsigned long *start_phys
,
1141 unsigned long *start_virt
, unsigned long *size
)
1143 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1144 struct pci_bus_region region
;
1145 struct resource
*res
;
1148 res
= bus
->resource
[0];
1149 pcibios_resource_to_bus(bus
->self
, ®ion
, res
);
1150 *start_phys
= hose
->io_base_phys
+ region
.start
;
1151 *start_virt
= (unsigned long) hose
->io_base_virt
+
1153 if (region
.end
> region
.start
)
1154 *size
= region
.end
- region
.start
+ 1;
1156 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1157 __FUNCTION__
, region
.start
, region
.end
);
1163 res
= &hose
->io_resource
;
1164 *start_phys
= hose
->io_base_phys
;
1165 *start_virt
= (unsigned long) hose
->io_base_virt
;
1166 if (res
->end
> res
->start
)
1167 *size
= res
->end
- res
->start
+ 1;
1169 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1170 __FUNCTION__
, res
->start
, res
->end
);
1178 int unmap_bus_range(struct pci_bus
*bus
)
1180 unsigned long start_phys
;
1181 unsigned long start_virt
;
1185 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1189 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1191 if (iounmap_explicit((void __iomem
*) start_virt
, size
))
1196 EXPORT_SYMBOL(unmap_bus_range
);
1198 int remap_bus_range(struct pci_bus
*bus
)
1200 unsigned long start_phys
;
1201 unsigned long start_virt
;
1205 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1210 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1212 if (start_phys
== 0)
1214 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys
, start_virt
, size
);
1215 if (__ioremap_explicit(start_phys
, start_virt
, size
,
1216 _PAGE_NO_CACHE
| _PAGE_GUARDED
))
1221 EXPORT_SYMBOL(remap_bus_range
);
1223 static void phbs_remap_io(void)
1225 struct pci_controller
*hose
, *tmp
;
1227 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1228 remap_bus_range(hose
->bus
);
1231 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
1233 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1234 unsigned long start
, end
, mask
, offset
;
1236 if (res
->flags
& IORESOURCE_IO
) {
1237 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1239 start
= res
->start
+= offset
;
1240 end
= res
->end
+= offset
;
1242 /* Need to allow IO access to pages that are in the
1244 if (start
< MAX_ISA_PORT
) {
1245 if (end
> MAX_ISA_PORT
)
1248 start
>>= PAGE_SHIFT
;
1251 /* get the range of pages for the map */
1252 mask
= ((1 << (end
+1)) - 1) ^ ((1 << start
) - 1);
1253 io_page_mask
|= mask
;
1255 } else if (res
->flags
& IORESOURCE_MEM
) {
1256 res
->start
+= hose
->pci_mem_offset
;
1257 res
->end
+= hose
->pci_mem_offset
;
1261 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
1262 struct pci_bus
*bus
)
1264 /* Update device resources. */
1267 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1268 if (dev
->resource
[i
].flags
)
1269 fixup_resource(&dev
->resource
[i
], dev
);
1271 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
1274 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
1276 struct pci_dev
*dev
;
1278 ppc_md
.iommu_bus_setup(bus
);
1280 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1281 ppc_md
.iommu_dev_setup(dev
);
1283 if (ppc_md
.irq_bus_setup
)
1284 ppc_md
.irq_bus_setup(bus
);
1287 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1289 struct pci_dev
*dev
= bus
->self
;
1291 if (dev
&& pci_probe_only
&&
1292 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1293 /* This is a subordinate bridge */
1295 pci_read_bridge_bases(bus
);
1296 pcibios_fixup_device_resources(dev
, bus
);
1301 if (!pci_probe_only
)
1304 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1305 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1306 pcibios_fixup_device_resources(dev
, bus
);
1308 EXPORT_SYMBOL(pcibios_fixup_bus
);
1311 * Reads the interrupt pin to determine if interrupt is use by card.
1312 * If the interrupt is used, then gets the interrupt line from the
1313 * openfirmware and sets it in the pci_dev and pci_config line.
1315 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1318 struct device_node
*node
;
1320 pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &intpin
);
1324 node
= pci_device_to_OF_node(pci_dev
);
1328 if (node
->n_intrs
== 0)
1331 pci_dev
->irq
= node
->intrs
[0].line
;
1333 pci_write_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, pci_dev
->irq
);
1337 EXPORT_SYMBOL(pci_read_irq_line
);
1339 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1340 const struct resource
*rsrc
,
1341 u64
*start
, u64
*end
)
1343 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1344 unsigned long offset
= 0;
1349 if (rsrc
->flags
& IORESOURCE_IO
)
1350 offset
= pci_io_base
- (unsigned long)hose
->io_base_virt
+
1353 *start
= rsrc
->start
+ offset
;
1354 *end
= rsrc
->end
+ offset
;
1357 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
1362 struct pci_controller
*hose
, *tmp
;
1363 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1364 if (hose
->arch_data
== node
)
1366 node
= node
->parent
;
1371 #endif /* CONFIG_PPC_MULTIPLATFORM */
1373 unsigned long pci_address_to_pio(phys_addr_t address
)
1375 struct pci_controller
*hose
, *tmp
;
1377 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1378 if (address
>= hose
->io_base_phys
&&
1379 address
< (hose
->io_base_phys
+ hose
->pci_io_size
)) {
1380 unsigned long base
=
1381 (unsigned long)hose
->io_base_virt
- pci_io_base
;
1382 return base
+ (address
- hose
->io_base_phys
);
1385 return (unsigned int)-1;
1387 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
1390 #define IOBASE_BRIDGE_NUMBER 0
1391 #define IOBASE_MEMORY 1
1393 #define IOBASE_ISA_IO 3
1394 #define IOBASE_ISA_MEM 4
1396 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
1397 unsigned long in_devfn
)
1399 struct pci_controller
* hose
;
1400 struct list_head
*ln
;
1401 struct pci_bus
*bus
= NULL
;
1402 struct device_node
*hose_node
;
1404 /* Argh ! Please forgive me for that hack, but that's the
1405 * simplest way to get existing XFree to not lockup on some
1406 * G5 machines... So when something asks for bus 0 io base
1407 * (bus 0 is HT root), we return the AGP one instead.
1409 if (machine_is_compatible("MacRISC4"))
1413 /* That syscall isn't quite compatible with PCI domains, but it's
1414 * used on pre-domains setup. We return the first match
1417 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
1418 bus
= pci_bus_b(ln
);
1419 if (in_bus
>= bus
->number
&& in_bus
< (bus
->number
+ bus
->subordinate
))
1423 if (bus
== NULL
|| bus
->sysdata
== NULL
)
1426 hose_node
= (struct device_node
*)bus
->sysdata
;
1427 hose
= PCI_DN(hose_node
)->phb
;
1430 case IOBASE_BRIDGE_NUMBER
:
1431 return (long)hose
->first_busno
;
1433 return (long)hose
->pci_mem_offset
;
1435 return (long)hose
->io_base_phys
;
1437 return (long)isa_io_base
;
1438 case IOBASE_ISA_MEM
: