2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
37 #define DBG(fmt...) printk(fmt)
42 unsigned long pci_probe_only
= 1;
43 int pci_assign_all_buses
= 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask
;
51 EXPORT_SYMBOL(io_page_mask
);
53 #ifdef CONFIG_PPC_MULTIPLATFORM
54 static void fixup_resource(struct resource
*res
, struct pci_dev
*dev
);
55 static void do_bus_setup(struct pci_bus
*bus
);
56 static void phbs_remap_io(void);
59 /* pci_io_base -- the base address from which io bars are offsets.
60 * This is the lowest I/O base address (so bar values are always positive),
61 * and it *must* be the start of ISA space if an ISA bus exists because
62 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
63 * page is mapped and isa_io_limit prevents access to it.
65 unsigned long isa_io_base
; /* NULL if no ISA bus */
66 EXPORT_SYMBOL(isa_io_base
);
67 unsigned long pci_io_base
;
68 EXPORT_SYMBOL(pci_io_base
);
70 void iSeries_pcibios_init(void);
74 struct dma_mapping_ops pci_dma_ops
;
75 EXPORT_SYMBOL(pci_dma_ops
);
77 int global_phb_number
; /* Global phb counter */
79 /* Cached ISA bridge dev. */
80 struct pci_dev
*ppc64_isabridge_dev
= NULL
;
81 EXPORT_SYMBOL_GPL(ppc64_isabridge_dev
);
83 static void fixup_broken_pcnet32(struct pci_dev
* dev
)
85 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
86 dev
->vendor
= PCI_VENDOR_ID_AMD
;
87 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
90 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
92 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
95 unsigned long offset
= 0;
96 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
101 if (res
->flags
& IORESOURCE_IO
)
102 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
104 if (res
->flags
& IORESOURCE_MEM
)
105 offset
= hose
->pci_mem_offset
;
107 region
->start
= res
->start
- offset
;
108 region
->end
= res
->end
- offset
;
111 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
112 struct pci_bus_region
*region
)
114 unsigned long offset
= 0;
115 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
120 if (res
->flags
& IORESOURCE_IO
)
121 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
123 if (res
->flags
& IORESOURCE_MEM
)
124 offset
= hose
->pci_mem_offset
;
126 res
->start
= region
->start
+ offset
;
127 res
->end
= region
->end
+ offset
;
130 #ifdef CONFIG_HOTPLUG
131 EXPORT_SYMBOL(pcibios_resource_to_bus
);
132 EXPORT_SYMBOL(pcibios_bus_to_resource
);
136 * We need to avoid collisions with `mirrored' VGA ports
137 * and other strange ISA hardware, so we always want the
138 * addresses to be allocated in the 0x000-0x0ff region
141 * Why? Because some silly external IO cards only decode
142 * the low 10 bits of the IO address. The 0x00-0xff region
143 * is reserved for motherboard devices that decode all 16
144 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
145 * but we want to try to avoid allocating at 0x2900-0x2bff
146 * which might have be mirrored at 0x0100-0x03ff..
148 void pcibios_align_resource(void *data
, struct resource
*res
,
149 unsigned long size
, unsigned long align
)
151 struct pci_dev
*dev
= data
;
152 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
153 unsigned long start
= res
->start
;
154 unsigned long alignto
;
156 if (res
->flags
& IORESOURCE_IO
) {
157 unsigned long offset
= (unsigned long)hose
->io_base_virt
-
159 /* Make sure we start at our min on all hoses */
160 if (start
- offset
< PCIBIOS_MIN_IO
)
161 start
= PCIBIOS_MIN_IO
+ offset
;
164 * Put everything into 0x00-0xff region modulo 0x400
167 start
= (start
+ 0x3ff) & ~0x3ff;
169 } else if (res
->flags
& IORESOURCE_MEM
) {
170 /* Make sure we start at our min on all hoses */
171 if (start
- hose
->pci_mem_offset
< PCIBIOS_MIN_MEM
)
172 start
= PCIBIOS_MIN_MEM
+ hose
->pci_mem_offset
;
174 /* Align to multiple of size of minimum base. */
175 alignto
= max(0x1000UL
, align
);
176 start
= ALIGN(start
, alignto
);
182 static DEFINE_SPINLOCK(hose_spinlock
);
185 * pci_controller(phb) initialized common variables.
187 static void __devinit
pci_setup_pci_controller(struct pci_controller
*hose
)
189 memset(hose
, 0, sizeof(struct pci_controller
));
191 spin_lock(&hose_spinlock
);
192 hose
->global_number
= global_phb_number
++;
193 list_add_tail(&hose
->list_node
, &hose_list
);
194 spin_unlock(&hose_spinlock
);
197 static void add_linux_pci_domain(struct device_node
*dev
,
198 struct pci_controller
*phb
)
200 struct property
*of_prop
;
203 of_prop
= (struct property
*)
204 get_property(dev
, "linux,pci-domain", &size
);
207 WARN_ON(of_prop
&& size
< sizeof(int));
208 if (of_prop
&& size
< sizeof(int))
210 size
= sizeof(struct property
) + sizeof(int);
211 if (of_prop
== NULL
) {
213 of_prop
= kmalloc(size
, GFP_KERNEL
);
215 of_prop
= alloc_bootmem(size
);
217 memset(of_prop
, 0, sizeof(struct property
));
218 of_prop
->name
= "linux,pci-domain";
219 of_prop
->length
= sizeof(int);
220 of_prop
->value
= (unsigned char *)&of_prop
[1];
221 *((int *)of_prop
->value
) = phb
->global_number
;
222 prom_add_property(dev
, of_prop
);
225 struct pci_controller
* pcibios_alloc_controller(struct device_node
*dev
)
227 struct pci_controller
*phb
;
230 phb
= kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
232 phb
= alloc_bootmem(sizeof (struct pci_controller
));
235 pci_setup_pci_controller(phb
);
236 phb
->arch_data
= dev
;
237 phb
->is_dynamic
= mem_init_done
;
239 add_linux_pci_domain(dev
, phb
);
243 void pcibios_free_controller(struct pci_controller
*phb
)
245 if (phb
->arch_data
) {
246 struct device_node
*np
= phb
->arch_data
;
247 int *domain
= (int *)get_property(np
,
248 "linux,pci-domain", NULL
);
256 #ifndef CONFIG_PPC_ISERIES
257 void __devinit
pcibios_claim_one_bus(struct pci_bus
*b
)
260 struct pci_bus
*child_bus
;
262 list_for_each_entry(dev
, &b
->devices
, bus_list
) {
265 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
266 struct resource
*r
= &dev
->resource
[i
];
268 if (r
->parent
|| !r
->start
|| !r
->flags
)
270 pci_claim_resource(dev
, i
);
274 list_for_each_entry(child_bus
, &b
->children
, node
)
275 pcibios_claim_one_bus(child_bus
);
277 #ifdef CONFIG_HOTPLUG
278 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
281 static void __init
pcibios_claim_of_setup(void)
285 list_for_each_entry(b
, &pci_root_buses
, node
)
286 pcibios_claim_one_bus(b
);
290 #ifdef CONFIG_PPC_MULTIPLATFORM
291 static u32
get_int_prop(struct device_node
*np
, const char *name
, u32 def
)
296 prop
= (u32
*) get_property(np
, name
, &len
);
297 if (prop
&& len
>= 4)
302 static unsigned int pci_parse_of_flags(u32 addr0
)
304 unsigned int flags
= 0;
306 if (addr0
& 0x02000000) {
307 flags
= IORESOURCE_MEM
| PCI_BASE_ADDRESS_SPACE_MEMORY
;
308 flags
|= (addr0
>> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64
;
309 flags
|= (addr0
>> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M
;
310 if (addr0
& 0x40000000)
311 flags
|= IORESOURCE_PREFETCH
312 | PCI_BASE_ADDRESS_MEM_PREFETCH
;
313 } else if (addr0
& 0x01000000)
314 flags
= IORESOURCE_IO
| PCI_BASE_ADDRESS_SPACE_IO
;
318 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
320 static void pci_parse_of_addrs(struct device_node
*node
, struct pci_dev
*dev
)
324 struct resource
*res
;
328 addrs
= (u32
*) get_property(node
, "assigned-addresses", &proplen
);
331 DBG(" parse addresses (%d bytes) @ %p\n", proplen
, addrs
);
332 for (; proplen
>= 20; proplen
-= 20, addrs
+= 5) {
333 flags
= pci_parse_of_flags(addrs
[0]);
336 base
= GET_64BIT(addrs
, 1);
337 size
= GET_64BIT(addrs
, 3);
341 DBG(" base: %llx, size: %llx, i: %x\n",
342 (unsigned long long)base
, (unsigned long long)size
, i
);
344 if (PCI_BASE_ADDRESS_0
<= i
&& i
<= PCI_BASE_ADDRESS_5
) {
345 res
= &dev
->resource
[(i
- PCI_BASE_ADDRESS_0
) >> 2];
346 } else if (i
== dev
->rom_base_reg
) {
347 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
348 flags
|= IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
350 printk(KERN_ERR
"PCI: bad cfg reg num 0x%x\n", i
);
354 res
->end
= base
+ size
- 1;
356 res
->name
= pci_name(dev
);
357 fixup_resource(res
, dev
);
361 struct pci_dev
*of_create_pci_dev(struct device_node
*node
,
362 struct pci_bus
*bus
, int devfn
)
367 dev
= kmalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
370 type
= get_property(node
, "device_type", NULL
);
374 DBG(" create device, devfn: %x, type: %s\n", devfn
, type
);
376 memset(dev
, 0, sizeof(struct pci_dev
));
379 dev
->dev
.parent
= bus
->bridge
;
380 dev
->dev
.bus
= &pci_bus_type
;
382 dev
->multifunction
= 0; /* maybe a lie? */
384 dev
->vendor
= get_int_prop(node
, "vendor-id", 0xffff);
385 dev
->device
= get_int_prop(node
, "device-id", 0xffff);
386 dev
->subsystem_vendor
= get_int_prop(node
, "subsystem-vendor-id", 0);
387 dev
->subsystem_device
= get_int_prop(node
, "subsystem-id", 0);
389 dev
->cfg_size
= pci_cfg_space_size(dev
);
391 sprintf(pci_name(dev
), "%04x:%02x:%02x.%d", pci_domain_nr(bus
),
392 dev
->bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
393 dev
->class = get_int_prop(node
, "class-code", 0);
395 DBG(" class: 0x%x\n", dev
->class);
397 dev
->current_state
= 4; /* unknown power state */
399 if (!strcmp(type
, "pci")) {
400 /* a PCI-PCI bridge */
401 dev
->hdr_type
= PCI_HEADER_TYPE_BRIDGE
;
402 dev
->rom_base_reg
= PCI_ROM_ADDRESS1
;
403 } else if (!strcmp(type
, "cardbus")) {
404 dev
->hdr_type
= PCI_HEADER_TYPE_CARDBUS
;
406 dev
->hdr_type
= PCI_HEADER_TYPE_NORMAL
;
407 dev
->rom_base_reg
= PCI_ROM_ADDRESS
;
409 if (node
->n_intrs
> 0) {
410 dev
->irq
= node
->intrs
[0].line
;
411 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
,
416 pci_parse_of_addrs(node
, dev
);
418 DBG(" adding to system ...\n");
420 pci_device_add(dev
, bus
);
422 /* XXX pci_scan_msi_device(dev); */
426 EXPORT_SYMBOL(of_create_pci_dev
);
428 void __devinit
of_scan_bus(struct device_node
*node
,
431 struct device_node
*child
= NULL
;
436 DBG("of_scan_bus(%s) bus no %d... \n", node
->full_name
, bus
->number
);
438 while ((child
= of_get_next_child(node
, child
)) != NULL
) {
439 DBG(" * %s\n", child
->full_name
);
440 reg
= (u32
*) get_property(child
, "reg", ®len
);
441 if (reg
== NULL
|| reglen
< 20)
443 devfn
= (reg
[0] >> 8) & 0xff;
445 /* create a new pci_dev for this device */
446 dev
= of_create_pci_dev(child
, bus
, devfn
);
449 DBG("dev header type: %x\n", dev
->hdr_type
);
451 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
452 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
453 of_scan_pci_bridge(child
, dev
);
458 EXPORT_SYMBOL(of_scan_bus
);
460 void __devinit
of_scan_pci_bridge(struct device_node
*node
,
464 u32
*busrange
, *ranges
;
466 struct resource
*res
;
470 DBG("of_scan_pci_bridge(%s)\n", node
->full_name
);
472 /* parse bus-range property */
473 busrange
= (u32
*) get_property(node
, "bus-range", &len
);
474 if (busrange
== NULL
|| len
!= 8) {
475 printk(KERN_DEBUG
"Can't get bus-range for PCI-PCI bridge %s\n",
479 ranges
= (u32
*) get_property(node
, "ranges", &len
);
480 if (ranges
== NULL
) {
481 printk(KERN_DEBUG
"Can't get ranges for PCI-PCI bridge %s\n",
486 bus
= pci_add_new_bus(dev
->bus
, dev
, busrange
[0]);
488 printk(KERN_ERR
"Failed to create pci bus for %s\n",
493 bus
->primary
= dev
->bus
->number
;
494 bus
->subordinate
= busrange
[1];
498 /* parse ranges property */
499 /* PCI #address-cells == 3 and #size-cells == 2 always */
500 res
= &dev
->resource
[PCI_BRIDGE_RESOURCES
];
501 for (i
= 0; i
< PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
; ++i
) {
503 bus
->resource
[i
] = res
;
507 for (; len
>= 32; len
-= 32, ranges
+= 8) {
508 flags
= pci_parse_of_flags(ranges
[0]);
509 size
= GET_64BIT(ranges
, 6);
510 if (flags
== 0 || size
== 0)
512 if (flags
& IORESOURCE_IO
) {
513 res
= bus
->resource
[0];
515 printk(KERN_ERR
"PCI: ignoring extra I/O range"
516 " for bridge %s\n", node
->full_name
);
520 if (i
>= PCI_NUM_RESOURCES
- PCI_BRIDGE_RESOURCES
) {
521 printk(KERN_ERR
"PCI: too many memory ranges"
522 " for bridge %s\n", node
->full_name
);
525 res
= bus
->resource
[i
];
528 res
->start
= GET_64BIT(ranges
, 1);
529 res
->end
= res
->start
+ size
- 1;
531 fixup_resource(res
, dev
);
533 sprintf(bus
->name
, "PCI Bus %04x:%02x", pci_domain_nr(bus
),
535 DBG(" bus name: %s\n", bus
->name
);
537 mode
= PCI_PROBE_NORMAL
;
538 if (ppc_md
.pci_probe_mode
)
539 mode
= ppc_md
.pci_probe_mode(bus
);
540 DBG(" probe mode: %d\n", mode
);
542 if (mode
== PCI_PROBE_DEVTREE
)
543 of_scan_bus(node
, bus
);
544 else if (mode
== PCI_PROBE_NORMAL
)
545 pci_scan_child_bus(bus
);
547 EXPORT_SYMBOL(of_scan_pci_bridge
);
548 #endif /* CONFIG_PPC_MULTIPLATFORM */
550 void __devinit
scan_phb(struct pci_controller
*hose
)
553 struct device_node
*node
= hose
->arch_data
;
555 struct resource
*res
;
557 DBG("Scanning PHB %s\n", node
? node
->full_name
: "<NO NAME>");
559 bus
= pci_create_bus(NULL
, hose
->first_busno
, hose
->ops
, node
);
561 printk(KERN_ERR
"Failed to create bus for PCI domain %04x\n",
562 hose
->global_number
);
565 bus
->secondary
= hose
->first_busno
;
568 bus
->resource
[0] = res
= &hose
->io_resource
;
569 if (res
->flags
&& request_resource(&ioport_resource
, res
))
570 printk(KERN_ERR
"Failed to request PCI IO region "
571 "on PCI domain %04x\n", hose
->global_number
);
573 for (i
= 0; i
< 3; ++i
) {
574 res
= &hose
->mem_resources
[i
];
575 bus
->resource
[i
+1] = res
;
576 if (res
->flags
&& request_resource(&iomem_resource
, res
))
577 printk(KERN_ERR
"Failed to request PCI memory region "
578 "on PCI domain %04x\n", hose
->global_number
);
581 mode
= PCI_PROBE_NORMAL
;
582 #ifdef CONFIG_PPC_MULTIPLATFORM
583 if (node
&& ppc_md
.pci_probe_mode
)
584 mode
= ppc_md
.pci_probe_mode(bus
);
585 DBG(" probe mode: %d\n", mode
);
586 if (mode
== PCI_PROBE_DEVTREE
) {
587 bus
->subordinate
= hose
->last_busno
;
588 of_scan_bus(node
, bus
);
590 #endif /* CONFIG_PPC_MULTIPLATFORM */
591 if (mode
== PCI_PROBE_NORMAL
)
592 hose
->last_busno
= bus
->subordinate
= pci_scan_child_bus(bus
);
595 static int __init
pcibios_init(void)
597 struct pci_controller
*hose
, *tmp
;
599 /* For now, override phys_mem_access_prot. If we need it,
600 * later, we may move that initialization to each ppc_md
602 ppc_md
.phys_mem_access_prot
= pci_phys_mem_access_prot
;
604 #ifdef CONFIG_PPC_ISERIES
605 iSeries_pcibios_init();
608 printk("PCI: Probing PCI hardware\n");
610 /* Scan all of the recorded PCI controllers. */
611 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
613 pci_bus_add_devices(hose
->bus
);
616 #ifndef CONFIG_PPC_ISERIES
618 pcibios_claim_of_setup();
620 /* FIXME: `else' will be removed when
621 pci_assign_unassigned_resources() is able to work
622 correctly with [partially] allocated PCI tree. */
623 pci_assign_unassigned_resources();
624 #endif /* !CONFIG_PPC_ISERIES */
626 /* Call machine dependent final fixup */
627 if (ppc_md
.pcibios_fixup
)
628 ppc_md
.pcibios_fixup();
630 /* Cache the location of the ISA bridge (if we have one) */
631 ppc64_isabridge_dev
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
632 if (ppc64_isabridge_dev
!= NULL
)
633 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev
));
635 #ifdef CONFIG_PPC_MULTIPLATFORM
636 /* map in PCI I/O space */
640 printk("PCI: Probing PCI hardware done\n");
645 subsys_initcall(pcibios_init
);
647 char __init
*pcibios_setup(char *str
)
652 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
657 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
660 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
661 struct resource
*res
= &dev
->resource
[i
];
663 /* Only set up the requested stuff */
664 if (!(mask
& (1<<i
)))
667 if (res
->flags
& IORESOURCE_IO
)
668 cmd
|= PCI_COMMAND_IO
;
669 if (res
->flags
& IORESOURCE_MEM
)
670 cmd
|= PCI_COMMAND_MEMORY
;
674 printk(KERN_DEBUG
"PCI: Enabling device: (%s), cmd %x\n",
676 /* Enable the appropriate bits in the PCI command register. */
677 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
683 * Return the domain number for this bus.
685 int pci_domain_nr(struct pci_bus
*bus
)
687 #ifdef CONFIG_PPC_ISERIES
690 struct pci_controller
*hose
= pci_bus_to_host(bus
);
692 return hose
->global_number
;
696 EXPORT_SYMBOL(pci_domain_nr
);
698 /* Decide whether to display the domain number in /proc */
699 int pci_proc_domain(struct pci_bus
*bus
)
701 #ifdef CONFIG_PPC_ISERIES
704 struct pci_controller
*hose
= pci_bus_to_host(bus
);
710 * Platform support for /proc/bus/pci/X/Y mmap()s,
711 * modelled on the sparc64 implementation by Dave Miller.
716 * Adjust vm_pgoff of VMA such that it is the physical page offset
717 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
719 * Basically, the user finds the base address for his device which he wishes
720 * to mmap. They read the 32-bit value from the config space base register,
721 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
722 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
724 * Returns negative error code on failure, zero on success.
726 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
727 unsigned long *offset
,
728 enum pci_mmap_state mmap_state
)
730 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
731 unsigned long io_offset
= 0;
735 return NULL
; /* should never happen */
737 /* If memory, add on the PCI bridge address offset */
738 if (mmap_state
== pci_mmap_mem
) {
739 *offset
+= hose
->pci_mem_offset
;
740 res_bit
= IORESOURCE_MEM
;
742 io_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
743 *offset
+= io_offset
;
744 res_bit
= IORESOURCE_IO
;
748 * Check that the offset requested corresponds to one of the
749 * resources of the device.
751 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
752 struct resource
*rp
= &dev
->resource
[i
];
753 int flags
= rp
->flags
;
755 /* treat ROM as memory (should be already) */
756 if (i
== PCI_ROM_RESOURCE
)
757 flags
|= IORESOURCE_MEM
;
759 /* Active and same type? */
760 if ((flags
& res_bit
) == 0)
763 /* In the range of this resource? */
764 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
767 /* found it! construct the final physical address */
768 if (mmap_state
== pci_mmap_io
)
769 *offset
+= hose
->io_base_phys
- io_offset
;
777 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
780 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
782 enum pci_mmap_state mmap_state
,
785 unsigned long prot
= pgprot_val(protection
);
787 /* Write combine is always 0 on non-memory space mappings. On
788 * memory space, if the user didn't pass 1, we check for a
789 * "prefetchable" resource. This is a bit hackish, but we use
790 * this to workaround the inability of /sysfs to provide a write
793 if (mmap_state
!= pci_mmap_mem
)
795 else if (write_combine
== 0) {
796 if (rp
->flags
& IORESOURCE_PREFETCH
)
800 /* XXX would be nice to have a way to ask for write-through */
801 prot
|= _PAGE_NO_CACHE
;
803 prot
&= ~_PAGE_GUARDED
;
805 prot
|= _PAGE_GUARDED
;
807 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev
), rp
->start
,
810 return __pgprot(prot
);
814 * This one is used by /dev/mem and fbdev who have no clue about the
815 * PCI device, it tries to find the PCI device first and calls the
818 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
823 struct pci_dev
*pdev
= NULL
;
824 struct resource
*found
= NULL
;
825 unsigned long prot
= pgprot_val(protection
);
826 unsigned long offset
= pfn
<< PAGE_SHIFT
;
829 if (page_is_ram(pfn
))
830 return __pgprot(prot
);
832 prot
|= _PAGE_NO_CACHE
| _PAGE_GUARDED
;
834 for_each_pci_dev(pdev
) {
835 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
836 struct resource
*rp
= &pdev
->resource
[i
];
837 int flags
= rp
->flags
;
839 /* Active and same type? */
840 if ((flags
& IORESOURCE_MEM
) == 0)
842 /* In the range of this resource? */
843 if (offset
< (rp
->start
& PAGE_MASK
) ||
853 if (found
->flags
& IORESOURCE_PREFETCH
)
854 prot
&= ~_PAGE_GUARDED
;
858 DBG("non-PCI map for %lx, prot: %lx\n", offset
, prot
);
860 return __pgprot(prot
);
865 * Perform the actual remap of the pages for a PCI device mapping, as
866 * appropriate for this architecture. The region in the process to map
867 * is described by vm_start and vm_end members of VMA, the base physical
868 * address is found in vm_pgoff.
869 * The pci device structure is provided so that architectures may make mapping
870 * decisions on a per-device or per-bus basis.
872 * Returns a negative error code on failure, zero on success.
874 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
875 enum pci_mmap_state mmap_state
, int write_combine
)
877 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
881 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
885 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
886 vma
->vm_flags
|= VM_SHM
| VM_LOCKED
| VM_IO
;
887 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
889 mmap_state
, write_combine
);
891 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
892 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
897 #ifdef CONFIG_PPC_MULTIPLATFORM
898 static ssize_t
pci_show_devspec(struct device
*dev
, struct device_attribute
*attr
, char *buf
)
900 struct pci_dev
*pdev
;
901 struct device_node
*np
;
903 pdev
= to_pci_dev (dev
);
904 np
= pci_device_to_OF_node(pdev
);
905 if (np
== NULL
|| np
->full_name
== NULL
)
907 return sprintf(buf
, "%s", np
->full_name
);
909 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
910 #endif /* CONFIG_PPC_MULTIPLATFORM */
912 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
914 #ifdef CONFIG_PPC_MULTIPLATFORM
915 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
916 #endif /* CONFIG_PPC_MULTIPLATFORM */
919 #ifdef CONFIG_PPC_MULTIPLATFORM
921 #define ISA_SPACE_MASK 0x1
922 #define ISA_SPACE_IO 0x1
924 static void __devinit
pci_process_ISA_OF_ranges(struct device_node
*isa_node
,
925 unsigned long phb_io_base_phys
,
926 void __iomem
* phb_io_base_virt
)
928 /* Remove these asap */
942 struct isa_address isa_addr
;
943 struct pci_address pci_addr
;
947 struct isa_range
*range
;
948 unsigned long pci_addr
;
949 unsigned int isa_addr
;
953 range
= (struct isa_range
*) get_property(isa_node
, "ranges", &rlen
);
954 if (range
== NULL
|| (rlen
< sizeof(struct isa_range
))) {
955 printk(KERN_ERR
"no ISA ranges or unexpected isa range size,"
957 __ioremap_explicit(phb_io_base_phys
,
958 (unsigned long)phb_io_base_virt
,
959 0x10000, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
963 /* From "ISA Binding to 1275"
964 * The ranges property is laid out as an array of elements,
965 * each of which comprises:
966 * cells 0 - 1: an ISA address
967 * cells 2 - 4: a PCI address
968 * (size depending on dev->n_addr_cells)
969 * cell 5: the size of the range
971 if ((range
->isa_addr
.a_hi
&& ISA_SPACE_MASK
) == ISA_SPACE_IO
) {
972 isa_addr
= range
->isa_addr
.a_lo
;
973 pci_addr
= (unsigned long) range
->pci_addr
.a_mid
<< 32 |
974 range
->pci_addr
.a_lo
;
976 /* Assume these are both zero */
977 if ((pci_addr
!= 0) || (isa_addr
!= 0)) {
978 printk(KERN_ERR
"unexpected isa to pci mapping: %s\n",
983 size
= PAGE_ALIGN(range
->size
);
985 __ioremap_explicit(phb_io_base_phys
,
986 (unsigned long) phb_io_base_virt
,
987 size
, _PAGE_NO_CACHE
| _PAGE_GUARDED
);
991 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
992 struct device_node
*dev
, int prim
)
994 unsigned int *ranges
, pci_space
;
998 struct resource
*res
;
999 int np
, na
= prom_n_addr_cells(dev
);
1000 unsigned long pci_addr
, cpu_phys_addr
;
1004 /* From "PCI Binding to 1275"
1005 * The ranges property is laid out as an array of elements,
1006 * each of which comprises:
1007 * cells 0 - 2: a PCI address
1008 * cells 3 or 3+4: a CPU physical address
1009 * (size depending on dev->n_addr_cells)
1010 * cells 4+5 or 5+6: the size of the range
1012 ranges
= (unsigned int *) get_property(dev
, "ranges", &rlen
);
1015 hose
->io_base_phys
= 0;
1016 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
1018 pci_space
= ranges
[0];
1019 pci_addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1021 cpu_phys_addr
= ranges
[3];
1023 cpu_phys_addr
= (cpu_phys_addr
<< 32) | ranges
[4];
1025 size
= ((unsigned long)ranges
[na
+3] << 32) | ranges
[na
+4];
1030 /* Now consume following elements while they are contiguous */
1031 while (rlen
>= np
* sizeof(unsigned int)) {
1032 unsigned long addr
, phys
;
1034 if (ranges
[0] != pci_space
)
1036 addr
= ((unsigned long)ranges
[1] << 32) | ranges
[2];
1039 phys
= (phys
<< 32) | ranges
[4];
1040 if (addr
!= pci_addr
+ size
||
1041 phys
!= cpu_phys_addr
+ size
)
1044 size
+= ((unsigned long)ranges
[na
+3] << 32)
1047 rlen
-= np
* sizeof(unsigned int);
1050 switch ((pci_space
>> 24) & 0x3) {
1051 case 1: /* I/O space */
1052 hose
->io_base_phys
= cpu_phys_addr
;
1053 hose
->pci_io_size
= size
;
1055 res
= &hose
->io_resource
;
1056 res
->flags
= IORESOURCE_IO
;
1057 res
->start
= pci_addr
;
1058 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose
->global_number
,
1059 res
->start
, res
->start
+ size
- 1);
1061 case 2: /* memory space */
1063 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
1067 hose
->pci_mem_offset
= cpu_phys_addr
- pci_addr
;
1069 res
= &hose
->mem_resources
[memno
];
1070 res
->flags
= IORESOURCE_MEM
;
1071 res
->start
= cpu_phys_addr
;
1072 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose
->global_number
,
1073 res
->start
, res
->start
+ size
- 1);
1078 res
->name
= dev
->full_name
;
1079 res
->end
= res
->start
+ size
- 1;
1081 res
->sibling
= NULL
;
1087 void __init
pci_setup_phb_io(struct pci_controller
*hose
, int primary
)
1089 unsigned long size
= hose
->pci_io_size
;
1090 unsigned long io_virt_offset
;
1091 struct resource
*res
;
1092 struct device_node
*isa_dn
;
1094 hose
->io_base_virt
= reserve_phb_iospace(size
);
1095 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1096 hose
->global_number
, hose
->io_base_phys
,
1097 (unsigned long) hose
->io_base_virt
);
1100 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1101 isa_dn
= of_find_node_by_type(NULL
, "isa");
1103 isa_io_base
= pci_io_base
;
1104 pci_process_ISA_OF_ranges(isa_dn
, hose
->io_base_phys
,
1105 hose
->io_base_virt
);
1106 of_node_put(isa_dn
);
1112 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1113 res
= &hose
->io_resource
;
1114 res
->start
+= io_virt_offset
;
1115 res
->end
+= io_virt_offset
;
1118 void __devinit
pci_setup_phb_io_dynamic(struct pci_controller
*hose
,
1121 unsigned long size
= hose
->pci_io_size
;
1122 unsigned long io_virt_offset
;
1123 struct resource
*res
;
1125 hose
->io_base_virt
= __ioremap(hose
->io_base_phys
, size
,
1126 _PAGE_NO_CACHE
| _PAGE_GUARDED
);
1127 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1128 hose
->global_number
, hose
->io_base_phys
,
1129 (unsigned long) hose
->io_base_virt
);
1132 pci_io_base
= (unsigned long)hose
->io_base_virt
;
1134 io_virt_offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1135 res
= &hose
->io_resource
;
1136 res
->start
+= io_virt_offset
;
1137 res
->end
+= io_virt_offset
;
1141 static int get_bus_io_range(struct pci_bus
*bus
, unsigned long *start_phys
,
1142 unsigned long *start_virt
, unsigned long *size
)
1144 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1145 struct pci_bus_region region
;
1146 struct resource
*res
;
1149 res
= bus
->resource
[0];
1150 pcibios_resource_to_bus(bus
->self
, ®ion
, res
);
1151 *start_phys
= hose
->io_base_phys
+ region
.start
;
1152 *start_virt
= (unsigned long) hose
->io_base_virt
+
1154 if (region
.end
> region
.start
)
1155 *size
= region
.end
- region
.start
+ 1;
1157 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1158 __FUNCTION__
, region
.start
, region
.end
);
1164 res
= &hose
->io_resource
;
1165 *start_phys
= hose
->io_base_phys
;
1166 *start_virt
= (unsigned long) hose
->io_base_virt
;
1167 if (res
->end
> res
->start
)
1168 *size
= res
->end
- res
->start
+ 1;
1170 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1171 __FUNCTION__
, res
->start
, res
->end
);
1179 int unmap_bus_range(struct pci_bus
*bus
)
1181 unsigned long start_phys
;
1182 unsigned long start_virt
;
1186 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1190 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1192 if (iounmap_explicit((void __iomem
*) start_virt
, size
))
1197 EXPORT_SYMBOL(unmap_bus_range
);
1199 int remap_bus_range(struct pci_bus
*bus
)
1201 unsigned long start_phys
;
1202 unsigned long start_virt
;
1206 printk(KERN_ERR
"%s() expected bus\n", __FUNCTION__
);
1211 if (get_bus_io_range(bus
, &start_phys
, &start_virt
, &size
))
1213 if (start_phys
== 0)
1215 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys
, start_virt
, size
);
1216 if (__ioremap_explicit(start_phys
, start_virt
, size
,
1217 _PAGE_NO_CACHE
| _PAGE_GUARDED
))
1222 EXPORT_SYMBOL(remap_bus_range
);
1224 static void phbs_remap_io(void)
1226 struct pci_controller
*hose
, *tmp
;
1228 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1229 remap_bus_range(hose
->bus
);
1232 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
1234 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1235 unsigned long start
, end
, mask
, offset
;
1237 if (res
->flags
& IORESOURCE_IO
) {
1238 offset
= (unsigned long)hose
->io_base_virt
- pci_io_base
;
1240 start
= res
->start
+= offset
;
1241 end
= res
->end
+= offset
;
1243 /* Need to allow IO access to pages that are in the
1245 if (start
< MAX_ISA_PORT
) {
1246 if (end
> MAX_ISA_PORT
)
1249 start
>>= PAGE_SHIFT
;
1252 /* get the range of pages for the map */
1253 mask
= ((1 << (end
+1)) - 1) ^ ((1 << start
) - 1);
1254 io_page_mask
|= mask
;
1256 } else if (res
->flags
& IORESOURCE_MEM
) {
1257 res
->start
+= hose
->pci_mem_offset
;
1258 res
->end
+= hose
->pci_mem_offset
;
1262 void __devinit
pcibios_fixup_device_resources(struct pci_dev
*dev
,
1263 struct pci_bus
*bus
)
1265 /* Update device resources. */
1268 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1269 if (dev
->resource
[i
].flags
)
1270 fixup_resource(&dev
->resource
[i
], dev
);
1272 EXPORT_SYMBOL(pcibios_fixup_device_resources
);
1275 static void __devinit
do_bus_setup(struct pci_bus
*bus
)
1277 struct pci_dev
*dev
;
1279 ppc_md
.iommu_bus_setup(bus
);
1281 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1282 ppc_md
.iommu_dev_setup(dev
);
1284 if (ppc_md
.irq_bus_setup
)
1285 ppc_md
.irq_bus_setup(bus
);
1288 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1290 struct pci_dev
*dev
= bus
->self
;
1292 if (dev
&& pci_probe_only
&&
1293 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1294 /* This is a subordinate bridge */
1296 pci_read_bridge_bases(bus
);
1297 pcibios_fixup_device_resources(dev
, bus
);
1302 if (!pci_probe_only
)
1305 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1306 if ((dev
->class >> 8) != PCI_CLASS_BRIDGE_PCI
)
1307 pcibios_fixup_device_resources(dev
, bus
);
1309 EXPORT_SYMBOL(pcibios_fixup_bus
);
1312 * Reads the interrupt pin to determine if interrupt is use by card.
1313 * If the interrupt is used, then gets the interrupt line from the
1314 * openfirmware and sets it in the pci_dev and pci_config line.
1316 int pci_read_irq_line(struct pci_dev
*pci_dev
)
1319 struct device_node
*node
;
1321 pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &intpin
);
1325 node
= pci_device_to_OF_node(pci_dev
);
1329 if (node
->n_intrs
== 0)
1332 pci_dev
->irq
= node
->intrs
[0].line
;
1334 pci_write_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, pci_dev
->irq
);
1338 EXPORT_SYMBOL(pci_read_irq_line
);
1340 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
1341 const struct resource
*rsrc
,
1342 u64
*start
, u64
*end
)
1344 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1345 unsigned long offset
= 0;
1350 if (rsrc
->flags
& IORESOURCE_IO
)
1351 offset
= pci_io_base
- (unsigned long)hose
->io_base_virt
+
1354 *start
= rsrc
->start
+ offset
;
1355 *end
= rsrc
->end
+ offset
;
1358 struct pci_controller
* pci_find_hose_for_OF_device(struct device_node
* node
)
1363 struct pci_controller
*hose
, *tmp
;
1364 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1365 if (hose
->arch_data
== node
)
1367 node
= node
->parent
;
1372 #endif /* CONFIG_PPC_MULTIPLATFORM */
1374 unsigned long pci_address_to_pio(phys_addr_t address
)
1376 struct pci_controller
*hose
, *tmp
;
1378 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1379 if (address
>= hose
->io_base_phys
&&
1380 address
< (hose
->io_base_phys
+ hose
->pci_io_size
)) {
1381 unsigned long base
=
1382 (unsigned long)hose
->io_base_virt
- pci_io_base
;
1383 return base
+ (address
- hose
->io_base_phys
);
1386 return (unsigned int)-1;
1388 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
1391 #define IOBASE_BRIDGE_NUMBER 0
1392 #define IOBASE_MEMORY 1
1394 #define IOBASE_ISA_IO 3
1395 #define IOBASE_ISA_MEM 4
1397 long sys_pciconfig_iobase(long which
, unsigned long in_bus
,
1398 unsigned long in_devfn
)
1400 struct pci_controller
* hose
;
1401 struct list_head
*ln
;
1402 struct pci_bus
*bus
= NULL
;
1403 struct device_node
*hose_node
;
1405 /* Argh ! Please forgive me for that hack, but that's the
1406 * simplest way to get existing XFree to not lockup on some
1407 * G5 machines... So when something asks for bus 0 io base
1408 * (bus 0 is HT root), we return the AGP one instead.
1410 if (machine_is_compatible("MacRISC4"))
1414 /* That syscall isn't quite compatible with PCI domains, but it's
1415 * used on pre-domains setup. We return the first match
1418 for (ln
= pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
= ln
->next
) {
1419 bus
= pci_bus_b(ln
);
1420 if (in_bus
>= bus
->number
&& in_bus
< (bus
->number
+ bus
->subordinate
))
1424 if (bus
== NULL
|| bus
->sysdata
== NULL
)
1427 hose_node
= (struct device_node
*)bus
->sysdata
;
1428 hose
= PCI_DN(hose_node
)->phb
;
1431 case IOBASE_BRIDGE_NUMBER
:
1432 return (long)hose
->first_busno
;
1434 return (long)hose
->pci_mem_offset
;
1436 return (long)hose
->io_base_phys
;
1438 return (long)isa_io_base
;
1439 case IOBASE_ISA_MEM
: