arch/powerpc/kernel/perf_counter.c

   1 /*
   2  * Performance counter support - powerpc architecture code
   3  *
   4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/sched.h>
  13 #include <linux/perf_counter.h>
  14 #include <linux/percpu.h>
  15 #include <linux/hardirq.h>
  16 #include <asm/reg.h>
  17 #include <asm/pmc.h>
  18 #include <asm/machdep.h>
  19 #include <asm/firmware.h>
  20
  21 struct cpu_hw_counters {
  22         int n_counters;
  23         int n_percpu;
  24         int disabled;
  25         int n_added;
  26         struct perf_counter *counter[MAX_HWCOUNTERS];
  27         unsigned int events[MAX_HWCOUNTERS];
  28         u64 mmcr[3];
  29         u8 pmcs_enabled;
  30 };
  31 DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
  32
  33 struct power_pmu *ppmu;
  34
  35 /*
  36  * Normally, to ignore kernel events we set the FCS (freeze counters
  37  * in supervisor mode) bit in MMCR0, but if the kernel runs with the
  38  * hypervisor bit set in the MSR, or if we are running on a processor
  39  * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
  40  * then we need to use the FCHV bit to ignore kernel events.
  41  */
  42 static unsigned int freeze_counters_kernel = MMCR0_FCS;
  43
  44 static void perf_counter_interrupt(struct pt_regs *regs);
  45
  46 void perf_counter_print_debug(void)
  47 {
  48 }
  49
  50 /*
  51  * Read one performance monitor counter (PMC).
  52  */
  53 static unsigned long read_pmc(int idx)
  54 {
  55         unsigned long val;
  56
  57         switch (idx) {
  58         case 1:
  59                 val = mfspr(SPRN_PMC1);
  60                 break;
  61         case 2:
  62                 val = mfspr(SPRN_PMC2);
  63                 break;
  64         case 3:
  65                 val = mfspr(SPRN_PMC3);
  66                 break;
  67         case 4:
  68                 val = mfspr(SPRN_PMC4);
  69                 break;
  70         case 5:
  71                 val = mfspr(SPRN_PMC5);
  72                 break;
  73         case 6:
  74                 val = mfspr(SPRN_PMC6);
  75                 break;
  76         case 7:
  77                 val = mfspr(SPRN_PMC7);
  78                 break;
  79         case 8:
  80                 val = mfspr(SPRN_PMC8);
  81                 break;
  82         default:
  83                 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
  84                 val = 0;
  85         }
  86         return val;
  87 }
  88
  89 /*
  90  * Write one PMC.
  91  */
  92 static void write_pmc(int idx, unsigned long val)
  93 {
  94         switch (idx) {
  95         case 1:
  96                 mtspr(SPRN_PMC1, val);
  97                 break;
  98         case 2:
  99                 mtspr(SPRN_PMC2, val);
 100                 break;
 101         case 3:
 102                 mtspr(SPRN_PMC3, val);
 103                 break;
 104         case 4:
 105                 mtspr(SPRN_PMC4, val);
 106                 break;
 107         case 5:
 108                 mtspr(SPRN_PMC5, val);
 109                 break;
 110         case 6:
 111                 mtspr(SPRN_PMC6, val);
 112                 break;
 113         case 7:
 114                 mtspr(SPRN_PMC7, val);
 115                 break;
 116         case 8:
 117                 mtspr(SPRN_PMC8, val);
 118                 break;
 119         default:
 120                 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
 121         }
 122 }
 123
 124 /*
 125  * Check if a set of events can all go on the PMU at once.
 126  * If they can't, this will look at alternative codes for the events
 127  * and see if any combination of alternative codes is feasible.
 128  * The feasible set is returned in event[].
 129  */
 130 static int power_check_constraints(unsigned int event[], int n_ev)
 131 {
 132         u64 mask, value, nv;
 133         unsigned int alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 134         u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 135         u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 136         u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
 137         int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
 138         int i, j;
 139         u64 addf = ppmu->add_fields;
 140         u64 tadd = ppmu->test_adder;
 141
 142         if (n_ev > ppmu->n_counter)
 143                 return -1;
 144
 145         /* First see if the events will go on as-is */
 146         for (i = 0; i < n_ev; ++i) {
 147                 alternatives[i][0] = event[i];
 148                 if (ppmu->get_constraint(event[i], &amasks[i][0],
 149                                          &avalues[i][0]))
 150                         return -1;
 151                 choice[i] = 0;
 152         }
 153         value = mask = 0;
 154         for (i = 0; i < n_ev; ++i) {
 155                 nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf);
 156                 if ((((nv + tadd) ^ value) & mask) != 0 ||
 157                     (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0)
 158                         break;
 159                 value = nv;
 160                 mask |= amasks[i][0];
 161         }
 162         if (i == n_ev)
 163                 return 0;       /* all OK */
 164
 165         /* doesn't work, gather alternatives... */
 166         if (!ppmu->get_alternatives)
 167                 return -1;
 168         for (i = 0; i < n_ev; ++i) {
 169                 n_alt[i] = ppmu->get_alternatives(event[i], alternatives[i]);
 170                 for (j = 1; j < n_alt[i]; ++j)
 171                         ppmu->get_constraint(alternatives[i][j],
 172                                              &amasks[i][j], &avalues[i][j]);
 173         }
 174
 175         /* enumerate all possibilities and see if any will work */
 176         i = 0;
 177         j = -1;
 178         value = mask = nv = 0;
 179         while (i < n_ev) {
 180                 if (j >= 0) {
 181                         /* we're backtracking, restore context */
 182                         value = svalues[i];
 183                         mask = smasks[i];
 184                         j = choice[i];
 185                 }
 186                 /*
 187                  * See if any alternative k for event i,
 188                  * where k > j, will satisfy the constraints.
 189                  */
 190                 while (++j < n_alt[i]) {
 191                         nv = (value | avalues[i][j]) +
 192                                 (value & avalues[i][j] & addf);
 193                         if ((((nv + tadd) ^ value) & mask) == 0 &&
 194                             (((nv + tadd) ^ avalues[i][j])
 195                              & amasks[i][j]) == 0)
 196                                 break;
 197                 }
 198                 if (j >= n_alt[i]) {
 199                         /*
 200                          * No feasible alternative, backtrack
 201                          * to event i-1 and continue enumerating its
 202                          * alternatives from where we got up to.
 203                          */
 204                         if (--i < 0)
 205                                 return -1;
 206                 } else {
 207                         /*
 208                          * Found a feasible alternative for event i,
 209                          * remember where we got up to with this event,
 210                          * go on to the next event, and start with
 211                          * the first alternative for it.
 212                          */
 213                         choice[i] = j;
 214                         svalues[i] = value;
 215                         smasks[i] = mask;
 216                         value = nv;
 217                         mask |= amasks[i][j];
 218                         ++i;
 219                         j = -1;
 220                 }
 221         }
 222
 223         /* OK, we have a feasible combination, tell the caller the solution */
 224         for (i = 0; i < n_ev; ++i)
 225                 event[i] = alternatives[i][choice[i]];
 226         return 0;
 227 }
 228
 229 /*
 230  * Check if newly-added counters have consistent settings for
 231  * exclude_{user,kernel,hv} with each other and any previously
 232  * added counters.
 233  */
 234 static int check_excludes(struct perf_counter **ctrs, int n_prev, int n_new)
 235 {
 236         int eu, ek, eh;
 237         int i, n;
 238         struct perf_counter *counter;
 239
 240         n = n_prev + n_new;
 241         if (n <= 1)
 242                 return 0;
 243
 244         eu = ctrs[0]->hw_event.exclude_user;
 245         ek = ctrs[0]->hw_event.exclude_kernel;
 246         eh = ctrs[0]->hw_event.exclude_hv;
 247         if (n_prev == 0)
 248                 n_prev = 1;
 249         for (i = n_prev; i < n; ++i) {
 250                 counter = ctrs[i];
 251                 if (counter->hw_event.exclude_user != eu ||
 252                     counter->hw_event.exclude_kernel != ek ||
 253                     counter->hw_event.exclude_hv != eh)
 254                         return -EAGAIN;
 255         }
 256         return 0;
 257 }
 258
 259 static void power_perf_read(struct perf_counter *counter)
 260 {
 261         long val, delta, prev;
 262
 263         if (!counter->hw.idx)
 264                 return;
 265         /*
 266          * Performance monitor interrupts come even when interrupts
 267          * are soft-disabled, as long as interrupts are hard-enabled.
 268          * Therefore we treat them like NMIs.
 269          */
 270         do {
 271                 prev = atomic64_read(&counter->hw.prev_count);
 272                 barrier();
 273                 val = read_pmc(counter->hw.idx);
 274         } while (atomic64_cmpxchg(&counter->hw.prev_count, prev, val) != prev);
 275
 276         /* The counters are only 32 bits wide */
 277         delta = (val - prev) & 0xfffffffful;
 278         atomic64_add(delta, &counter->count);
 279         atomic64_sub(delta, &counter->hw.period_left);
 280 }
 281
 282 /*
 283  * Disable all counters to prevent PMU interrupts and to allow
 284  * counters to be added or removed.
 285  */
 286 u64 hw_perf_save_disable(void)
 287 {
 288         struct cpu_hw_counters *cpuhw;
 289         unsigned long ret;
 290         unsigned long flags;
 291
 292         local_irq_save(flags);
 293         cpuhw = &__get_cpu_var(cpu_hw_counters);
 294
 295         ret = cpuhw->disabled;
 296         if (!ret) {
 297                 cpuhw->disabled = 1;
 298                 cpuhw->n_added = 0;
 299
 300                 /*
 301                  * Check if we ever enabled the PMU on this cpu.
 302                  */
 303                 if (!cpuhw->pmcs_enabled) {
 304                         if (ppc_md.enable_pmcs)
 305                                 ppc_md.enable_pmcs();
 306                         cpuhw->pmcs_enabled = 1;
 307                 }
 308
 309                 /*
 310                  * Set the 'freeze counters' bit.
 311                  * The barrier is to make sure the mtspr has been
 312                  * executed and the PMU has frozen the counters
 313                  * before we return.
 314                  */
 315                 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) | MMCR0_FC);
 316                 mb();
 317         }
 318         local_irq_restore(flags);
 319         return ret;
 320 }
 321
 322 /*
 323  * Re-enable all counters if disable == 0.
 324  * If we were previously disabled and counters were added, then
 325  * put the new config on the PMU.
 326  */
 327 void hw_perf_restore(u64 disable)
 328 {
 329         struct perf_counter *counter;
 330         struct cpu_hw_counters *cpuhw;
 331         unsigned long flags;
 332         long i;
 333         unsigned long val;
 334         s64 left;
 335         unsigned int hwc_index[MAX_HWCOUNTERS];
 336
 337         if (disable)
 338                 return;
 339         local_irq_save(flags);
 340         cpuhw = &__get_cpu_var(cpu_hw_counters);
 341         cpuhw->disabled = 0;
 342
 343         /*
 344          * If we didn't change anything, or only removed counters,
 345          * no need to recalculate MMCR* settings and reset the PMCs.
 346          * Just reenable the PMU with the current MMCR* settings
 347          * (possibly updated for removal of counters).
 348          */
 349         if (!cpuhw->n_added) {
 350                 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
 351                 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 352                 mtspr(SPRN_MMCR0, cpuhw->mmcr[0]);
 353                 if (cpuhw->n_counters == 0)
 354                         get_lppaca()->pmcregs_in_use = 0;
 355                 goto out;
 356         }
 357
 358         /*
 359          * Compute MMCR* values for the new set of counters
 360          */
 361         if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_counters, hwc_index,
 362                                cpuhw->mmcr)) {
 363                 /* shouldn't ever get here */
 364                 printk(KERN_ERR "oops compute_mmcr failed\n");
 365                 goto out;
 366         }
 367
 368         /*
 369          * Add in MMCR0 freeze bits corresponding to the
 370          * hw_event.exclude_* bits for the first counter.
 371          * We have already checked that all counters have the
 372          * same values for these bits as the first counter.
 373          */
 374         counter = cpuhw->counter[0];
 375         if (counter->hw_event.exclude_user)
 376                 cpuhw->mmcr[0] |= MMCR0_FCP;
 377         if (counter->hw_event.exclude_kernel)
 378                 cpuhw->mmcr[0] |= freeze_counters_kernel;
 379         if (counter->hw_event.exclude_hv)
 380                 cpuhw->mmcr[0] |= MMCR0_FCHV;
 381
 382         /*
 383          * Write the new configuration to MMCR* with the freeze
 384          * bit set and set the hardware counters to their initial values.
 385          * Then unfreeze the counters.
 386          */
 387         get_lppaca()->pmcregs_in_use = 1;
 388         mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
 389         mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 390         mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
 391                                 | MMCR0_FC);
 392
 393         /*
 394          * Read off any pre-existing counters that need to move
 395          * to another PMC.
 396          */
 397         for (i = 0; i < cpuhw->n_counters; ++i) {
 398                 counter = cpuhw->counter[i];
 399                 if (counter->hw.idx && counter->hw.idx != hwc_index[i] + 1) {
 400                         power_perf_read(counter);
 401                         write_pmc(counter->hw.idx, 0);
 402                         counter->hw.idx = 0;
 403                 }
 404         }
 405
 406         /*
 407          * Initialize the PMCs for all the new and moved counters.
 408          */
 409         for (i = 0; i < cpuhw->n_counters; ++i) {
 410                 counter = cpuhw->counter[i];
 411                 if (counter->hw.idx)
 412                         continue;
 413                 val = 0;
 414                 if (counter->hw_event.irq_period) {
 415                         left = atomic64_read(&counter->hw.period_left);
 416                         if (left < 0x80000000L)
 417                                 val = 0x80000000L - left;
 418                 }
 419                 atomic64_set(&counter->hw.prev_count, val);
 420                 counter->hw.idx = hwc_index[i] + 1;
 421                 write_pmc(counter->hw.idx, val);
 422                 perf_counter_update_userpage(counter);
 423         }
 424         mb();
 425         cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
 426         mtspr(SPRN_MMCR0, cpuhw->mmcr[0]);
 427
 428  out:
 429         local_irq_restore(flags);
 430 }
 431
 432 static int collect_events(struct perf_counter *group, int max_count,
 433                           struct perf_counter *ctrs[], unsigned int *events)
 434 {
 435         int n = 0;
 436         struct perf_counter *counter;
 437
 438         if (!is_software_counter(group)) {
 439                 if (n >= max_count)
 440                         return -1;
 441                 ctrs[n] = group;
 442                 events[n++] = group->hw.config;
 443         }
 444         list_for_each_entry(counter, &group->sibling_list, list_entry) {
 445                 if (!is_software_counter(counter) &&
 446                     counter->state != PERF_COUNTER_STATE_OFF) {
 447                         if (n >= max_count)
 448                                 return -1;
 449                         ctrs[n] = counter;
 450                         events[n++] = counter->hw.config;
 451                 }
 452         }
 453         return n;
 454 }
 455
 456 static void counter_sched_in(struct perf_counter *counter, int cpu)
 457 {
 458         counter->state = PERF_COUNTER_STATE_ACTIVE;
 459         counter->oncpu = cpu;
 460         counter->tstamp_running += counter->ctx->time - counter->tstamp_stopped;
 461         if (is_software_counter(counter))
 462                 counter->hw_ops->enable(counter);
 463 }
 464
 465 /*
 466  * Called to enable a whole group of counters.
 467  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
 468  * Assumes the caller has disabled interrupts and has
 469  * frozen the PMU with hw_perf_save_disable.
 470  */
 471 int hw_perf_group_sched_in(struct perf_counter *group_leader,
 472                struct perf_cpu_context *cpuctx,
 473                struct perf_counter_context *ctx, int cpu)
 474 {
 475         struct cpu_hw_counters *cpuhw;
 476         long i, n, n0;
 477         struct perf_counter *sub;
 478
 479         cpuhw = &__get_cpu_var(cpu_hw_counters);
 480         n0 = cpuhw->n_counters;
 481         n = collect_events(group_leader, ppmu->n_counter - n0,
 482                            &cpuhw->counter[n0], &cpuhw->events[n0]);
 483         if (n < 0)
 484                 return -EAGAIN;
 485         if (check_excludes(cpuhw->counter, n0, n))
 486                 return -EAGAIN;
 487         if (power_check_constraints(cpuhw->events, n + n0))
 488                 return -EAGAIN;
 489         cpuhw->n_counters = n0 + n;
 490         cpuhw->n_added += n;
 491
 492         /*
 493          * OK, this group can go on; update counter states etc.,
 494          * and enable any software counters
 495          */
 496         for (i = n0; i < n0 + n; ++i)
 497                 cpuhw->counter[i]->hw.config = cpuhw->events[i];
 498         cpuctx->active_oncpu += n;
 499         n = 1;
 500         counter_sched_in(group_leader, cpu);
 501         list_for_each_entry(sub, &group_leader->sibling_list, list_entry) {
 502                 if (sub->state != PERF_COUNTER_STATE_OFF) {
 503                         counter_sched_in(sub, cpu);
 504                         ++n;
 505                 }
 506         }
 507         ctx->nr_active += n;
 508
 509         return 1;
 510 }
 511
 512 /*
 513  * Add a counter to the PMU.
 514  * If all counters are not already frozen, then we disable and
 515  * re-enable the PMU in order to get hw_perf_restore to do the
 516  * actual work of reconfiguring the PMU.
 517  */
 518 static int power_perf_enable(struct perf_counter *counter)
 519 {
 520         struct cpu_hw_counters *cpuhw;
 521         unsigned long flags;
 522         u64 pmudis;
 523         int n0;
 524         int ret = -EAGAIN;
 525
 526         local_irq_save(flags);
 527         pmudis = hw_perf_save_disable();
 528
 529         /*
 530          * Add the counter to the list (if there is room)
 531          * and check whether the total set is still feasible.
 532          */
 533         cpuhw = &__get_cpu_var(cpu_hw_counters);
 534         n0 = cpuhw->n_counters;
 535         if (n0 >= ppmu->n_counter)
 536                 goto out;
 537         cpuhw->counter[n0] = counter;
 538         cpuhw->events[n0] = counter->hw.config;
 539         if (check_excludes(cpuhw->counter, n0, 1))
 540                 goto out;
 541         if (power_check_constraints(cpuhw->events, n0 + 1))
 542                 goto out;
 543
 544         counter->hw.config = cpuhw->events[n0];
 545         ++cpuhw->n_counters;
 546         ++cpuhw->n_added;
 547
 548         ret = 0;
 549  out:
 550         hw_perf_restore(pmudis);
 551         local_irq_restore(flags);
 552         return ret;
 553 }
 554
 555 /*
 556  * Remove a counter from the PMU.
 557  */
 558 static void power_perf_disable(struct perf_counter *counter)
 559 {
 560         struct cpu_hw_counters *cpuhw;
 561         long i;
 562         u64 pmudis;
 563         unsigned long flags;
 564
 565         local_irq_save(flags);
 566         pmudis = hw_perf_save_disable();
 567
 568         power_perf_read(counter);
 569
 570         cpuhw = &__get_cpu_var(cpu_hw_counters);
 571         for (i = 0; i < cpuhw->n_counters; ++i) {
 572                 if (counter == cpuhw->counter[i]) {
 573                         while (++i < cpuhw->n_counters)
 574                                 cpuhw->counter[i-1] = cpuhw->counter[i];
 575                         --cpuhw->n_counters;
 576                         ppmu->disable_pmc(counter->hw.idx - 1, cpuhw->mmcr);
 577                         write_pmc(counter->hw.idx, 0);
 578                         counter->hw.idx = 0;
 579                         perf_counter_update_userpage(counter);
 580                         break;
 581                 }
 582         }
 583         if (cpuhw->n_counters == 0) {
 584                 /* disable exceptions if no counters are running */
 585                 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
 586         }
 587
 588         hw_perf_restore(pmudis);
 589         local_irq_restore(flags);
 590 }
 591
 592 struct hw_perf_counter_ops power_perf_ops = {
 593         .enable = power_perf_enable,
 594         .disable = power_perf_disable,
 595         .read = power_perf_read
 596 };
 597
 598 /* Number of perf_counters counting hardware events */
 599 static atomic_t num_counters;
 600 /* Used to avoid races in calling reserve/release_pmc_hardware */
 601 static DEFINE_MUTEX(pmc_reserve_mutex);
 602
 603 /*
 604  * Release the PMU if this is the last perf_counter.
 605  */
 606 static void hw_perf_counter_destroy(struct perf_counter *counter)
 607 {
 608         if (!atomic_add_unless(&num_counters, -1, 1)) {
 609                 mutex_lock(&pmc_reserve_mutex);
 610                 if (atomic_dec_return(&num_counters) == 0)
 611                         release_pmc_hardware();
 612                 mutex_unlock(&pmc_reserve_mutex);
 613         }
 614 }
 615
 616 const struct hw_perf_counter_ops *
 617 hw_perf_counter_init(struct perf_counter *counter)
 618 {
 619         unsigned long ev;
 620         struct perf_counter *ctrs[MAX_HWCOUNTERS];
 621         unsigned int events[MAX_HWCOUNTERS];
 622         int n;
 623         int err;
 624
 625         if (!ppmu)
 626                 return ERR_PTR(-ENXIO);
 627         if ((s64)counter->hw_event.irq_period < 0)
 628                 return ERR_PTR(-EINVAL);
 629         if (!perf_event_raw(&counter->hw_event)) {
 630                 ev = perf_event_id(&counter->hw_event);
 631                 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
 632                         return ERR_PTR(-EOPNOTSUPP);
 633                 ev = ppmu->generic_events[ev];
 634         } else {
 635                 ev = perf_event_config(&counter->hw_event);
 636         }
 637         counter->hw.config_base = ev;
 638         counter->hw.idx = 0;
 639
 640         /*
 641          * If we are not running on a hypervisor, force the
 642          * exclude_hv bit to 0 so that we don't care what
 643          * the user set it to.
 644          */
 645         if (!firmware_has_feature(FW_FEATURE_LPAR))
 646                 counter->hw_event.exclude_hv = 0;
 647
 648         /*
 649          * If this is in a group, check if it can go on with all the
 650          * other hardware counters in the group.  We assume the counter
 651          * hasn't been linked into its leader's sibling list at this point.
 652          */
 653         n = 0;
 654         if (counter->group_leader != counter) {
 655                 n = collect_events(counter->group_leader, ppmu->n_counter - 1,
 656                                    ctrs, events);
 657                 if (n < 0)
 658                         return ERR_PTR(-EINVAL);
 659         }
 660         events[n] = ev;
 661         ctrs[n] = counter;
 662         if (check_excludes(ctrs, n, 1))
 663                 return ERR_PTR(-EINVAL);
 664         if (power_check_constraints(events, n + 1))
 665                 return ERR_PTR(-EINVAL);
 666
 667         counter->hw.config = events[n];
 668         atomic64_set(&counter->hw.period_left, counter->hw_event.irq_period);
 669
 670         /*
 671          * See if we need to reserve the PMU.
 672          * If no counters are currently in use, then we have to take a
 673          * mutex to ensure that we don't race with another task doing
 674          * reserve_pmc_hardware or release_pmc_hardware.
 675          */
 676         err = 0;
 677         if (!atomic_inc_not_zero(&num_counters)) {
 678                 mutex_lock(&pmc_reserve_mutex);
 679                 if (atomic_read(&num_counters) == 0 &&
 680                     reserve_pmc_hardware(perf_counter_interrupt))
 681                         err = -EBUSY;
 682                 else
 683                         atomic_inc(&num_counters);
 684                 mutex_unlock(&pmc_reserve_mutex);
 685         }
 686         counter->destroy = hw_perf_counter_destroy;
 687
 688         if (err)
 689                 return ERR_PTR(err);
 690         return &power_perf_ops;
 691 }
 692
 693 /*
 694  * A counter has overflowed; update its count and record
 695  * things if requested.  Note that interrupts are hard-disabled
 696  * here so there is no possibility of being interrupted.
 697  */
 698 static void record_and_restart(struct perf_counter *counter, long val,
 699                                struct pt_regs *regs)
 700 {
 701         s64 prev, delta, left;
 702         int record = 0;
 703
 704         /* we don't have to worry about interrupts here */
 705         prev = atomic64_read(&counter->hw.prev_count);
 706         delta = (val - prev) & 0xfffffffful;
 707         atomic64_add(delta, &counter->count);
 708
 709         /*
 710          * See if the total period for this counter has expired,
 711          * and update for the next period.
 712          */
 713         val = 0;
 714         left = atomic64_read(&counter->hw.period_left) - delta;
 715         if (counter->hw_event.irq_period) {
 716                 if (left <= 0) {
 717                         left += counter->hw_event.irq_period;
 718                         if (left <= 0)
 719                                 left = counter->hw_event.irq_period;
 720                         record = 1;
 721                 }
 722                 if (left < 0x80000000L)
 723                         val = 0x80000000L - left;
 724         }
 725         write_pmc(counter->hw.idx, val);
 726         atomic64_set(&counter->hw.prev_count, val);
 727         atomic64_set(&counter->hw.period_left, left);
 728         perf_counter_update_userpage(counter);
 729
 730         /*
 731          * Finally record data if requested.
 732          */
 733         if (record)
 734                 perf_counter_overflow(counter, 1, regs);
 735 }
 736
 737 /*
 738  * Performance monitor interrupt stuff
 739  */
 740 static void perf_counter_interrupt(struct pt_regs *regs)
 741 {
 742         int i;
 743         struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters);
 744         struct perf_counter *counter;
 745         long val;
 746         int found = 0;
 747
 748         for (i = 0; i < cpuhw->n_counters; ++i) {
 749                 counter = cpuhw->counter[i];
 750                 val = read_pmc(counter->hw.idx);
 751                 if ((int)val < 0) {
 752                         /* counter has overflowed */
 753                         found = 1;
 754                         record_and_restart(counter, val, regs);
 755                 }
 756         }
 757
 758         /*
 759          * In case we didn't find and reset the counter that caused
 760          * the interrupt, scan all counters and reset any that are
 761          * negative, to avoid getting continual interrupts.
 762          * Any that we processed in the previous loop will not be negative.
 763          */
 764         if (!found) {
 765                 for (i = 0; i < ppmu->n_counter; ++i) {
 766                         val = read_pmc(i + 1);
 767                         if ((int)val < 0)
 768                                 write_pmc(i + 1, 0);
 769                 }
 770         }
 771
 772         /*
 773          * Reset MMCR0 to its normal value.  This will set PMXE and
 774          * clear FC (freeze counters) and PMAO (perf mon alert occurred)
 775          * and thus allow interrupts to occur again.
 776          * XXX might want to use MSR.PM to keep the counters frozen until
 777          * we get back out of this interrupt.
 778          */
 779         mtspr(SPRN_MMCR0, cpuhw->mmcr[0]);
 780
 781         /*
 782          * If we need a wakeup, check whether interrupts were soft-enabled
 783          * when we took the interrupt.  If they were, we can wake stuff up
 784          * immediately; otherwise we'll have do the wakeup when interrupts
 785          * get soft-enabled.
 786          */
 787         if (test_perf_counter_pending() && regs->softe) {
 788                 irq_enter();
 789                 clear_perf_counter_pending();
 790                 perf_counter_do_pending();
 791                 irq_exit();
 792         }
 793 }
 794
 795 void hw_perf_counter_setup(int cpu)
 796 {
 797         struct cpu_hw_counters *cpuhw = &per_cpu(cpu_hw_counters, cpu);
 798
 799         memset(cpuhw, 0, sizeof(*cpuhw));
 800         cpuhw->mmcr[0] = MMCR0_FC;
 801 }
 802
 803 extern struct power_pmu power4_pmu;
 804 extern struct power_pmu ppc970_pmu;
 805 extern struct power_pmu power5_pmu;
 806 extern struct power_pmu power5p_pmu;
 807 extern struct power_pmu power6_pmu;
 808
 809 static int init_perf_counters(void)
 810 {
 811         unsigned long pvr;
 812
 813         /* XXX should get this from cputable */
 814         pvr = mfspr(SPRN_PVR);
 815         switch (PVR_VER(pvr)) {
 816         case PV_POWER4:
 817         case PV_POWER4p:
 818                 ppmu = &power4_pmu;
 819                 break;
 820         case PV_970:
 821         case PV_970FX:
 822         case PV_970MP:
 823                 ppmu = &ppc970_pmu;
 824                 break;
 825         case PV_POWER5:
 826                 ppmu = &power5_pmu;
 827                 break;
 828         case PV_POWER5p:
 829                 ppmu = &power5p_pmu;
 830                 break;
 831         case 0x3e:
 832                 ppmu = &power6_pmu;
 833                 break;
 834         }
 835
 836         /*
 837          * Use FCHV to ignore kernel events if MSR.HV is set.
 838          */
 839         if (mfmsr() & MSR_HV)
 840                 freeze_counters_kernel = MMCR0_FCHV;
 841
 842         return 0;
 843 }
 844
 845 arch_initcall(init_perf_counters);