2 * Performance counter support for POWER5+/++ (not POWER5) processors.
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/perf_counter.h>
16 * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
18 #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
19 #define PM_PMC_MSK 0xf
20 #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21 #define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */
22 #define PM_UNIT_MSK 0xf
23 #define PM_BYTE_SH 12 /* Byte number of event bus to use */
25 #define PM_GRS_SH 8 /* Storage subsystem mux select */
27 #define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */
28 #define PM_PMCSEL_MSK 0x7f
30 /* Values in PM_UNIT field */
40 #define PM_LASTUNIT 0xc
43 * Bits in MMCR1 for POWER5+
45 #define MMCR1_TTM0SEL_SH 62
46 #define MMCR1_TTM1SEL_SH 60
47 #define MMCR1_TTM2SEL_SH 58
48 #define MMCR1_TTM3SEL_SH 56
49 #define MMCR1_TTMSEL_MSK 3
50 #define MMCR1_TD_CP_DBG0SEL_SH 54
51 #define MMCR1_TD_CP_DBG1SEL_SH 52
52 #define MMCR1_TD_CP_DBG2SEL_SH 50
53 #define MMCR1_TD_CP_DBG3SEL_SH 48
54 #define MMCR1_GRS_L2SEL_SH 46
55 #define MMCR1_GRS_L2SEL_MSK 3
56 #define MMCR1_GRS_L3SEL_SH 44
57 #define MMCR1_GRS_L3SEL_MSK 3
58 #define MMCR1_GRS_MCSEL_SH 41
59 #define MMCR1_GRS_MCSEL_MSK 7
60 #define MMCR1_GRS_FABSEL_SH 39
61 #define MMCR1_GRS_FABSEL_MSK 3
62 #define MMCR1_PMC1_ADDER_SEL_SH 35
63 #define MMCR1_PMC2_ADDER_SEL_SH 34
64 #define MMCR1_PMC3_ADDER_SEL_SH 33
65 #define MMCR1_PMC4_ADDER_SEL_SH 32
66 #define MMCR1_PMC1SEL_SH 25
67 #define MMCR1_PMC2SEL_SH 17
68 #define MMCR1_PMC3SEL_SH 9
69 #define MMCR1_PMC4SEL_SH 1
70 #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
71 #define MMCR1_PMCSEL_MSK 0x7f
78 * Layout of constraint bits:
79 * 6666555555555544444444443333333333222222222211111111110000000000
80 * 3210987654321098765432109876543210987654321098765432109876543210
81 * [ ><><>< ><> <><>[ > < >< >< >< ><><><><><><>
82 * NC G0G1G2 G3 T0T1 UC B0 B1 B2 B3 P6P5P4P3P2P1
84 * NC - number of counters
85 * 51: NC error 0x0008_0000_0000_0000
86 * 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
88 * G0..G3 - GRS mux constraints
89 * 46-47: GRS_L2SEL value
90 * 44-45: GRS_L3SEL value
91 * 41-44: GRS_MCSEL value
92 * 39-40: GRS_FABSEL value
93 * Note that these match up with their bit positions in MMCR1
95 * T0 - TTM0 constraint
96 * 36-37: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0x30_0000_0000
98 * T1 - TTM1 constraint
99 * 34-35: TTM1SEL value (0=IDU, 3=GRS) 0x0c_0000_0000
101 * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
102 * 33: UC3 error 0x02_0000_0000
103 * 32: FPU|IFU|ISU1 events needed 0x01_0000_0000
104 * 31: ISU0 events needed 0x01_8000_0000
105 * 30: IDU|GRS events needed 0x00_4000_0000
108 * 24-27: Byte 0 event source 0x0f00_0000
109 * Encoding as for the event code
112 * 20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
116 * 10-11: Count of events needing PMC6
119 * 0-9: Count of events needing PMC1..PMC5
122 static const int grsel_shift
[8] = {
123 MMCR1_GRS_L2SEL_SH
, MMCR1_GRS_L2SEL_SH
, MMCR1_GRS_L2SEL_SH
,
124 MMCR1_GRS_L3SEL_SH
, MMCR1_GRS_L3SEL_SH
, MMCR1_GRS_L3SEL_SH
,
125 MMCR1_GRS_MCSEL_SH
, MMCR1_GRS_FABSEL_SH
128 /* Masks and values for using events from the various units */
129 static u64 unit_cons
[PM_LASTUNIT
+1][2] = {
130 [PM_FPU
] = { 0x3200000000ull
, 0x0100000000ull
},
131 [PM_ISU0
] = { 0x0200000000ull
, 0x0080000000ull
},
132 [PM_ISU1
] = { 0x3200000000ull
, 0x3100000000ull
},
133 [PM_IFU
] = { 0x3200000000ull
, 0x2100000000ull
},
134 [PM_IDU
] = { 0x0e00000000ull
, 0x0040000000ull
},
135 [PM_GRS
] = { 0x0e00000000ull
, 0x0c40000000ull
},
138 static int power5p_get_constraint(unsigned int event
, u64
*maskp
, u64
*valp
)
140 int pmc
, byte
, unit
, sh
;
142 u64 mask
= 0, value
= 0;
144 pmc
= (event
>> PM_PMC_SH
) & PM_PMC_MSK
;
151 if (pmc
>= 5 && !(event
== 0x500009 || event
== 0x600005))
154 if (event
& PM_BUSEVENT_MSK
) {
155 unit
= (event
>> PM_UNIT_SH
) & PM_UNIT_MSK
;
156 if (unit
> PM_LASTUNIT
)
158 if (unit
== PM_ISU0_ALT
)
160 mask
|= unit_cons
[unit
][0];
161 value
|= unit_cons
[unit
][1];
162 byte
= (event
>> PM_BYTE_SH
) & PM_BYTE_MSK
;
166 /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
170 if (unit
== PM_GRS
) {
172 fmask
= (bit
== 6)? 7: 3;
173 sh
= grsel_shift
[bit
];
174 mask
|= (u64
)fmask
<< sh
;
175 value
|= (u64
)((event
>> PM_GRS_SH
) & fmask
) << sh
;
177 /* Set byte lane select field */
178 mask
|= 0xfULL
<< (24 - 4 * byte
);
179 value
|= (u64
)unit
<< (24 - 4 * byte
);
182 /* need a counter from PMC1-4 set */
183 mask
|= 0x8000000000000ull
;
184 value
|= 0x1000000000000ull
;
191 static int power5p_limited_pmc_event(unsigned int event
)
193 int pmc
= (event
>> PM_PMC_SH
) & PM_PMC_MSK
;
195 return pmc
== 5 || pmc
== 6;
198 #define MAX_ALT 3 /* at most 3 alternatives for any event */
200 static const unsigned int event_alternatives
[][MAX_ALT
] = {
201 { 0x100c0, 0x40001f }, /* PM_GCT_FULL_CYC */
202 { 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */
203 { 0x230e2, 0x323087 }, /* PM_BR_PRED_CR */
204 { 0x230e3, 0x223087, 0x3230a0 }, /* PM_BR_PRED_TA */
205 { 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */
206 { 0x800c4, 0xc20e0 }, /* PM_DTLB_MISS */
207 { 0xc50c6, 0xc60e0 }, /* PM_MRK_DTLB_MISS */
208 { 0x100005, 0x600005 }, /* PM_RUN_CYC */
209 { 0x100009, 0x200009 }, /* PM_INST_CMPL */
210 { 0x200015, 0x300015 }, /* PM_LSU_LMQ_SRQ_EMPTY_CYC */
211 { 0x300009, 0x400009 }, /* PM_INST_DISP */
215 * Scan the alternatives table for a match and return the
216 * index into the alternatives table if found, else -1.
218 static int find_alternative(unsigned int event
)
222 for (i
= 0; i
< ARRAY_SIZE(event_alternatives
); ++i
) {
223 if (event
< event_alternatives
[i
][0])
225 for (j
= 0; j
< MAX_ALT
&& event_alternatives
[i
][j
]; ++j
)
226 if (event
== event_alternatives
[i
][j
])
232 static const unsigned char bytedecode_alternatives
[4][4] = {
233 /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
234 /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
235 /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
236 /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
240 * Some direct events for decodes of event bus byte 3 have alternative
241 * PMCSEL values on other counters. This returns the alternative
242 * event code for those that do, or -1 otherwise. This also handles
243 * alternative PCMSEL values for add events.
245 static int find_alternative_bdecode(unsigned int event
)
247 int pmc
, altpmc
, pp
, j
;
249 pmc
= (event
>> PM_PMC_SH
) & PM_PMC_MSK
;
250 if (pmc
== 0 || pmc
> 4)
252 altpmc
= 5 - pmc
; /* 1 <-> 4, 2 <-> 3 */
253 pp
= event
& PM_PMCSEL_MSK
;
254 for (j
= 0; j
< 4; ++j
) {
255 if (bytedecode_alternatives
[pmc
- 1][j
] == pp
) {
256 return (event
& ~(PM_PMC_MSKS
| PM_PMCSEL_MSK
)) |
257 (altpmc
<< PM_PMC_SH
) |
258 bytedecode_alternatives
[altpmc
- 1][j
];
262 /* new decode alternatives for power5+ */
263 if (pmc
== 1 && (pp
== 0x0d || pp
== 0x0e))
264 return event
+ (2 << PM_PMC_SH
) + (0x2e - 0x0d);
265 if (pmc
== 3 && (pp
== 0x2e || pp
== 0x2f))
266 return event
- (2 << PM_PMC_SH
) - (0x2e - 0x0d);
268 /* alternative add event encodings */
269 if (pp
== 0x10 || pp
== 0x28)
270 return ((event
^ (0x10 ^ 0x28)) & ~PM_PMC_MSKS
) |
271 (altpmc
<< PM_PMC_SH
);
276 static int power5p_get_alternatives(unsigned int event
, unsigned int flags
,
279 int i
, j
, ae
, nalt
= 1;
284 nlim
= power5p_limited_pmc_event(event
);
285 i
= find_alternative(event
);
287 for (j
= 0; j
< MAX_ALT
; ++j
) {
288 ae
= event_alternatives
[i
][j
];
289 if (ae
&& ae
!= event
)
291 nlim
+= power5p_limited_pmc_event(ae
);
294 ae
= find_alternative_bdecode(event
);
299 if (flags
& PPMU_ONLY_COUNT_RUN
) {
301 * We're only counting in RUN state,
302 * so PM_CYC is equivalent to PM_RUN_CYC
303 * and PM_INST_CMPL === PM_RUN_INST_CMPL.
304 * This doesn't include alternatives that don't provide
305 * any extra flexibility in assigning PMCs (e.g.
306 * 0x100005 for PM_RUN_CYC vs. 0xf for PM_CYC).
307 * Note that even with these additional alternatives
308 * we never end up with more than 3 alternatives for any event.
311 for (i
= 0; i
< nalt
; ++i
) {
313 case 0xf: /* PM_CYC */
314 alt
[j
++] = 0x600005; /* PM_RUN_CYC */
317 case 0x600005: /* PM_RUN_CYC */
320 case 0x100009: /* PM_INST_CMPL */
321 alt
[j
++] = 0x500009; /* PM_RUN_INST_CMPL */
324 case 0x500009: /* PM_RUN_INST_CMPL */
325 alt
[j
++] = 0x100009; /* PM_INST_CMPL */
333 if (!(flags
& PPMU_LIMITED_PMC_OK
) && nlim
) {
334 /* remove the limited PMC events */
336 for (i
= 0; i
< nalt
; ++i
) {
337 if (!power5p_limited_pmc_event(alt
[i
])) {
343 } else if ((flags
& PPMU_LIMITED_PMC_REQD
) && nlim
< nalt
) {
344 /* remove all but the limited PMC events */
346 for (i
= 0; i
< nalt
; ++i
) {
347 if (power5p_limited_pmc_event(alt
[i
])) {
359 * Map of which direct events on which PMCs are marked instruction events.
360 * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
361 * Bit 0 is set if it is marked for all PMCs.
362 * The 0x80 bit indicates a byte decode PMCSEL value.
364 static unsigned char direct_event_is_marked
[0x28] = {
366 0x1f, /* 01 PM_IOPS_CMPL */
367 0x2, /* 02 PM_MRK_GRP_DISP */
368 0xe, /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
370 0x1c, /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
373 0, 0, 0,/* 08 - 0a */
374 0x18, /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
380 0x14, /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
382 0x10, /* 13 PM_MRK_GRP_CMPL */
383 0x1f, /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
384 0x2, /* 15 PM_MRK_GRP_ISSUED */
402 * Returns 1 if event counts things relating to marked instructions
403 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
405 static int power5p_marked_instr_event(unsigned int event
)
411 pmc
= (event
>> PM_PMC_SH
) & PM_PMC_MSK
;
412 psel
= event
& PM_PMCSEL_MSK
;
417 if (psel
< sizeof(direct_event_is_marked
)) {
418 if (direct_event_is_marked
[psel
] & (1 << pmc
))
420 if (direct_event_is_marked
[psel
] & 0x80)
422 else if (psel
== 0x08)
424 else if (psel
== 0x10)
426 else if (psel
== 0x1b && (pmc
== 1 || pmc
== 3))
428 } else if ((psel
& 0x48) == 0x40) {
430 } else if (psel
== 0x28) {
432 } else if (pmc
== 3 && (psel
== 0x2e || psel
== 0x2f)) {
436 if (!(event
& PM_BUSEVENT_MSK
) || bit
== -1)
439 byte
= (event
>> PM_BYTE_SH
) & PM_BYTE_MSK
;
440 unit
= (event
>> PM_UNIT_SH
) & PM_UNIT_MSK
;
441 if (unit
== PM_LSU0
) {
442 /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
444 } else if (unit
== PM_LSU1
&& byte
>= 4) {
446 /* byte 5 bits 6-7, byte 6 bits 0,4, byte 7 bits 0-4,6 */
451 return (mask
>> (byte
* 8 + bit
)) & 1;
454 static int power5p_compute_mmcr(unsigned int event
[], int n_ev
,
455 unsigned int hwc
[], u64 mmcr
[])
459 unsigned int pmc
, unit
, byte
, psel
;
461 int i
, isbus
, bit
, grsel
;
462 unsigned int pmc_inuse
= 0;
463 unsigned char busbyte
[4];
464 unsigned char unituse
[16];
470 /* First pass to count resource use */
471 memset(busbyte
, 0, sizeof(busbyte
));
472 memset(unituse
, 0, sizeof(unituse
));
473 for (i
= 0; i
< n_ev
; ++i
) {
474 pmc
= (event
[i
] >> PM_PMC_SH
) & PM_PMC_MSK
;
478 if (pmc_inuse
& (1 << (pmc
- 1)))
480 pmc_inuse
|= 1 << (pmc
- 1);
482 if (event
[i
] & PM_BUSEVENT_MSK
) {
483 unit
= (event
[i
] >> PM_UNIT_SH
) & PM_UNIT_MSK
;
484 byte
= (event
[i
] >> PM_BYTE_SH
) & PM_BYTE_MSK
;
485 if (unit
> PM_LASTUNIT
)
487 if (unit
== PM_ISU0_ALT
)
495 if (busbyte
[byte
] && busbyte
[byte
] != unit
)
497 busbyte
[byte
] = unit
;
503 * Assign resources and set multiplexer selects.
505 * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
506 * choice we have to deal with.
508 if (unituse
[PM_ISU0
] &
509 (unituse
[PM_FPU
] | unituse
[PM_IFU
] | unituse
[PM_ISU1
])) {
510 unituse
[PM_ISU0_ALT
] = 1; /* move ISU to TTM1 */
511 unituse
[PM_ISU0
] = 0;
513 /* Set TTM[01]SEL fields. */
515 for (i
= PM_FPU
; i
<= PM_ISU1
; ++i
) {
520 mmcr1
|= (u64
)i
<< MMCR1_TTM0SEL_SH
;
523 for (; i
<= PM_GRS
; ++i
) {
528 mmcr1
|= (u64
)(i
& 3) << MMCR1_TTM1SEL_SH
;
533 /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
534 for (byte
= 0; byte
< 4; ++byte
) {
535 unit
= busbyte
[byte
];
538 if (unit
== PM_ISU0
&& unituse
[PM_ISU0_ALT
]) {
539 /* get ISU0 through TTM1 rather than TTM0 */
541 } else if (unit
== PM_LSU1
+ 1) {
542 /* select lower word of LSU1 for this byte */
543 mmcr1
|= 1ull << (MMCR1_TTM3SEL_SH
+ 3 - byte
);
546 mmcr1
|= (u64
)ttm
<< (MMCR1_TD_CP_DBG0SEL_SH
- 2 * byte
);
549 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
550 for (i
= 0; i
< n_ev
; ++i
) {
551 pmc
= (event
[i
] >> PM_PMC_SH
) & PM_PMC_MSK
;
552 unit
= (event
[i
] >> PM_UNIT_SH
) & PM_UNIT_MSK
;
553 byte
= (event
[i
] >> PM_BYTE_SH
) & PM_BYTE_MSK
;
554 psel
= event
[i
] & PM_PMCSEL_MSK
;
555 isbus
= event
[i
] & PM_BUSEVENT_MSK
;
557 /* Bus event or any-PMC direct event */
558 for (pmc
= 0; pmc
< 4; ++pmc
) {
559 if (!(pmc_inuse
& (1 << pmc
)))
564 pmc_inuse
|= 1 << pmc
;
565 } else if (pmc
<= 4) {
568 if (isbus
&& (byte
& 2) &&
569 (psel
== 8 || psel
== 0x10 || psel
== 0x28))
570 /* add events on higher-numbered bus */
571 mmcr1
|= 1ull << (MMCR1_PMC1_ADDER_SEL_SH
- pmc
);
573 /* Instructions or run cycles on PMC5/6 */
576 if (isbus
&& unit
== PM_GRS
) {
578 grsel
= (event
[i
] >> PM_GRS_SH
) & PM_GRS_MSK
;
579 mmcr1
|= (u64
)grsel
<< grsel_shift
[bit
];
581 if (power5p_marked_instr_event(event
[i
]))
582 mmcra
|= MMCRA_SAMPLE_ENABLE
;
583 if ((psel
& 0x58) == 0x40 && (byte
& 1) != ((pmc
>> 1) & 1))
584 /* select alternate byte lane */
587 mmcr1
|= psel
<< MMCR1_PMCSEL_SH(pmc
);
591 /* Return MMCRx values */
594 mmcr
[0] = MMCR0_PMC1CE
;
595 if (pmc_inuse
& 0x3e)
596 mmcr
[0] |= MMCR0_PMCjCE
;
602 static void power5p_disable_pmc(unsigned int pmc
, u64 mmcr
[])
605 mmcr
[1] &= ~(0x7fUL
<< MMCR1_PMCSEL_SH(pmc
));
608 static int power5p_generic_events
[] = {
609 [PERF_COUNT_CPU_CYCLES
] = 0xf,
610 [PERF_COUNT_INSTRUCTIONS
] = 0x100009,
611 [PERF_COUNT_CACHE_REFERENCES
] = 0x1c10a8, /* LD_REF_L1 */
612 [PERF_COUNT_CACHE_MISSES
] = 0x3c1088, /* LD_MISS_L1 */
613 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x230e4, /* BR_ISSUED */
614 [PERF_COUNT_BRANCH_MISSES
] = 0x230e5, /* BR_MPRED_CR */
617 struct power_pmu power5p_pmu
= {
619 .max_alternatives
= MAX_ALT
,
620 .add_fields
= 0x7000000000055ull
,
621 .test_adder
= 0x3000040000000ull
,
622 .compute_mmcr
= power5p_compute_mmcr
,
623 .get_constraint
= power5p_get_constraint
,
624 .get_alternatives
= power5p_get_alternatives
,
625 .disable_pmc
= power5p_disable_pmc
,
626 .n_generic
= ARRAY_SIZE(power5p_generic_events
),
627 .generic_events
= power5p_generic_events
,
629 .limited_pmc_event
= power5p_limited_pmc_event
,