arch/powerpc/kernel/power5-pmu.c

   1 /*
   2  * Performance counter support for POWER5 (not POWER5++) processors.
   3  *
   4  * Copyright 2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/perf_counter.h>
  13 #include <asm/reg.h>
  14
  15 /*
  16  * Bits in event code for POWER5 (not POWER5++)
  17  */
  18 #define PM_PMC_SH       20      /* PMC number (1-based) for direct events */
  19 #define PM_PMC_MSK      0xf
  20 #define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
  21 #define PM_UNIT_SH      16      /* TTMMUX number and setting - unit select */
  22 #define PM_UNIT_MSK     0xf
  23 #define PM_BYTE_SH      12      /* Byte number of event bus to use */
  24 #define PM_BYTE_MSK     7
  25 #define PM_GRS_SH       8       /* Storage subsystem mux select */
  26 #define PM_GRS_MSK      7
  27 #define PM_BUSEVENT_MSK 0x80    /* Set if event uses event bus */
  28 #define PM_PMCSEL_MSK   0x7f
  29
  30 /* Values in PM_UNIT field */
  31 #define PM_FPU          0
  32 #define PM_ISU0         1
  33 #define PM_IFU          2
  34 #define PM_ISU1         3
  35 #define PM_IDU          4
  36 #define PM_ISU0_ALT     6
  37 #define PM_GRS          7
  38 #define PM_LSU0         8
  39 #define PM_LSU1         0xc
  40 #define PM_LASTUNIT     0xc
  41
  42 /*
  43  * Bits in MMCR1 for POWER5
  44  */
  45 #define MMCR1_TTM0SEL_SH        62
  46 #define MMCR1_TTM1SEL_SH        60
  47 #define MMCR1_TTM2SEL_SH        58
  48 #define MMCR1_TTM3SEL_SH        56
  49 #define MMCR1_TTMSEL_MSK        3
  50 #define MMCR1_TD_CP_DBG0SEL_SH  54
  51 #define MMCR1_TD_CP_DBG1SEL_SH  52
  52 #define MMCR1_TD_CP_DBG2SEL_SH  50
  53 #define MMCR1_TD_CP_DBG3SEL_SH  48
  54 #define MMCR1_GRS_L2SEL_SH      46
  55 #define MMCR1_GRS_L2SEL_MSK     3
  56 #define MMCR1_GRS_L3SEL_SH      44
  57 #define MMCR1_GRS_L3SEL_MSK     3
  58 #define MMCR1_GRS_MCSEL_SH      41
  59 #define MMCR1_GRS_MCSEL_MSK     7
  60 #define MMCR1_GRS_FABSEL_SH     39
  61 #define MMCR1_GRS_FABSEL_MSK    3
  62 #define MMCR1_PMC1_ADDER_SEL_SH 35
  63 #define MMCR1_PMC2_ADDER_SEL_SH 34
  64 #define MMCR1_PMC3_ADDER_SEL_SH 33
  65 #define MMCR1_PMC4_ADDER_SEL_SH 32
  66 #define MMCR1_PMC1SEL_SH        25
  67 #define MMCR1_PMC2SEL_SH        17
  68 #define MMCR1_PMC3SEL_SH        9
  69 #define MMCR1_PMC4SEL_SH        1
  70 #define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
  71 #define MMCR1_PMCSEL_MSK        0x7f
  72
  73 /*
  74  * Bits in MMCRA
  75  */
  76
  77 /*
  78  * Layout of constraint bits:
  79  * 6666555555555544444444443333333333222222222211111111110000000000
  80  * 3210987654321098765432109876543210987654321098765432109876543210
  81  *         <><>[  ><><>< ><> [  >[ >[ ><  ><  ><  ><  ><><><><><><>
  82  *         T0T1 NC G0G1G2 G3  UC PS1PS2 B0  B1  B2  B3 P6P5P4P3P2P1
  83  *
  84  * T0 - TTM0 constraint
  85  *     54-55: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0xc0_0000_0000_0000
  86  *
  87  * T1 - TTM1 constraint
  88  *     52-53: TTM1SEL value (0=IDU, 3=GRS) 0x30_0000_0000_0000
  89  *
  90  * NC - number of counters
  91  *     51: NC error 0x0008_0000_0000_0000
  92  *     48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
  93  *
  94  * G0..G3 - GRS mux constraints
  95  *     46-47: GRS_L2SEL value
  96  *     44-45: GRS_L3SEL value
  97  *     41-44: GRS_MCSEL value
  98  *     39-40: GRS_FABSEL value
  99  *      Note that these match up with their bit positions in MMCR1
 100  *
 101  * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
 102  *     37: UC3 error 0x20_0000_0000
 103  *     36: FPU|IFU|ISU1 events needed 0x10_0000_0000
 104  *     35: ISU0 events needed 0x08_0000_0000
 105  *     34: IDU|GRS events needed 0x04_0000_0000
 106  *
 107  * PS1
 108  *     33: PS1 error 0x2_0000_0000
 109  *     31-32: count of events needing PMC1/2 0x1_8000_0000
 110  *
 111  * PS2
 112  *     30: PS2 error 0x4000_0000
 113  *     28-29: count of events needing PMC3/4 0x3000_0000
 114  *
 115  * B0
 116  *     24-27: Byte 0 event source 0x0f00_0000
 117  *            Encoding as for the event code
 118  *
 119  * B1, B2, B3
 120  *     20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
 121  *
 122  * P1..P6
 123  *     0-11: Count of events needing PMC1..PMC6
 124  */
 125
 126 static const int grsel_shift[8] = {
 127         MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
 128         MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
 129         MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
 130 };
 131
 132 /* Masks and values for using events from the various units */
 133 static u64 unit_cons[PM_LASTUNIT+1][2] = {
 134         [PM_FPU] =   { 0xc0002000000000ull, 0x00001000000000ull },
 135         [PM_ISU0] =  { 0x00002000000000ull, 0x00000800000000ull },
 136         [PM_ISU1] =  { 0xc0002000000000ull, 0xc0001000000000ull },
 137         [PM_IFU] =   { 0xc0002000000000ull, 0x80001000000000ull },
 138         [PM_IDU] =   { 0x30002000000000ull, 0x00000400000000ull },
 139         [PM_GRS] =   { 0x30002000000000ull, 0x30000400000000ull },
 140 };
 141
 142 static int power5_get_constraint(unsigned int event, u64 *maskp, u64 *valp)
 143 {
 144         int pmc, byte, unit, sh;
 145         int bit, fmask;
 146         u64 mask = 0, value = 0;
 147         int grp = -1;
 148
 149         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 150         if (pmc) {
 151                 if (pmc > 6)
 152                         return -1;
 153                 sh = (pmc - 1) * 2;
 154                 mask |= 2 << sh;
 155                 value |= 1 << sh;
 156                 if (pmc <= 4)
 157                         grp = (pmc - 1) >> 1;
 158                 else if (event != 0x500009 && event != 0x600005)
 159                         return -1;
 160         }
 161         if (event & PM_BUSEVENT_MSK) {
 162                 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 163                 if (unit > PM_LASTUNIT)
 164                         return -1;
 165                 if (unit == PM_ISU0_ALT)
 166                         unit = PM_ISU0;
 167                 mask |= unit_cons[unit][0];
 168                 value |= unit_cons[unit][1];
 169                 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 170                 if (byte >= 4) {
 171                         if (unit != PM_LSU1)
 172                                 return -1;
 173                         /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
 174                         ++unit;
 175                         byte &= 3;
 176                 }
 177                 if (unit == PM_GRS) {
 178                         bit = event & 7;
 179                         fmask = (bit == 6)? 7: 3;
 180                         sh = grsel_shift[bit];
 181                         mask |= (u64)fmask << sh;
 182                         value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
 183                 }
 184                 /*
 185                  * Bus events on bytes 0 and 2 can be counted
 186                  * on PMC1/2; bytes 1 and 3 on PMC3/4.
 187                  */
 188                 if (!pmc)
 189                         grp = byte & 1;
 190                 /* Set byte lane select field */
 191                 mask  |= 0xfULL << (24 - 4 * byte);
 192                 value |= (u64)unit << (24 - 4 * byte);
 193         }
 194         if (grp == 0) {
 195                 /* increment PMC1/2 field */
 196                 mask  |= 0x200000000ull;
 197                 value |= 0x080000000ull;
 198         } else if (grp == 1) {
 199                 /* increment PMC3/4 field */
 200                 mask  |= 0x40000000ull;
 201                 value |= 0x10000000ull;
 202         }
 203         if (pmc < 5) {
 204                 /* need a counter from PMC1-4 set */
 205                 mask  |= 0x8000000000000ull;
 206                 value |= 0x1000000000000ull;
 207         }
 208         *maskp = mask;
 209         *valp = value;
 210         return 0;
 211 }
 212
 213 #define MAX_ALT 3       /* at most 3 alternatives for any event */
 214
 215 static const unsigned int event_alternatives[][MAX_ALT] = {
 216         { 0x120e4,  0x400002 },                 /* PM_GRP_DISP_REJECT */
 217         { 0x410c7,  0x441084 },                 /* PM_THRD_L2MISS_BOTH_CYC */
 218         { 0x100005, 0x600005 },                 /* PM_RUN_CYC */
 219         { 0x100009, 0x200009, 0x500009 },       /* PM_INST_CMPL */
 220         { 0x300009, 0x400009 },                 /* PM_INST_DISP */
 221 };
 222
 223 /*
 224  * Scan the alternatives table for a match and return the
 225  * index into the alternatives table if found, else -1.
 226  */
 227 static int find_alternative(unsigned int event)
 228 {
 229         int i, j;
 230
 231         for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
 232                 if (event < event_alternatives[i][0])
 233                         break;
 234                 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
 235                         if (event == event_alternatives[i][j])
 236                                 return i;
 237         }
 238         return -1;
 239 }
 240
 241 static const unsigned char bytedecode_alternatives[4][4] = {
 242         /* PMC 1 */     { 0x21, 0x23, 0x25, 0x27 },
 243         /* PMC 2 */     { 0x07, 0x17, 0x0e, 0x1e },
 244         /* PMC 3 */     { 0x20, 0x22, 0x24, 0x26 },
 245         /* PMC 4 */     { 0x07, 0x17, 0x0e, 0x1e }
 246 };
 247
 248 /*
 249  * Some direct events for decodes of event bus byte 3 have alternative
 250  * PMCSEL values on other counters.  This returns the alternative
 251  * event code for those that do, or -1 otherwise.
 252  */
 253 static int find_alternative_bdecode(unsigned int event)
 254 {
 255         int pmc, altpmc, pp, j;
 256
 257         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 258         if (pmc == 0 || pmc > 4)
 259                 return -1;
 260         altpmc = 5 - pmc;       /* 1 <-> 4, 2 <-> 3 */
 261         pp = event & PM_PMCSEL_MSK;
 262         for (j = 0; j < 4; ++j) {
 263                 if (bytedecode_alternatives[pmc - 1][j] == pp) {
 264                         return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
 265                                 (altpmc << PM_PMC_SH) |
 266                                 bytedecode_alternatives[altpmc - 1][j];
 267                 }
 268         }
 269         return -1;
 270 }
 271
 272 static int power5_get_alternatives(unsigned int event, unsigned int alt[])
 273 {
 274         int i, j, ae, nalt = 1;
 275
 276         alt[0] = event;
 277         nalt = 1;
 278         i = find_alternative(event);
 279         if (i >= 0) {
 280                 for (j = 0; j < MAX_ALT; ++j) {
 281                         ae = event_alternatives[i][j];
 282                         if (ae && ae != event)
 283                                 alt[nalt++] = ae;
 284                 }
 285         } else {
 286                 ae = find_alternative_bdecode(event);
 287                 if (ae > 0)
 288                         alt[nalt++] = ae;
 289         }
 290         return nalt;
 291 }
 292
 293 /*
 294  * Map of which direct events on which PMCs are marked instruction events.
 295  * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
 296  * Bit 0 is set if it is marked for all PMCs.
 297  * The 0x80 bit indicates a byte decode PMCSEL value.
 298  */
 299 static unsigned char direct_event_is_marked[0x28] = {
 300         0,      /* 00 */
 301         0x1f,   /* 01 PM_IOPS_CMPL */
 302         0x2,    /* 02 PM_MRK_GRP_DISP */
 303         0xe,    /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
 304         0,      /* 04 */
 305         0x1c,   /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
 306         0x80,   /* 06 */
 307         0x80,   /* 07 */
 308         0, 0, 0,/* 08 - 0a */
 309         0x18,   /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
 310         0,      /* 0c */
 311         0x80,   /* 0d */
 312         0x80,   /* 0e */
 313         0,      /* 0f */
 314         0,      /* 10 */
 315         0x14,   /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
 316         0,      /* 12 */
 317         0x10,   /* 13 PM_MRK_GRP_CMPL */
 318         0x1f,   /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
 319         0x2,    /* 15 PM_MRK_GRP_ISSUED */
 320         0x80,   /* 16 */
 321         0x80,   /* 17 */
 322         0, 0, 0, 0, 0,
 323         0x80,   /* 1d */
 324         0x80,   /* 1e */
 325         0,      /* 1f */
 326         0x80,   /* 20 */
 327         0x80,   /* 21 */
 328         0x80,   /* 22 */
 329         0x80,   /* 23 */
 330         0x80,   /* 24 */
 331         0x80,   /* 25 */
 332         0x80,   /* 26 */
 333         0x80,   /* 27 */
 334 };
 335
 336 /*
 337  * Returns 1 if event counts things relating to marked instructions
 338  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 339  */
 340 static int power5_marked_instr_event(unsigned int event)
 341 {
 342         int pmc, psel;
 343         int bit, byte, unit;
 344         u32 mask;
 345
 346         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 347         psel = event & PM_PMCSEL_MSK;
 348         if (pmc >= 5)
 349                 return 0;
 350
 351         bit = -1;
 352         if (psel < sizeof(direct_event_is_marked)) {
 353                 if (direct_event_is_marked[psel] & (1 << pmc))
 354                         return 1;
 355                 if (direct_event_is_marked[psel] & 0x80)
 356                         bit = 4;
 357                 else if (psel == 0x08)
 358                         bit = pmc - 1;
 359                 else if (psel == 0x10)
 360                         bit = 4 - pmc;
 361                 else if (psel == 0x1b && (pmc == 1 || pmc == 3))
 362                         bit = 4;
 363         } else if ((psel & 0x58) == 0x40)
 364                 bit = psel & 7;
 365
 366         if (!(event & PM_BUSEVENT_MSK))
 367                 return 0;
 368
 369         byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 370         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 371         if (unit == PM_LSU0) {
 372                 /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
 373                 mask = 0x5dff00;
 374         } else if (unit == PM_LSU1 && byte >= 4) {
 375                 byte -= 4;
 376                 /* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */
 377                 mask = 0x5f00c0aa;
 378         } else
 379                 return 0;
 380
 381         return (mask >> (byte * 8 + bit)) & 1;
 382 }
 383
 384 static int power5_compute_mmcr(unsigned int event[], int n_ev,
 385                                unsigned int hwc[], u64 mmcr[])
 386 {
 387         u64 mmcr1 = 0;
 388         u64 mmcra = 0;
 389         unsigned int pmc, unit, byte, psel;
 390         unsigned int ttm, grp;
 391         int i, isbus, bit, grsel;
 392         unsigned int pmc_inuse = 0;
 393         unsigned int pmc_grp_use[2];
 394         unsigned char busbyte[4];
 395         unsigned char unituse[16];
 396         int ttmuse;
 397
 398         if (n_ev > 6)
 399                 return -1;
 400
 401         /* First pass to count resource use */
 402         pmc_grp_use[0] = pmc_grp_use[1] = 0;
 403         memset(busbyte, 0, sizeof(busbyte));
 404         memset(unituse, 0, sizeof(unituse));
 405         for (i = 0; i < n_ev; ++i) {
 406                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 407                 if (pmc) {
 408                         if (pmc > 6)
 409                                 return -1;
 410                         if (pmc_inuse & (1 << (pmc - 1)))
 411                                 return -1;
 412                         pmc_inuse |= 1 << (pmc - 1);
 413                         /* count 1/2 vs 3/4 use */
 414                         if (pmc <= 4)
 415                                 ++pmc_grp_use[(pmc - 1) >> 1];
 416                 }
 417                 if (event[i] & PM_BUSEVENT_MSK) {
 418                         unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 419                         byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 420                         if (unit > PM_LASTUNIT)
 421                                 return -1;
 422                         if (unit == PM_ISU0_ALT)
 423                                 unit = PM_ISU0;
 424                         if (byte >= 4) {
 425                                 if (unit != PM_LSU1)
 426                                         return -1;
 427                                 ++unit;
 428                                 byte &= 3;
 429                         }
 430                         if (!pmc)
 431                                 ++pmc_grp_use[byte & 1];
 432                         if (busbyte[byte] && busbyte[byte] != unit)
 433                                 return -1;
 434                         busbyte[byte] = unit;
 435                         unituse[unit] = 1;
 436                 }
 437         }
 438         if (pmc_grp_use[0] > 2 || pmc_grp_use[1] > 2)
 439                 return -1;
 440
 441         /*
 442          * Assign resources and set multiplexer selects.
 443          *
 444          * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
 445          * choice we have to deal with.
 446          */
 447         if (unituse[PM_ISU0] &
 448             (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
 449                 unituse[PM_ISU0_ALT] = 1;       /* move ISU to TTM1 */
 450                 unituse[PM_ISU0] = 0;
 451         }
 452         /* Set TTM[01]SEL fields. */
 453         ttmuse = 0;
 454         for (i = PM_FPU; i <= PM_ISU1; ++i) {
 455                 if (!unituse[i])
 456                         continue;
 457                 if (ttmuse++)
 458                         return -1;
 459                 mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
 460         }
 461         ttmuse = 0;
 462         for (; i <= PM_GRS; ++i) {
 463                 if (!unituse[i])
 464                         continue;
 465                 if (ttmuse++)
 466                         return -1;
 467                 mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
 468         }
 469         if (ttmuse > 1)
 470                 return -1;
 471
 472         /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
 473         for (byte = 0; byte < 4; ++byte) {
 474                 unit = busbyte[byte];
 475                 if (!unit)
 476                         continue;
 477                 if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
 478                         /* get ISU0 through TTM1 rather than TTM0 */
 479                         unit = PM_ISU0_ALT;
 480                 } else if (unit == PM_LSU1 + 1) {
 481                         /* select lower word of LSU1 for this byte */
 482                         mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
 483                 }
 484                 ttm = unit >> 2;
 485                 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
 486         }
 487
 488         /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
 489         for (i = 0; i < n_ev; ++i) {
 490                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 491                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 492                 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 493                 psel = event[i] & PM_PMCSEL_MSK;
 494                 isbus = event[i] & PM_BUSEVENT_MSK;
 495                 if (!pmc) {
 496                         /* Bus event or any-PMC direct event */
 497                         for (pmc = 0; pmc < 4; ++pmc) {
 498                                 if (pmc_inuse & (1 << pmc))
 499                                         continue;
 500                                 grp = (pmc >> 1) & 1;
 501                                 if (isbus) {
 502                                         if (grp == (byte & 1))
 503                                                 break;
 504                                 } else if (pmc_grp_use[grp] < 2) {
 505                                         ++pmc_grp_use[grp];
 506                                         break;
 507                                 }
 508                         }
 509                         pmc_inuse |= 1 << pmc;
 510                 } else if (pmc <= 4) {
 511                         /* Direct event */
 512                         --pmc;
 513                         if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
 514                                 /* add events on higher-numbered bus */
 515                                 mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
 516                 } else {
 517                         /* Instructions or run cycles on PMC5/6 */
 518                         --pmc;
 519                 }
 520                 if (isbus && unit == PM_GRS) {
 521                         bit = psel & 7;
 522                         grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
 523                         mmcr1 |= (u64)grsel << grsel_shift[bit];
 524                 }
 525                 if (power5_marked_instr_event(event[i]))
 526                         mmcra |= MMCRA_SAMPLE_ENABLE;
 527                 if (pmc <= 3)
 528                         mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
 529                 hwc[i] = pmc;
 530         }
 531
 532         /* Return MMCRx values */
 533         mmcr[0] = 0;
 534         if (pmc_inuse & 1)
 535                 mmcr[0] = MMCR0_PMC1CE;
 536         if (pmc_inuse & 0x3e)
 537                 mmcr[0] |= MMCR0_PMCjCE;
 538         mmcr[1] = mmcr1;
 539         mmcr[2] = mmcra;
 540         return 0;
 541 }
 542
 543 static void power5_disable_pmc(unsigned int pmc, u64 mmcr[])
 544 {
 545         if (pmc <= 3)
 546                 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
 547 }
 548
 549 static int power5_generic_events[] = {
 550         [PERF_COUNT_CPU_CYCLES] = 0xf,
 551         [PERF_COUNT_INSTRUCTIONS] = 0x100009,
 552         [PERF_COUNT_CACHE_REFERENCES] = 0x4c1090,       /* LD_REF_L1 */
 553         [PERF_COUNT_CACHE_MISSES] = 0x3c1088,           /* LD_MISS_L1 */
 554         [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x230e4,     /* BR_ISSUED */
 555         [PERF_COUNT_BRANCH_MISSES] = 0x230e5,           /* BR_MPRED_CR */
 556 };
 557
 558 struct power_pmu power5_pmu = {
 559         .n_counter = 6,
 560         .max_alternatives = MAX_ALT,
 561         .add_fields = 0x7000090000555ull,
 562         .test_adder = 0x3000490000000ull,
 563         .compute_mmcr = power5_compute_mmcr,
 564         .get_constraint = power5_get_constraint,
 565         .get_alternatives = power5_get_alternatives,
 566         .disable_pmc = power5_disable_pmc,
 567         .n_generic = ARRAY_SIZE(power5_generic_events),
 568         .generic_events = power5_generic_events,
 569 };