arch/powerpc/kernel/ppc970-pmu.c

   1 /*
   2  * Performance counter support for PPC970-family processors.
   3  *
   4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/string.h>
  12 #include <linux/perf_counter.h>
  13 #include <asm/reg.h>
  14
  15 /*
  16  * Bits in event code for PPC970
  17  */
  18 #define PM_PMC_SH       12      /* PMC number (1-based) for direct events */
  19 #define PM_PMC_MSK      0xf
  20 #define PM_UNIT_SH      8       /* TTMMUX number and setting - unit select */
  21 #define PM_UNIT_MSK     0xf
  22 #define PM_SPCSEL_SH    6
  23 #define PM_SPCSEL_MSK   3
  24 #define PM_BYTE_SH      4       /* Byte number of event bus to use */
  25 #define PM_BYTE_MSK     3
  26 #define PM_PMCSEL_MSK   0xf
  27
  28 /* Values in PM_UNIT field */
  29 #define PM_NONE         0
  30 #define PM_FPU          1
  31 #define PM_VPU          2
  32 #define PM_ISU          3
  33 #define PM_IFU          4
  34 #define PM_IDU          5
  35 #define PM_STS          6
  36 #define PM_LSU0         7
  37 #define PM_LSU1U        8
  38 #define PM_LSU1L        9
  39 #define PM_LASTUNIT     9
  40
  41 /*
  42  * Bits in MMCR0 for PPC970
  43  */
  44 #define MMCR0_PMC1SEL_SH        8
  45 #define MMCR0_PMC2SEL_SH        1
  46 #define MMCR_PMCSEL_MSK         0x1f
  47
  48 /*
  49  * Bits in MMCR1 for PPC970
  50  */
  51 #define MMCR1_TTM0SEL_SH        62
  52 #define MMCR1_TTM1SEL_SH        59
  53 #define MMCR1_TTM3SEL_SH        53
  54 #define MMCR1_TTMSEL_MSK        3
  55 #define MMCR1_TD_CP_DBG0SEL_SH  50
  56 #define MMCR1_TD_CP_DBG1SEL_SH  48
  57 #define MMCR1_TD_CP_DBG2SEL_SH  46
  58 #define MMCR1_TD_CP_DBG3SEL_SH  44
  59 #define MMCR1_PMC1_ADDER_SEL_SH 39
  60 #define MMCR1_PMC2_ADDER_SEL_SH 38
  61 #define MMCR1_PMC6_ADDER_SEL_SH 37
  62 #define MMCR1_PMC5_ADDER_SEL_SH 36
  63 #define MMCR1_PMC8_ADDER_SEL_SH 35
  64 #define MMCR1_PMC7_ADDER_SEL_SH 34
  65 #define MMCR1_PMC3_ADDER_SEL_SH 33
  66 #define MMCR1_PMC4_ADDER_SEL_SH 32
  67 #define MMCR1_PMC3SEL_SH        27
  68 #define MMCR1_PMC4SEL_SH        22
  69 #define MMCR1_PMC5SEL_SH        17
  70 #define MMCR1_PMC6SEL_SH        12
  71 #define MMCR1_PMC7SEL_SH        7
  72 #define MMCR1_PMC8SEL_SH        2
  73
  74 static short mmcr1_adder_bits[8] = {
  75         MMCR1_PMC1_ADDER_SEL_SH,
  76         MMCR1_PMC2_ADDER_SEL_SH,
  77         MMCR1_PMC3_ADDER_SEL_SH,
  78         MMCR1_PMC4_ADDER_SEL_SH,
  79         MMCR1_PMC5_ADDER_SEL_SH,
  80         MMCR1_PMC6_ADDER_SEL_SH,
  81         MMCR1_PMC7_ADDER_SEL_SH,
  82         MMCR1_PMC8_ADDER_SEL_SH
  83 };
  84
  85 /*
  86  * Bits in MMCRA
  87  */
  88
  89 /*
  90  * Layout of constraint bits:
  91  * 6666555555555544444444443333333333222222222211111111110000000000
  92  * 3210987654321098765432109876543210987654321098765432109876543210
  93  *               <><><>[  >[  >[  ><  ><  ><  ><  ><><><><><><><><>
  94  *               SPT0T1 UC  PS1 PS2 B0  B1  B2  B3 P1P2P3P4P5P6P7P8
  95  *
  96  * SP - SPCSEL constraint
  97  *     48-49: SPCSEL value 0x3_0000_0000_0000
  98  *
  99  * T0 - TTM0 constraint
 100  *     46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
 101  *
 102  * T1 - TTM1 constraint
 103  *     44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
 104  *
 105  * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS
 106  *     43: UC3 error 0x0800_0000_0000
 107  *     42: FPU|IFU|VPU events needed 0x0400_0000_0000
 108  *     41: ISU events needed 0x0200_0000_0000
 109  *     40: IDU|STS events needed 0x0100_0000_0000
 110  *
 111  * PS1
 112  *     39: PS1 error 0x0080_0000_0000
 113  *     36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
 114  *
 115  * PS2
 116  *     35: PS2 error 0x0008_0000_0000
 117  *     32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
 118  *
 119  * B0
 120  *     28-31: Byte 0 event source 0xf000_0000
 121  *            Encoding as for the event code
 122  *
 123  * B1, B2, B3
 124  *     24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
 125  *
 126  * P1
 127  *     15: P1 error 0x8000
 128  *     14-15: Count of events needing PMC1
 129  *
 130  * P2..P8
 131  *     0-13: Count of events needing PMC2..PMC8
 132  */
 133
 134 static unsigned char direct_marked_event[8] = {
 135         (1<<2) | (1<<3),        /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
 136         (1<<3) | (1<<5),        /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
 137         (1<<3) | (1<<5),        /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */
 138         (1<<4) | (1<<5),        /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
 139         (1<<4) | (1<<5),        /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
 140         (1<<3) | (1<<4) | (1<<5),
 141                 /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
 142         (1<<4) | (1<<5),        /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
 143         (1<<4)                  /* PMC8: PM_MRK_LSU_FIN */
 144 };
 145
 146 /*
 147  * Returns 1 if event counts things relating to marked instructions
 148  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 149  */
 150 static int p970_marked_instr_event(unsigned int event)
 151 {
 152         int pmc, psel, unit, byte, bit;
 153         unsigned int mask;
 154
 155         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 156         psel = event & PM_PMCSEL_MSK;
 157         if (pmc) {
 158                 if (direct_marked_event[pmc - 1] & (1 << psel))
 159                         return 1;
 160                 if (psel == 0)          /* add events */
 161                         bit = (pmc <= 4)? pmc - 1: 8 - pmc;
 162                 else if (psel == 7 || psel == 13)       /* decode events */
 163                         bit = 4;
 164                 else
 165                         return 0;
 166         } else
 167                 bit = psel;
 168
 169         byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 170         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 171         mask = 0;
 172         switch (unit) {
 173         case PM_VPU:
 174                 mask = 0x4c;            /* byte 0 bits 2,3,6 */
 175         case PM_LSU0:
 176                 /* byte 2 bits 0,2,3,4,6; all of byte 1 */
 177                 mask = 0x085dff00;
 178         case PM_LSU1L:
 179                 mask = 0x50 << 24;      /* byte 3 bits 4,6 */
 180                 break;
 181         }
 182         return (mask >> (byte * 8 + bit)) & 1;
 183 }
 184
 185 /* Masks and values for using events from the various units */
 186 static u64 unit_cons[PM_LASTUNIT+1][2] = {
 187         [PM_FPU] =   { 0xc80000000000ull, 0x040000000000ull },
 188         [PM_VPU] =   { 0xc80000000000ull, 0xc40000000000ull },
 189         [PM_ISU] =   { 0x080000000000ull, 0x020000000000ull },
 190         [PM_IFU] =   { 0xc80000000000ull, 0x840000000000ull },
 191         [PM_IDU] =   { 0x380000000000ull, 0x010000000000ull },
 192         [PM_STS] =   { 0x380000000000ull, 0x310000000000ull },
 193 };
 194
 195 static int p970_get_constraint(unsigned int event, u64 *maskp, u64 *valp)
 196 {
 197         int pmc, byte, unit, sh, spcsel;
 198         u64 mask = 0, value = 0;
 199         int grp = -1;
 200
 201         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 202         if (pmc) {
 203                 if (pmc > 8)
 204                         return -1;
 205                 sh = (pmc - 1) * 2;
 206                 mask |= 2 << sh;
 207                 value |= 1 << sh;
 208                 grp = ((pmc - 1) >> 1) & 1;
 209         }
 210         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 211         if (unit) {
 212                 if (unit > PM_LASTUNIT)
 213                         return -1;
 214                 mask |= unit_cons[unit][0];
 215                 value |= unit_cons[unit][1];
 216                 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 217                 /*
 218                  * Bus events on bytes 0 and 2 can be counted
 219                  * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
 220                  */
 221                 if (!pmc)
 222                         grp = byte & 1;
 223                 /* Set byte lane select field */
 224                 mask  |= 0xfULL << (28 - 4 * byte);
 225                 value |= (u64)unit << (28 - 4 * byte);
 226         }
 227         if (grp == 0) {
 228                 /* increment PMC1/2/5/6 field */
 229                 mask  |= 0x8000000000ull;
 230                 value |= 0x1000000000ull;
 231         } else if (grp == 1) {
 232                 /* increment PMC3/4/7/8 field */
 233                 mask  |= 0x800000000ull;
 234                 value |= 0x100000000ull;
 235         }
 236         spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
 237         if (spcsel) {
 238                 mask  |= 3ull << 48;
 239                 value |= (u64)spcsel << 48;
 240         }
 241         *maskp = mask;
 242         *valp = value;
 243         return 0;
 244 }
 245
 246 static int p970_get_alternatives(unsigned int event, unsigned int alt[])
 247 {
 248         alt[0] = event;
 249
 250         /* 2 alternatives for LSU empty */
 251         if (event == 0x2002 || event == 0x3002) {
 252                 alt[1] = event ^ 0x1000;
 253                 return 2;
 254         }
 255
 256         return 1;
 257 }
 258
 259 static int p970_compute_mmcr(unsigned int event[], int n_ev,
 260                              unsigned int hwc[], u64 mmcr[])
 261 {
 262         u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0;
 263         unsigned int pmc, unit, byte, psel;
 264         unsigned int ttm, grp;
 265         unsigned int pmc_inuse = 0;
 266         unsigned int pmc_grp_use[2];
 267         unsigned char busbyte[4];
 268         unsigned char unituse[16];
 269         unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };
 270         unsigned char ttmuse[2];
 271         unsigned char pmcsel[8];
 272         int i;
 273         int spcsel;
 274
 275         if (n_ev > 8)
 276                 return -1;
 277
 278         /* First pass to count resource use */
 279         pmc_grp_use[0] = pmc_grp_use[1] = 0;
 280         memset(busbyte, 0, sizeof(busbyte));
 281         memset(unituse, 0, sizeof(unituse));
 282         for (i = 0; i < n_ev; ++i) {
 283                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 284                 if (pmc) {
 285                         if (pmc_inuse & (1 << (pmc - 1)))
 286                                 return -1;
 287                         pmc_inuse |= 1 << (pmc - 1);
 288                         /* count 1/2/5/6 vs 3/4/7/8 use */
 289                         ++pmc_grp_use[((pmc - 1) >> 1) & 1];
 290                 }
 291                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 292                 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 293                 if (unit) {
 294                         if (unit > PM_LASTUNIT)
 295                                 return -1;
 296                         if (!pmc)
 297                                 ++pmc_grp_use[byte & 1];
 298                         if (busbyte[byte] && busbyte[byte] != unit)
 299                                 return -1;
 300                         busbyte[byte] = unit;
 301                         unituse[unit] = 1;
 302                 }
 303         }
 304         if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
 305                 return -1;
 306
 307         /*
 308          * Assign resources and set multiplexer selects.
 309          *
 310          * PM_ISU can go either on TTM0 or TTM1, but that's the only
 311          * choice we have to deal with.
 312          */
 313         if (unituse[PM_ISU] &
 314             (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU]))
 315                 unitmap[PM_ISU] = 2 | 4;        /* move ISU to TTM1 */
 316         /* Set TTM[01]SEL fields. */
 317         ttmuse[0] = ttmuse[1] = 0;
 318         for (i = PM_FPU; i <= PM_STS; ++i) {
 319                 if (!unituse[i])
 320                         continue;
 321                 ttm = unitmap[i];
 322                 ++ttmuse[(ttm >> 2) & 1];
 323                 mmcr1 |= (u64)(ttm & ~4) << MMCR1_TTM1SEL_SH;
 324         }
 325         /* Check only one unit per TTMx */
 326         if (ttmuse[0] > 1 || ttmuse[1] > 1)
 327                 return -1;
 328
 329         /* Set byte lane select fields and TTM3SEL. */
 330         for (byte = 0; byte < 4; ++byte) {
 331                 unit = busbyte[byte];
 332                 if (!unit)
 333                         continue;
 334                 if (unit <= PM_STS)
 335                         ttm = (unitmap[unit] >> 2) & 1;
 336                 else if (unit == PM_LSU0)
 337                         ttm = 2;
 338                 else {
 339                         ttm = 3;
 340                         if (unit == PM_LSU1L && byte >= 2)
 341                                 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
 342                 }
 343                 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
 344         }
 345
 346         /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
 347         memset(pmcsel, 0x8, sizeof(pmcsel));    /* 8 means don't count */
 348         for (i = 0; i < n_ev; ++i) {
 349                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 350                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 351                 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 352                 psel = event[i] & PM_PMCSEL_MSK;
 353                 if (!pmc) {
 354                         /* Bus event or any-PMC direct event */
 355                         if (unit)
 356                                 psel |= 0x10 | ((byte & 2) << 2);
 357                         else
 358                                 psel |= 8;
 359                         for (pmc = 0; pmc < 8; ++pmc) {
 360                                 if (pmc_inuse & (1 << pmc))
 361                                         continue;
 362                                 grp = (pmc >> 1) & 1;
 363                                 if (unit) {
 364                                         if (grp == (byte & 1))
 365                                                 break;
 366                                 } else if (pmc_grp_use[grp] < 4) {
 367                                         ++pmc_grp_use[grp];
 368                                         break;
 369                                 }
 370                         }
 371                         pmc_inuse |= 1 << pmc;
 372                 } else {
 373                         /* Direct event */
 374                         --pmc;
 375                         if (psel == 0 && (byte & 2))
 376                                 /* add events on higher-numbered bus */
 377                                 mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
 378                 }
 379                 pmcsel[pmc] = psel;
 380                 hwc[i] = pmc;
 381                 spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
 382                 mmcr1 |= spcsel;
 383                 if (p970_marked_instr_event(event[i]))
 384                         mmcra |= MMCRA_SAMPLE_ENABLE;
 385         }
 386         for (pmc = 0; pmc < 2; ++pmc)
 387                 mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
 388         for (; pmc < 8; ++pmc)
 389                 mmcr1 |= (u64)pmcsel[pmc] << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
 390         if (pmc_inuse & 1)
 391                 mmcr0 |= MMCR0_PMC1CE;
 392         if (pmc_inuse & 0xfe)
 393                 mmcr0 |= MMCR0_PMCjCE;
 394
 395         mmcra |= 0x2000;        /* mark only one IOP per PPC instruction */
 396
 397         /* Return MMCRx values */
 398         mmcr[0] = mmcr0;
 399         mmcr[1] = mmcr1;
 400         mmcr[2] = mmcra;
 401         return 0;
 402 }
 403
 404 static void p970_disable_pmc(unsigned int pmc, u64 mmcr[])
 405 {
 406         int shift, i;
 407
 408         if (pmc <= 1) {
 409                 shift = MMCR0_PMC1SEL_SH - 7 * pmc;
 410                 i = 0;
 411         } else {
 412                 shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
 413                 i = 1;
 414         }
 415         /*
 416          * Setting the PMCxSEL field to 0x08 disables PMC x.
 417          */
 418         mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift);
 419 }
 420
 421 static int ppc970_generic_events[] = {
 422         [PERF_COUNT_CPU_CYCLES] = 7,
 423         [PERF_COUNT_INSTRUCTIONS] = 1,
 424         [PERF_COUNT_CACHE_REFERENCES] = 0x8810,         /* PM_LD_REF_L1 */
 425         [PERF_COUNT_CACHE_MISSES] = 0x3810,             /* PM_LD_MISS_L1 */
 426         [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x431,       /* PM_BR_ISSUED */
 427         [PERF_COUNT_BRANCH_MISSES] = 0x327,             /* PM_GRP_BR_MPRED */
 428 };
 429
 430 struct power_pmu ppc970_pmu = {
 431         .n_counter = 8,
 432         .max_alternatives = 2,
 433         .add_fields = 0x001100005555ull,
 434         .test_adder = 0x013300000000ull,
 435         .compute_mmcr = p970_compute_mmcr,
 436         .get_constraint = p970_get_constraint,
 437         .get_alternatives = p970_get_alternatives,
 438         .disable_pmc = p970_disable_pmc,
 439         .n_generic = ARRAY_SIZE(ppc970_generic_events),
 440         .generic_events = ppc970_generic_events,
 441 };