2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/init.h>
29 #include <linux/prctl.h>
30 #include <linux/init_task.h>
31 #include <linux/export.h>
32 #include <linux/kallsyms.h>
33 #include <linux/mqueue.h>
34 #include <linux/hardirq.h>
35 #include <linux/utsname.h>
36 #include <linux/ftrace.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/personality.h>
39 #include <linux/random.h>
40 #include <linux/hw_breakpoint.h>
42 #include <asm/pgtable.h>
43 #include <asm/uaccess.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
58 #include <linux/kprobes.h>
59 #include <linux/kdebug.h>
61 /* Transactional Memory debug */
63 #define TM_DEBUG(x...) printk(KERN_INFO x)
65 #define TM_DEBUG(x...) do { } while(0)
68 extern unsigned long _get_SP(void);
71 struct task_struct
*last_task_used_math
= NULL
;
72 struct task_struct
*last_task_used_altivec
= NULL
;
73 struct task_struct
*last_task_used_vsx
= NULL
;
74 struct task_struct
*last_task_used_spe
= NULL
;
79 * Make sure the floating-point register state in the
80 * the thread_struct is up to date for task tsk.
82 void flush_fp_to_thread(struct task_struct
*tsk
)
84 if (tsk
->thread
.regs
) {
86 * We need to disable preemption here because if we didn't,
87 * another process could get scheduled after the regs->msr
88 * test but before we have finished saving the FP registers
89 * to the thread_struct. That process could take over the
90 * FPU, and then when we get scheduled again we would store
91 * bogus values for the remaining FP registers.
94 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
97 * This should only ever be called for current or
98 * for a stopped child process. Since we save away
99 * the FP register state on context switch on SMP,
100 * there is something wrong if a stopped child appears
101 * to still have its FP state in the CPU registers.
103 BUG_ON(tsk
!= current
);
110 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
113 void enable_kernel_fp(void)
115 WARN_ON(preemptible());
118 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
))
121 giveup_fpu(NULL
); /* just enables FP for kernel */
123 giveup_fpu(last_task_used_math
);
124 #endif /* CONFIG_SMP */
126 EXPORT_SYMBOL(enable_kernel_fp
);
128 #ifdef CONFIG_ALTIVEC
129 void enable_kernel_altivec(void)
131 WARN_ON(preemptible());
134 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
))
135 giveup_altivec(current
);
137 giveup_altivec_notask();
139 giveup_altivec(last_task_used_altivec
);
140 #endif /* CONFIG_SMP */
142 EXPORT_SYMBOL(enable_kernel_altivec
);
145 * Make sure the VMX/Altivec register state in the
146 * the thread_struct is up to date for task tsk.
148 void flush_altivec_to_thread(struct task_struct
*tsk
)
150 if (tsk
->thread
.regs
) {
152 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
154 BUG_ON(tsk
!= current
);
161 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
162 #endif /* CONFIG_ALTIVEC */
166 /* not currently used, but some crazy RAID module might want to later */
167 void enable_kernel_vsx(void)
169 WARN_ON(preemptible());
172 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
))
175 giveup_vsx(NULL
); /* just enable vsx for kernel - force */
177 giveup_vsx(last_task_used_vsx
);
178 #endif /* CONFIG_SMP */
180 EXPORT_SYMBOL(enable_kernel_vsx
);
183 void giveup_vsx(struct task_struct
*tsk
)
190 void flush_vsx_to_thread(struct task_struct
*tsk
)
192 if (tsk
->thread
.regs
) {
194 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
196 BUG_ON(tsk
!= current
);
203 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
204 #endif /* CONFIG_VSX */
208 void enable_kernel_spe(void)
210 WARN_ON(preemptible());
213 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
))
216 giveup_spe(NULL
); /* just enable SPE for kernel - force */
218 giveup_spe(last_task_used_spe
);
219 #endif /* __SMP __ */
221 EXPORT_SYMBOL(enable_kernel_spe
);
223 void flush_spe_to_thread(struct task_struct
*tsk
)
225 if (tsk
->thread
.regs
) {
227 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
229 BUG_ON(tsk
!= current
);
231 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
237 #endif /* CONFIG_SPE */
241 * If we are doing lazy switching of CPU state (FP, altivec or SPE),
242 * and the current task has some state, discard it.
244 void discard_lazy_cpu_state(void)
247 if (last_task_used_math
== current
)
248 last_task_used_math
= NULL
;
249 #ifdef CONFIG_ALTIVEC
250 if (last_task_used_altivec
== current
)
251 last_task_used_altivec
= NULL
;
252 #endif /* CONFIG_ALTIVEC */
254 if (last_task_used_vsx
== current
)
255 last_task_used_vsx
= NULL
;
256 #endif /* CONFIG_VSX */
258 if (last_task_used_spe
== current
)
259 last_task_used_spe
= NULL
;
263 #endif /* CONFIG_SMP */
265 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
266 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
267 unsigned long error_code
, int signal_code
, int breakpt
)
271 current
->thread
.trap_nr
= signal_code
;
272 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
273 11, SIGSEGV
) == NOTIFY_STOP
)
276 /* Deliver the signal to userspace */
277 info
.si_signo
= SIGTRAP
;
278 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
279 info
.si_code
= signal_code
;
280 info
.si_addr
= (void __user
*)address
;
281 force_sig_info(SIGTRAP
, &info
, current
);
283 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
284 void do_break (struct pt_regs
*regs
, unsigned long address
,
285 unsigned long error_code
)
289 current
->thread
.trap_nr
= TRAP_HWBKPT
;
290 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
291 11, SIGSEGV
) == NOTIFY_STOP
)
294 if (debugger_break_match(regs
))
297 /* Clear the breakpoint */
298 hw_breakpoint_disable();
300 /* Deliver the signal to userspace */
301 info
.si_signo
= SIGTRAP
;
303 info
.si_code
= TRAP_HWBKPT
;
304 info
.si_addr
= (void __user
*)address
;
305 force_sig_info(SIGTRAP
, &info
, current
);
307 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
309 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
311 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
313 * Set the debug registers back to their default "safe" values.
315 static void set_debug_reg_defaults(struct thread_struct
*thread
)
317 thread
->iac1
= thread
->iac2
= 0;
318 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
319 thread
->iac3
= thread
->iac4
= 0;
321 thread
->dac1
= thread
->dac2
= 0;
322 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
323 thread
->dvc1
= thread
->dvc2
= 0;
328 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
330 thread
->dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
| \
331 DBCR1_IAC3US
| DBCR1_IAC4US
;
333 * Force Data Address Compare User/Supervisor bits to be User-only
334 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
336 thread
->dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
342 static void prime_debug_regs(struct thread_struct
*thread
)
345 * We could have inherited MSR_DE from userspace, since
346 * it doesn't get cleared on exception entry. Make sure
347 * MSR_DE is clear before we enable any debug events.
349 mtmsr(mfmsr() & ~MSR_DE
);
351 mtspr(SPRN_IAC1
, thread
->iac1
);
352 mtspr(SPRN_IAC2
, thread
->iac2
);
353 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
354 mtspr(SPRN_IAC3
, thread
->iac3
);
355 mtspr(SPRN_IAC4
, thread
->iac4
);
357 mtspr(SPRN_DAC1
, thread
->dac1
);
358 mtspr(SPRN_DAC2
, thread
->dac2
);
359 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
360 mtspr(SPRN_DVC1
, thread
->dvc1
);
361 mtspr(SPRN_DVC2
, thread
->dvc2
);
363 mtspr(SPRN_DBCR0
, thread
->dbcr0
);
364 mtspr(SPRN_DBCR1
, thread
->dbcr1
);
366 mtspr(SPRN_DBCR2
, thread
->dbcr2
);
370 * Unless neither the old or new thread are making use of the
371 * debug registers, set the debug registers from the values
372 * stored in the new thread.
374 static void switch_booke_debug_regs(struct thread_struct
*new_thread
)
376 if ((current
->thread
.dbcr0
& DBCR0_IDM
)
377 || (new_thread
->dbcr0
& DBCR0_IDM
))
378 prime_debug_regs(new_thread
);
380 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
381 #ifndef CONFIG_HAVE_HW_BREAKPOINT
382 static void set_debug_reg_defaults(struct thread_struct
*thread
)
384 thread
->hw_brk
.address
= 0;
385 thread
->hw_brk
.type
= 0;
386 set_breakpoint(&thread
->hw_brk
);
388 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
389 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
391 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
392 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
394 mtspr(SPRN_DAC1
, dabr
);
395 #ifdef CONFIG_PPC_47x
400 #elif defined(CONFIG_PPC_BOOK3S)
401 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
403 mtspr(SPRN_DABR
, dabr
);
404 if (cpu_has_feature(CPU_FTR_DABRX
))
405 mtspr(SPRN_DABRX
, dabrx
);
409 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
415 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
417 unsigned long dabr
, dabrx
;
419 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
420 dabrx
= ((brk
->type
>> 3) & 0x7);
423 return ppc_md
.set_dabr(dabr
, dabrx
);
425 return __set_dabr(dabr
, dabrx
);
428 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
430 unsigned long dawr
, dawrx
, mrd
;
434 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
435 << (63 - 58); //* read/write bits */
436 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
437 << (63 - 59); //* translate */
438 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
439 >> 3; //* PRIM bits */
440 /* dawr length is stored in field MDR bits 48:53. Matches range in
441 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
443 brk->len is in bytes.
444 This aligns up to double word size, shifts and does the bias.
446 mrd
= ((brk
->len
+ 7) >> 3) - 1;
447 dawrx
|= (mrd
& 0x3f) << (63 - 53);
450 return ppc_md
.set_dawr(dawr
, dawrx
);
451 mtspr(SPRN_DAWR
, dawr
);
452 mtspr(SPRN_DAWRX
, dawrx
);
456 int set_breakpoint(struct arch_hw_breakpoint
*brk
)
458 __get_cpu_var(current_brk
) = *brk
;
460 if (cpu_has_feature(CPU_FTR_DAWR
))
461 return set_dawr(brk
);
463 return set_dabr(brk
);
467 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
470 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
471 struct arch_hw_breakpoint
*b
)
473 if (a
->address
!= b
->address
)
475 if (a
->type
!= b
->type
)
477 if (a
->len
!= b
->len
)
481 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
482 static inline void tm_reclaim_task(struct task_struct
*tsk
)
484 /* We have to work out if we're switching from/to a task that's in the
485 * middle of a transaction.
487 * In switching we need to maintain a 2nd register state as
488 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
489 * checkpointed (tbegin) state in ckpt_regs and saves the transactional
490 * (current) FPRs into oldtask->thread.transact_fpr[].
492 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
494 struct thread_struct
*thr
= &tsk
->thread
;
499 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
500 goto out_and_saveregs
;
502 /* Stash the original thread MSR, as giveup_fpu et al will
503 * modify it. We hold onto it to see whether the task used
506 thr
->tm_orig_msr
= thr
->regs
->msr
;
508 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
509 "ccr=%lx, msr=%lx, trap=%lx)\n",
510 tsk
->pid
, thr
->regs
->nip
,
511 thr
->regs
->ccr
, thr
->regs
->msr
,
514 tm_reclaim(thr
, thr
->regs
->msr
, TM_CAUSE_RESCHED
);
516 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
520 /* Always save the regs here, even if a transaction's not active.
521 * This context-switches a thread's TM info SPRs. We do it here to
522 * be consistent with the restore path (in recheckpoint) which
523 * cannot happen later in _switch().
528 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
532 if (!cpu_has_feature(CPU_FTR_TM
))
535 /* Recheckpoint the registers of the thread we're about to switch to.
537 * If the task was using FP, we non-lazily reload both the original and
538 * the speculative FP register states. This is because the kernel
539 * doesn't see if/when a TM rollback occurs, so if we take an FP
540 * unavoidable later, we are unable to determine which set of FP regs
541 * need to be restored.
543 if (!new->thread
.regs
)
546 /* The TM SPRs are restored here, so that TEXASR.FS can be set
547 * before the trecheckpoint and no explosion occurs.
549 tm_restore_sprs(&new->thread
);
551 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
))
553 msr
= new->thread
.tm_orig_msr
;
554 /* Recheckpoint to restore original checkpointed register state. */
555 TM_DEBUG("*** tm_recheckpoint of pid %d "
556 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
557 new->pid
, new->thread
.regs
->msr
, msr
);
559 /* This loads the checkpointed FP/VEC state, if used */
560 tm_recheckpoint(&new->thread
, msr
);
562 /* This loads the speculative FP/VEC state, if used */
564 do_load_up_transact_fpu(&new->thread
);
565 new->thread
.regs
->msr
|=
566 (MSR_FP
| new->thread
.fpexc_mode
);
568 #ifdef CONFIG_ALTIVEC
570 do_load_up_transact_altivec(&new->thread
);
571 new->thread
.regs
->msr
|= MSR_VEC
;
574 /* We may as well turn on VSX too since all the state is restored now */
576 new->thread
.regs
->msr
|= MSR_VSX
;
578 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
579 "(kernel msr 0x%lx)\n",
583 static inline void __switch_to_tm(struct task_struct
*prev
)
585 if (cpu_has_feature(CPU_FTR_TM
)) {
587 tm_reclaim_task(prev
);
591 #define tm_recheckpoint_new_task(new)
592 #define __switch_to_tm(prev)
593 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
595 struct task_struct
*__switch_to(struct task_struct
*prev
,
596 struct task_struct
*new)
598 struct thread_struct
*new_thread
, *old_thread
;
600 struct task_struct
*last
;
601 #ifdef CONFIG_PPC_BOOK3S_64
602 struct ppc64_tlb_batch
*batch
;
605 /* Back up the TAR across context switches.
606 * Note that the TAR is not available for use in the kernel. (To
607 * provide this, the TAR should be backed up/restored on exception
608 * entry/exit instead, and be in pt_regs. FIXME, this should be in
609 * pt_regs anyway (for debug).)
610 * Save the TAR here before we do treclaim/trecheckpoint as these
611 * will change the TAR.
613 save_tar(&prev
->thread
);
615 __switch_to_tm(prev
);
618 /* avoid complexity of lazy save/restore of fpu
619 * by just saving it every time we switch out if
620 * this task used the fpu during the last quantum.
622 * If it tries to use the fpu again, it'll trap and
623 * reload its fp regs. So we don't have to do a restore
624 * every switch, just a save.
627 if (prev
->thread
.regs
&& (prev
->thread
.regs
->msr
& MSR_FP
))
629 #ifdef CONFIG_ALTIVEC
631 * If the previous thread used altivec in the last quantum
632 * (thus changing altivec regs) then save them.
633 * We used to check the VRSAVE register but not all apps
634 * set it, so we don't rely on it now (and in fact we need
635 * to save & restore VSCR even if VRSAVE == 0). -- paulus
637 * On SMP we always save/restore altivec regs just to avoid the
638 * complexity of changing processors.
641 if (prev
->thread
.regs
&& (prev
->thread
.regs
->msr
& MSR_VEC
))
642 giveup_altivec(prev
);
643 #endif /* CONFIG_ALTIVEC */
645 if (prev
->thread
.regs
&& (prev
->thread
.regs
->msr
& MSR_VSX
))
646 /* VMX and FPU registers are already save here */
648 #endif /* CONFIG_VSX */
651 * If the previous thread used spe in the last quantum
652 * (thus changing spe regs) then save them.
654 * On SMP we always save/restore spe regs just to avoid the
655 * complexity of changing processors.
657 if ((prev
->thread
.regs
&& (prev
->thread
.regs
->msr
& MSR_SPE
)))
659 #endif /* CONFIG_SPE */
661 #else /* CONFIG_SMP */
662 #ifdef CONFIG_ALTIVEC
663 /* Avoid the trap. On smp this this never happens since
664 * we don't set last_task_used_altivec -- Cort
666 if (new->thread
.regs
&& last_task_used_altivec
== new)
667 new->thread
.regs
->msr
|= MSR_VEC
;
668 #endif /* CONFIG_ALTIVEC */
670 if (new->thread
.regs
&& last_task_used_vsx
== new)
671 new->thread
.regs
->msr
|= MSR_VSX
;
672 #endif /* CONFIG_VSX */
674 /* Avoid the trap. On smp this this never happens since
675 * we don't set last_task_used_spe
677 if (new->thread
.regs
&& last_task_used_spe
== new)
678 new->thread
.regs
->msr
|= MSR_SPE
;
679 #endif /* CONFIG_SPE */
681 #endif /* CONFIG_SMP */
683 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
684 switch_booke_debug_regs(&new->thread
);
687 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
690 #ifndef CONFIG_HAVE_HW_BREAKPOINT
691 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk
), &new->thread
.hw_brk
)))
692 set_breakpoint(&new->thread
.hw_brk
);
693 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
697 new_thread
= &new->thread
;
698 old_thread
= ¤t
->thread
;
702 * Collect processor utilization data per process
704 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
705 struct cpu_usage
*cu
= &__get_cpu_var(cpu_usage_array
);
706 long unsigned start_tb
, current_tb
;
707 start_tb
= old_thread
->start_tb
;
708 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
709 old_thread
->accum_tb
+= (current_tb
- start_tb
);
710 new_thread
->start_tb
= current_tb
;
712 #endif /* CONFIG_PPC64 */
714 #ifdef CONFIG_PPC_BOOK3S_64
715 batch
= &__get_cpu_var(ppc64_tlb_batch
);
717 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
719 __flush_tlb_pending(batch
);
722 #endif /* CONFIG_PPC_BOOK3S_64 */
724 local_irq_save(flags
);
727 * We can't take a PMU exception inside _switch() since there is a
728 * window where the kernel stack SLB and the kernel stack are out
729 * of sync. Hard disable here.
733 tm_recheckpoint_new_task(new);
735 last
= _switch(old_thread
, new_thread
);
737 #ifdef CONFIG_PPC_BOOK3S_64
738 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
739 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
740 batch
= &__get_cpu_var(ppc64_tlb_batch
);
743 #endif /* CONFIG_PPC_BOOK3S_64 */
745 local_irq_restore(flags
);
750 static int instructions_to_print
= 16;
752 static void show_instructions(struct pt_regs
*regs
)
755 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
758 printk("Instruction dump:");
760 for (i
= 0; i
< instructions_to_print
; i
++) {
766 #if !defined(CONFIG_BOOKE)
767 /* If executing with the IMMU off, adjust pc rather
768 * than print XXXXXXXX.
770 if (!(regs
->msr
& MSR_IR
))
771 pc
= (unsigned long)phys_to_virt(pc
);
774 /* We use __get_user here *only* to avoid an OOPS on a
775 * bad address because the pc *should* only be a
778 if (!__kernel_text_address(pc
) ||
779 __get_user(instr
, (unsigned int __user
*)pc
)) {
780 printk(KERN_CONT
"XXXXXXXX ");
783 printk(KERN_CONT
"<%08x> ", instr
);
785 printk(KERN_CONT
"%08x ", instr
);
794 static struct regbit
{
798 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
827 static void printbits(unsigned long val
, struct regbit
*bits
)
829 const char *sep
= "";
832 for (; bits
->bit
; ++bits
)
833 if (val
& bits
->bit
) {
834 printk("%s%s", sep
, bits
->name
);
842 #define REGS_PER_LINE 4
843 #define LAST_VOLATILE 13
846 #define REGS_PER_LINE 8
847 #define LAST_VOLATILE 12
850 void show_regs(struct pt_regs
* regs
)
854 show_regs_print_info(KERN_DEFAULT
);
856 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
857 regs
->nip
, regs
->link
, regs
->ctr
);
858 printk("REGS: %p TRAP: %04lx %s (%s)\n",
859 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
860 printk("MSR: "REG
" ", regs
->msr
);
861 printbits(regs
->msr
, msr_bits
);
862 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
864 printk("SOFTE: %ld\n", regs
->softe
);
867 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
868 printk("CFAR: "REG
"\n", regs
->orig_gpr3
);
869 if (trap
== 0x300 || trap
== 0x600)
870 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
871 printk("DEAR: "REG
", ESR: "REG
"\n", regs
->dar
, regs
->dsisr
);
873 printk("DAR: "REG
", DSISR: %08lx\n", regs
->dar
, regs
->dsisr
);
876 for (i
= 0; i
< 32; i
++) {
877 if ((i
% REGS_PER_LINE
) == 0)
878 printk("\nGPR%02d: ", i
);
879 printk(REG
" ", regs
->gpr
[i
]);
880 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
884 #ifdef CONFIG_KALLSYMS
886 * Lookup NIP late so we have the best change of getting the
887 * above info out without failing
889 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
890 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
892 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
893 printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch
);
895 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
896 if (!user_mode(regs
))
897 show_instructions(regs
);
900 void exit_thread(void)
902 discard_lazy_cpu_state();
905 void flush_thread(void)
907 discard_lazy_cpu_state();
909 #ifdef CONFIG_HAVE_HW_BREAKPOINT
910 flush_ptrace_hw_breakpoint(current
);
911 #else /* CONFIG_HAVE_HW_BREAKPOINT */
912 set_debug_reg_defaults(¤t
->thread
);
913 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
917 release_thread(struct task_struct
*t
)
922 * this gets called so that we can store coprocessor state into memory and
923 * copy the current task into the new thread.
925 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
927 flush_fp_to_thread(src
);
928 flush_altivec_to_thread(src
);
929 flush_vsx_to_thread(src
);
930 flush_spe_to_thread(src
);
942 extern unsigned long dscr_default
; /* defined in arch/powerpc/kernel/sysfs.c */
944 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
945 unsigned long arg
, struct task_struct
*p
)
947 struct pt_regs
*childregs
, *kregs
;
948 extern void ret_from_fork(void);
949 extern void ret_from_kernel_thread(void);
951 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
954 sp
-= sizeof(struct pt_regs
);
955 childregs
= (struct pt_regs
*) sp
;
956 if (unlikely(p
->flags
& PF_KTHREAD
)) {
957 struct thread_info
*ti
= (void *)task_stack_page(p
);
958 memset(childregs
, 0, sizeof(struct pt_regs
));
959 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
960 childregs
->gpr
[14] = usp
; /* function */
962 clear_tsk_thread_flag(p
, TIF_32BIT
);
963 childregs
->softe
= 1;
965 childregs
->gpr
[15] = arg
;
966 p
->thread
.regs
= NULL
; /* no user register state */
967 ti
->flags
|= _TIF_RESTOREALL
;
968 f
= ret_from_kernel_thread
;
970 struct pt_regs
*regs
= current_pt_regs();
971 CHECK_FULL_REGS(regs
);
974 childregs
->gpr
[1] = usp
;
975 p
->thread
.regs
= childregs
;
976 childregs
->gpr
[3] = 0; /* Result from fork() */
977 if (clone_flags
& CLONE_SETTLS
) {
979 if (!is_32bit_task())
980 childregs
->gpr
[13] = childregs
->gpr
[6];
983 childregs
->gpr
[2] = childregs
->gpr
[6];
988 sp
-= STACK_FRAME_OVERHEAD
;
991 * The way this works is that at some point in the future
992 * some task will call _switch to switch to the new task.
993 * That will pop off the stack frame created below and start
994 * the new task running at ret_from_fork. The new task will
995 * do some house keeping and then return from the fork or clone
996 * system call, using the stack frame created above.
998 ((unsigned long *)sp
)[0] = 0;
999 sp
-= sizeof(struct pt_regs
);
1000 kregs
= (struct pt_regs
*) sp
;
1001 sp
-= STACK_FRAME_OVERHEAD
;
1004 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1005 _ALIGN_UP(sizeof(struct thread_info
), 16);
1007 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1008 p
->thread
.ptrace_bps
[0] = NULL
;
1011 #ifdef CONFIG_PPC_STD_MMU_64
1012 if (mmu_has_feature(MMU_FTR_SLB
)) {
1013 unsigned long sp_vsid
;
1014 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1016 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1017 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1018 << SLB_VSID_SHIFT_1T
;
1020 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1022 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1023 p
->thread
.ksp_vsid
= sp_vsid
;
1025 #endif /* CONFIG_PPC_STD_MMU_64 */
1027 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1028 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1029 p
->thread
.dscr
= current
->thread
.dscr
;
1031 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1032 p
->thread
.ppr
= INIT_PPR
;
1035 * The PPC64 ABI makes use of a TOC to contain function
1036 * pointers. The function (ret_from_except) is actually a pointer
1037 * to the TOC entry. The first entry is a pointer to the actual
1041 kregs
->nip
= *((unsigned long *)f
);
1043 kregs
->nip
= (unsigned long)f
;
1049 * Set up a thread for executing a new program
1051 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1054 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1058 * If we exec out of a kernel thread then thread.regs will not be
1061 if (!current
->thread
.regs
) {
1062 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1063 current
->thread
.regs
= regs
- 1;
1066 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1074 * We have just cleared all the nonvolatile GPRs, so make
1075 * FULL_REGS(regs) return true. This is necessary to allow
1076 * ptrace to examine the thread immediately after exec.
1083 regs
->msr
= MSR_USER
;
1085 if (!is_32bit_task()) {
1086 unsigned long entry
, toc
;
1088 /* start is a relocated pointer to the function descriptor for
1089 * the elf _start routine. The first entry in the function
1090 * descriptor is the entry address of _start and the second
1091 * entry is the TOC value we need to use.
1093 __get_user(entry
, (unsigned long __user
*)start
);
1094 __get_user(toc
, (unsigned long __user
*)start
+1);
1096 /* Check whether the e_entry function descriptor entries
1097 * need to be relocated before we can use them.
1099 if (load_addr
!= 0) {
1105 regs
->msr
= MSR_USER64
;
1109 regs
->msr
= MSR_USER32
;
1112 discard_lazy_cpu_state();
1114 current
->thread
.used_vsr
= 0;
1116 memset(current
->thread
.fpr
, 0, sizeof(current
->thread
.fpr
));
1117 current
->thread
.fpscr
.val
= 0;
1118 #ifdef CONFIG_ALTIVEC
1119 memset(current
->thread
.vr
, 0, sizeof(current
->thread
.vr
));
1120 memset(¤t
->thread
.vscr
, 0, sizeof(current
->thread
.vscr
));
1121 current
->thread
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1122 current
->thread
.vrsave
= 0;
1123 current
->thread
.used_vr
= 0;
1124 #endif /* CONFIG_ALTIVEC */
1126 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1127 current
->thread
.acc
= 0;
1128 current
->thread
.spefscr
= 0;
1129 current
->thread
.used_spe
= 0;
1130 #endif /* CONFIG_SPE */
1131 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1132 if (cpu_has_feature(CPU_FTR_TM
))
1133 regs
->msr
|= MSR_TM
;
1134 current
->thread
.tm_tfhar
= 0;
1135 current
->thread
.tm_texasr
= 0;
1136 current
->thread
.tm_tfiar
= 0;
1137 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1140 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1141 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1143 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1145 struct pt_regs
*regs
= tsk
->thread
.regs
;
1147 /* This is a bit hairy. If we are an SPE enabled processor
1148 * (have embedded fp) we store the IEEE exception enable flags in
1149 * fpexc_mode. fpexc_mode is also used for setting FP exception
1150 * mode (asyn, precise, disabled) for 'Classic' FP. */
1151 if (val
& PR_FP_EXC_SW_ENABLE
) {
1153 if (cpu_has_feature(CPU_FTR_SPE
)) {
1154 tsk
->thread
.fpexc_mode
= val
&
1155 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1165 /* on a CONFIG_SPE this does not hurt us. The bits that
1166 * __pack_fe01 use do not overlap with bits used for
1167 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1168 * on CONFIG_SPE implementations are reserved so writing to
1169 * them does not change anything */
1170 if (val
> PR_FP_EXC_PRECISE
)
1172 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1173 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1174 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1175 | tsk
->thread
.fpexc_mode
;
1179 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1183 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1185 if (cpu_has_feature(CPU_FTR_SPE
))
1186 val
= tsk
->thread
.fpexc_mode
;
1193 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1194 return put_user(val
, (unsigned int __user
*) adr
);
1197 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1199 struct pt_regs
*regs
= tsk
->thread
.regs
;
1201 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1202 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1208 if (val
== PR_ENDIAN_BIG
)
1209 regs
->msr
&= ~MSR_LE
;
1210 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1211 regs
->msr
|= MSR_LE
;
1218 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1220 struct pt_regs
*regs
= tsk
->thread
.regs
;
1223 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1224 !cpu_has_feature(CPU_FTR_REAL_LE
))
1230 if (regs
->msr
& MSR_LE
) {
1231 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1232 val
= PR_ENDIAN_LITTLE
;
1234 val
= PR_ENDIAN_PPC_LITTLE
;
1236 val
= PR_ENDIAN_BIG
;
1238 return put_user(val
, (unsigned int __user
*)adr
);
1241 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1243 tsk
->thread
.align_ctl
= val
;
1247 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1249 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1252 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1253 unsigned long nbytes
)
1255 unsigned long stack_page
;
1256 unsigned long cpu
= task_cpu(p
);
1259 * Avoid crashing if the stack has overflowed and corrupted
1260 * task_cpu(p), which is in the thread_info struct.
1262 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1263 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1264 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1265 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1268 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1269 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1270 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1276 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1277 unsigned long nbytes
)
1279 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1281 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1282 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1285 return valid_irq_stack(sp
, p
, nbytes
);
1288 EXPORT_SYMBOL(validate_sp
);
1290 unsigned long get_wchan(struct task_struct
*p
)
1292 unsigned long ip
, sp
;
1295 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1299 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1303 sp
= *(unsigned long *)sp
;
1304 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1307 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1308 if (!in_sched_functions(ip
))
1311 } while (count
++ < 16);
1315 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1317 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1319 unsigned long sp
, ip
, lr
, newsp
;
1322 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1323 int curr_frame
= current
->curr_ret_stack
;
1324 extern void return_to_handler(void);
1325 unsigned long rth
= (unsigned long)return_to_handler
;
1326 unsigned long mrth
= -1;
1328 extern void mod_return_to_handler(void);
1329 rth
= *(unsigned long *)rth
;
1330 mrth
= (unsigned long)mod_return_to_handler
;
1331 mrth
= *(unsigned long *)mrth
;
1335 sp
= (unsigned long) stack
;
1340 asm("mr %0,1" : "=r" (sp
));
1342 sp
= tsk
->thread
.ksp
;
1346 printk("Call Trace:\n");
1348 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1351 stack
= (unsigned long *) sp
;
1353 ip
= stack
[STACK_FRAME_LR_SAVE
];
1354 if (!firstframe
|| ip
!= lr
) {
1355 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1356 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1357 if ((ip
== rth
|| ip
== mrth
) && curr_frame
>= 0) {
1359 (void *)current
->ret_stack
[curr_frame
].ret
);
1364 printk(" (unreliable)");
1370 * See if this is an exception frame.
1371 * We look for the "regshere" marker in the current frame.
1373 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1374 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1375 struct pt_regs
*regs
= (struct pt_regs
*)
1376 (sp
+ STACK_FRAME_OVERHEAD
);
1378 printk("--- Exception: %lx at %pS\n LR = %pS\n",
1379 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1384 } while (count
++ < kstack_depth_to_print
);
1388 /* Called with hard IRQs off */
1389 void notrace
__ppc64_runlatch_on(void)
1391 struct thread_info
*ti
= current_thread_info();
1394 ctrl
= mfspr(SPRN_CTRLF
);
1395 ctrl
|= CTRL_RUNLATCH
;
1396 mtspr(SPRN_CTRLT
, ctrl
);
1398 ti
->local_flags
|= _TLF_RUNLATCH
;
1401 /* Called with hard IRQs off */
1402 void notrace
__ppc64_runlatch_off(void)
1404 struct thread_info
*ti
= current_thread_info();
1407 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1409 ctrl
= mfspr(SPRN_CTRLF
);
1410 ctrl
&= ~CTRL_RUNLATCH
;
1411 mtspr(SPRN_CTRLT
, ctrl
);
1413 #endif /* CONFIG_PPC64 */
1415 unsigned long arch_align_stack(unsigned long sp
)
1417 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1418 sp
-= get_random_int() & ~PAGE_MASK
;
1422 static inline unsigned long brk_rnd(void)
1424 unsigned long rnd
= 0;
1426 /* 8MB for 32bit, 1GB for 64bit */
1427 if (is_32bit_task())
1428 rnd
= (long)(get_random_int() % (1<<(23-PAGE_SHIFT
)));
1430 rnd
= (long)(get_random_int() % (1<<(30-PAGE_SHIFT
)));
1432 return rnd
<< PAGE_SHIFT
;
1435 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1437 unsigned long base
= mm
->brk
;
1440 #ifdef CONFIG_PPC_STD_MMU_64
1442 * If we are using 1TB segments and we are allowed to randomise
1443 * the heap, we can put it above 1TB so it is backed by a 1TB
1444 * segment. Otherwise the heap will be in the bottom 1TB
1445 * which always uses 256MB segments and this may result in a
1446 * performance penalty.
1448 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
1449 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
1452 ret
= PAGE_ALIGN(base
+ brk_rnd());
1460 unsigned long randomize_et_dyn(unsigned long base
)
1462 unsigned long ret
= PAGE_ALIGN(base
+ brk_rnd());
This page took 0.062164 seconds and 5 git commands to generate.