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Merge branch 'acpi-lpss'
[deliverable/linux.git] / arch / powerpc / kernel / ptrace.c
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/mm.h>
21 #include <linux/smp.h>
22 #include <linux/errno.h>
23 #include <linux/ptrace.h>
24 #include <linux/regset.h>
25 #include <linux/tracehook.h>
26 #include <linux/elf.h>
27 #include <linux/user.h>
28 #include <linux/security.h>
29 #include <linux/signal.h>
30 #include <linux/seccomp.h>
31 #include <linux/audit.h>
32 #include <trace/syscall.h>
33 #include <linux/hw_breakpoint.h>
34 #include <linux/perf_event.h>
35
36 #include <asm/uaccess.h>
37 #include <asm/page.h>
38 #include <asm/pgtable.h>
39 #include <asm/switch_to.h>
40
41 #define CREATE_TRACE_POINTS
42 #include <trace/events/syscalls.h>
43
44 /*
45 * The parameter save area on the stack is used to store arguments being passed
46 * to callee function and is located at fixed offset from stack pointer.
47 */
48 #ifdef CONFIG_PPC32
49 #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
50 #else /* CONFIG_PPC32 */
51 #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
52 #endif
53
54 struct pt_regs_offset {
55 const char *name;
56 int offset;
57 };
58
59 #define STR(s) #s /* convert to string */
60 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
61 #define GPR_OFFSET_NAME(num) \
62 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
63 #define REG_OFFSET_END {.name = NULL, .offset = 0}
64
65 static const struct pt_regs_offset regoffset_table[] = {
66 GPR_OFFSET_NAME(0),
67 GPR_OFFSET_NAME(1),
68 GPR_OFFSET_NAME(2),
69 GPR_OFFSET_NAME(3),
70 GPR_OFFSET_NAME(4),
71 GPR_OFFSET_NAME(5),
72 GPR_OFFSET_NAME(6),
73 GPR_OFFSET_NAME(7),
74 GPR_OFFSET_NAME(8),
75 GPR_OFFSET_NAME(9),
76 GPR_OFFSET_NAME(10),
77 GPR_OFFSET_NAME(11),
78 GPR_OFFSET_NAME(12),
79 GPR_OFFSET_NAME(13),
80 GPR_OFFSET_NAME(14),
81 GPR_OFFSET_NAME(15),
82 GPR_OFFSET_NAME(16),
83 GPR_OFFSET_NAME(17),
84 GPR_OFFSET_NAME(18),
85 GPR_OFFSET_NAME(19),
86 GPR_OFFSET_NAME(20),
87 GPR_OFFSET_NAME(21),
88 GPR_OFFSET_NAME(22),
89 GPR_OFFSET_NAME(23),
90 GPR_OFFSET_NAME(24),
91 GPR_OFFSET_NAME(25),
92 GPR_OFFSET_NAME(26),
93 GPR_OFFSET_NAME(27),
94 GPR_OFFSET_NAME(28),
95 GPR_OFFSET_NAME(29),
96 GPR_OFFSET_NAME(30),
97 GPR_OFFSET_NAME(31),
98 REG_OFFSET_NAME(nip),
99 REG_OFFSET_NAME(msr),
100 REG_OFFSET_NAME(ctr),
101 REG_OFFSET_NAME(link),
102 REG_OFFSET_NAME(xer),
103 REG_OFFSET_NAME(ccr),
104 #ifdef CONFIG_PPC64
105 REG_OFFSET_NAME(softe),
106 #else
107 REG_OFFSET_NAME(mq),
108 #endif
109 REG_OFFSET_NAME(trap),
110 REG_OFFSET_NAME(dar),
111 REG_OFFSET_NAME(dsisr),
112 REG_OFFSET_END,
113 };
114
115 /**
116 * regs_query_register_offset() - query register offset from its name
117 * @name: the name of a register
118 *
119 * regs_query_register_offset() returns the offset of a register in struct
120 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
121 */
122 int regs_query_register_offset(const char *name)
123 {
124 const struct pt_regs_offset *roff;
125 for (roff = regoffset_table; roff->name != NULL; roff++)
126 if (!strcmp(roff->name, name))
127 return roff->offset;
128 return -EINVAL;
129 }
130
131 /**
132 * regs_query_register_name() - query register name from its offset
133 * @offset: the offset of a register in struct pt_regs.
134 *
135 * regs_query_register_name() returns the name of a register from its
136 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
137 */
138 const char *regs_query_register_name(unsigned int offset)
139 {
140 const struct pt_regs_offset *roff;
141 for (roff = regoffset_table; roff->name != NULL; roff++)
142 if (roff->offset == offset)
143 return roff->name;
144 return NULL;
145 }
146
147 /*
148 * does not yet catch signals sent when the child dies.
149 * in exit.c or in signal.c.
150 */
151
152 /*
153 * Set of msr bits that gdb can change on behalf of a process.
154 */
155 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
156 #define MSR_DEBUGCHANGE 0
157 #else
158 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
159 #endif
160
161 /*
162 * Max register writeable via put_reg
163 */
164 #ifdef CONFIG_PPC32
165 #define PT_MAX_PUT_REG PT_MQ
166 #else
167 #define PT_MAX_PUT_REG PT_CCR
168 #endif
169
170 static unsigned long get_user_msr(struct task_struct *task)
171 {
172 return task->thread.regs->msr | task->thread.fpexc_mode;
173 }
174
175 static int set_user_msr(struct task_struct *task, unsigned long msr)
176 {
177 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
178 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
179 return 0;
180 }
181
182 #ifdef CONFIG_PPC64
183 static unsigned long get_user_dscr(struct task_struct *task)
184 {
185 return task->thread.dscr;
186 }
187
188 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
189 {
190 task->thread.dscr = dscr;
191 task->thread.dscr_inherit = 1;
192 return 0;
193 }
194 #else
195 static unsigned long get_user_dscr(struct task_struct *task)
196 {
197 return -EIO;
198 }
199
200 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
201 {
202 return -EIO;
203 }
204 #endif
205
206 /*
207 * We prevent mucking around with the reserved area of trap
208 * which are used internally by the kernel.
209 */
210 static int set_user_trap(struct task_struct *task, unsigned long trap)
211 {
212 task->thread.regs->trap = trap & 0xfff0;
213 return 0;
214 }
215
216 /*
217 * Get contents of register REGNO in task TASK.
218 */
219 unsigned long ptrace_get_reg(struct task_struct *task, int regno)
220 {
221 if (task->thread.regs == NULL)
222 return -EIO;
223
224 if (regno == PT_MSR)
225 return get_user_msr(task);
226
227 if (regno == PT_DSCR)
228 return get_user_dscr(task);
229
230 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
231 return ((unsigned long *)task->thread.regs)[regno];
232
233 return -EIO;
234 }
235
236 /*
237 * Write contents of register REGNO in task TASK.
238 */
239 int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
240 {
241 if (task->thread.regs == NULL)
242 return -EIO;
243
244 if (regno == PT_MSR)
245 return set_user_msr(task, data);
246 if (regno == PT_TRAP)
247 return set_user_trap(task, data);
248 if (regno == PT_DSCR)
249 return set_user_dscr(task, data);
250
251 if (regno <= PT_MAX_PUT_REG) {
252 ((unsigned long *)task->thread.regs)[regno] = data;
253 return 0;
254 }
255 return -EIO;
256 }
257
258 static int gpr_get(struct task_struct *target, const struct user_regset *regset,
259 unsigned int pos, unsigned int count,
260 void *kbuf, void __user *ubuf)
261 {
262 int i, ret;
263
264 if (target->thread.regs == NULL)
265 return -EIO;
266
267 if (!FULL_REGS(target->thread.regs)) {
268 /* We have a partial register set. Fill 14-31 with bogus values */
269 for (i = 14; i < 32; i++)
270 target->thread.regs->gpr[i] = NV_REG_POISON;
271 }
272
273 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
274 target->thread.regs,
275 0, offsetof(struct pt_regs, msr));
276 if (!ret) {
277 unsigned long msr = get_user_msr(target);
278 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
279 offsetof(struct pt_regs, msr),
280 offsetof(struct pt_regs, msr) +
281 sizeof(msr));
282 }
283
284 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
285 offsetof(struct pt_regs, msr) + sizeof(long));
286
287 if (!ret)
288 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
289 &target->thread.regs->orig_gpr3,
290 offsetof(struct pt_regs, orig_gpr3),
291 sizeof(struct pt_regs));
292 if (!ret)
293 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
294 sizeof(struct pt_regs), -1);
295
296 return ret;
297 }
298
299 static int gpr_set(struct task_struct *target, const struct user_regset *regset,
300 unsigned int pos, unsigned int count,
301 const void *kbuf, const void __user *ubuf)
302 {
303 unsigned long reg;
304 int ret;
305
306 if (target->thread.regs == NULL)
307 return -EIO;
308
309 CHECK_FULL_REGS(target->thread.regs);
310
311 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
312 target->thread.regs,
313 0, PT_MSR * sizeof(reg));
314
315 if (!ret && count > 0) {
316 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
317 PT_MSR * sizeof(reg),
318 (PT_MSR + 1) * sizeof(reg));
319 if (!ret)
320 ret = set_user_msr(target, reg);
321 }
322
323 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
324 offsetof(struct pt_regs, msr) + sizeof(long));
325
326 if (!ret)
327 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
328 &target->thread.regs->orig_gpr3,
329 PT_ORIG_R3 * sizeof(reg),
330 (PT_MAX_PUT_REG + 1) * sizeof(reg));
331
332 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
333 ret = user_regset_copyin_ignore(
334 &pos, &count, &kbuf, &ubuf,
335 (PT_MAX_PUT_REG + 1) * sizeof(reg),
336 PT_TRAP * sizeof(reg));
337
338 if (!ret && count > 0) {
339 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
340 PT_TRAP * sizeof(reg),
341 (PT_TRAP + 1) * sizeof(reg));
342 if (!ret)
343 ret = set_user_trap(target, reg);
344 }
345
346 if (!ret)
347 ret = user_regset_copyin_ignore(
348 &pos, &count, &kbuf, &ubuf,
349 (PT_TRAP + 1) * sizeof(reg), -1);
350
351 return ret;
352 }
353
354 static int fpr_get(struct task_struct *target, const struct user_regset *regset,
355 unsigned int pos, unsigned int count,
356 void *kbuf, void __user *ubuf)
357 {
358 #ifdef CONFIG_VSX
359 double buf[33];
360 int i;
361 #endif
362 flush_fp_to_thread(target);
363
364 #ifdef CONFIG_VSX
365 /* copy to local buffer then write that out */
366 for (i = 0; i < 32 ; i++)
367 buf[i] = target->thread.TS_FPR(i);
368 memcpy(&buf[32], &target->thread.fpscr, sizeof(double));
369 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
370
371 #else
372 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
373 offsetof(struct thread_struct, TS_FPR(32)));
374
375 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
376 &target->thread.fpr, 0, -1);
377 #endif
378 }
379
380 static int fpr_set(struct task_struct *target, const struct user_regset *regset,
381 unsigned int pos, unsigned int count,
382 const void *kbuf, const void __user *ubuf)
383 {
384 #ifdef CONFIG_VSX
385 double buf[33];
386 int i;
387 #endif
388 flush_fp_to_thread(target);
389
390 #ifdef CONFIG_VSX
391 /* copy to local buffer then write that out */
392 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
393 if (i)
394 return i;
395 for (i = 0; i < 32 ; i++)
396 target->thread.TS_FPR(i) = buf[i];
397 memcpy(&target->thread.fpscr, &buf[32], sizeof(double));
398 return 0;
399 #else
400 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
401 offsetof(struct thread_struct, TS_FPR(32)));
402
403 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
404 &target->thread.fpr, 0, -1);
405 #endif
406 }
407
408 #ifdef CONFIG_ALTIVEC
409 /*
410 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
411 * The transfer totals 34 quadword. Quadwords 0-31 contain the
412 * corresponding vector registers. Quadword 32 contains the vscr as the
413 * last word (offset 12) within that quadword. Quadword 33 contains the
414 * vrsave as the first word (offset 0) within the quadword.
415 *
416 * This definition of the VMX state is compatible with the current PPC32
417 * ptrace interface. This allows signal handling and ptrace to use the
418 * same structures. This also simplifies the implementation of a bi-arch
419 * (combined (32- and 64-bit) gdb.
420 */
421
422 static int vr_active(struct task_struct *target,
423 const struct user_regset *regset)
424 {
425 flush_altivec_to_thread(target);
426 return target->thread.used_vr ? regset->n : 0;
427 }
428
429 static int vr_get(struct task_struct *target, const struct user_regset *regset,
430 unsigned int pos, unsigned int count,
431 void *kbuf, void __user *ubuf)
432 {
433 int ret;
434
435 flush_altivec_to_thread(target);
436
437 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
438 offsetof(struct thread_struct, vr[32]));
439
440 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
441 &target->thread.vr, 0,
442 33 * sizeof(vector128));
443 if (!ret) {
444 /*
445 * Copy out only the low-order word of vrsave.
446 */
447 union {
448 elf_vrreg_t reg;
449 u32 word;
450 } vrsave;
451 memset(&vrsave, 0, sizeof(vrsave));
452 vrsave.word = target->thread.vrsave;
453 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
454 33 * sizeof(vector128), -1);
455 }
456
457 return ret;
458 }
459
460 static int vr_set(struct task_struct *target, const struct user_regset *regset,
461 unsigned int pos, unsigned int count,
462 const void *kbuf, const void __user *ubuf)
463 {
464 int ret;
465
466 flush_altivec_to_thread(target);
467
468 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
469 offsetof(struct thread_struct, vr[32]));
470
471 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
472 &target->thread.vr, 0, 33 * sizeof(vector128));
473 if (!ret && count > 0) {
474 /*
475 * We use only the first word of vrsave.
476 */
477 union {
478 elf_vrreg_t reg;
479 u32 word;
480 } vrsave;
481 memset(&vrsave, 0, sizeof(vrsave));
482 vrsave.word = target->thread.vrsave;
483 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
484 33 * sizeof(vector128), -1);
485 if (!ret)
486 target->thread.vrsave = vrsave.word;
487 }
488
489 return ret;
490 }
491 #endif /* CONFIG_ALTIVEC */
492
493 #ifdef CONFIG_VSX
494 /*
495 * Currently to set and and get all the vsx state, you need to call
496 * the fp and VMX calls as well. This only get/sets the lower 32
497 * 128bit VSX registers.
498 */
499
500 static int vsr_active(struct task_struct *target,
501 const struct user_regset *regset)
502 {
503 flush_vsx_to_thread(target);
504 return target->thread.used_vsr ? regset->n : 0;
505 }
506
507 static int vsr_get(struct task_struct *target, const struct user_regset *regset,
508 unsigned int pos, unsigned int count,
509 void *kbuf, void __user *ubuf)
510 {
511 double buf[32];
512 int ret, i;
513
514 flush_vsx_to_thread(target);
515
516 for (i = 0; i < 32 ; i++)
517 buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET];
518 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
519 buf, 0, 32 * sizeof(double));
520
521 return ret;
522 }
523
524 static int vsr_set(struct task_struct *target, const struct user_regset *regset,
525 unsigned int pos, unsigned int count,
526 const void *kbuf, const void __user *ubuf)
527 {
528 double buf[32];
529 int ret,i;
530
531 flush_vsx_to_thread(target);
532
533 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
534 buf, 0, 32 * sizeof(double));
535 for (i = 0; i < 32 ; i++)
536 target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
537
538
539 return ret;
540 }
541 #endif /* CONFIG_VSX */
542
543 #ifdef CONFIG_SPE
544
545 /*
546 * For get_evrregs/set_evrregs functions 'data' has the following layout:
547 *
548 * struct {
549 * u32 evr[32];
550 * u64 acc;
551 * u32 spefscr;
552 * }
553 */
554
555 static int evr_active(struct task_struct *target,
556 const struct user_regset *regset)
557 {
558 flush_spe_to_thread(target);
559 return target->thread.used_spe ? regset->n : 0;
560 }
561
562 static int evr_get(struct task_struct *target, const struct user_regset *regset,
563 unsigned int pos, unsigned int count,
564 void *kbuf, void __user *ubuf)
565 {
566 int ret;
567
568 flush_spe_to_thread(target);
569
570 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
571 &target->thread.evr,
572 0, sizeof(target->thread.evr));
573
574 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
575 offsetof(struct thread_struct, spefscr));
576
577 if (!ret)
578 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
579 &target->thread.acc,
580 sizeof(target->thread.evr), -1);
581
582 return ret;
583 }
584
585 static int evr_set(struct task_struct *target, const struct user_regset *regset,
586 unsigned int pos, unsigned int count,
587 const void *kbuf, const void __user *ubuf)
588 {
589 int ret;
590
591 flush_spe_to_thread(target);
592
593 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
594 &target->thread.evr,
595 0, sizeof(target->thread.evr));
596
597 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
598 offsetof(struct thread_struct, spefscr));
599
600 if (!ret)
601 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
602 &target->thread.acc,
603 sizeof(target->thread.evr), -1);
604
605 return ret;
606 }
607 #endif /* CONFIG_SPE */
608
609
610 /*
611 * These are our native regset flavors.
612 */
613 enum powerpc_regset {
614 REGSET_GPR,
615 REGSET_FPR,
616 #ifdef CONFIG_ALTIVEC
617 REGSET_VMX,
618 #endif
619 #ifdef CONFIG_VSX
620 REGSET_VSX,
621 #endif
622 #ifdef CONFIG_SPE
623 REGSET_SPE,
624 #endif
625 };
626
627 static const struct user_regset native_regsets[] = {
628 [REGSET_GPR] = {
629 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
630 .size = sizeof(long), .align = sizeof(long),
631 .get = gpr_get, .set = gpr_set
632 },
633 [REGSET_FPR] = {
634 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
635 .size = sizeof(double), .align = sizeof(double),
636 .get = fpr_get, .set = fpr_set
637 },
638 #ifdef CONFIG_ALTIVEC
639 [REGSET_VMX] = {
640 .core_note_type = NT_PPC_VMX, .n = 34,
641 .size = sizeof(vector128), .align = sizeof(vector128),
642 .active = vr_active, .get = vr_get, .set = vr_set
643 },
644 #endif
645 #ifdef CONFIG_VSX
646 [REGSET_VSX] = {
647 .core_note_type = NT_PPC_VSX, .n = 32,
648 .size = sizeof(double), .align = sizeof(double),
649 .active = vsr_active, .get = vsr_get, .set = vsr_set
650 },
651 #endif
652 #ifdef CONFIG_SPE
653 [REGSET_SPE] = {
654 .n = 35,
655 .size = sizeof(u32), .align = sizeof(u32),
656 .active = evr_active, .get = evr_get, .set = evr_set
657 },
658 #endif
659 };
660
661 static const struct user_regset_view user_ppc_native_view = {
662 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
663 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
664 };
665
666 #ifdef CONFIG_PPC64
667 #include <linux/compat.h>
668
669 static int gpr32_get(struct task_struct *target,
670 const struct user_regset *regset,
671 unsigned int pos, unsigned int count,
672 void *kbuf, void __user *ubuf)
673 {
674 const unsigned long *regs = &target->thread.regs->gpr[0];
675 compat_ulong_t *k = kbuf;
676 compat_ulong_t __user *u = ubuf;
677 compat_ulong_t reg;
678 int i;
679
680 if (target->thread.regs == NULL)
681 return -EIO;
682
683 if (!FULL_REGS(target->thread.regs)) {
684 /* We have a partial register set. Fill 14-31 with bogus values */
685 for (i = 14; i < 32; i++)
686 target->thread.regs->gpr[i] = NV_REG_POISON;
687 }
688
689 pos /= sizeof(reg);
690 count /= sizeof(reg);
691
692 if (kbuf)
693 for (; count > 0 && pos < PT_MSR; --count)
694 *k++ = regs[pos++];
695 else
696 for (; count > 0 && pos < PT_MSR; --count)
697 if (__put_user((compat_ulong_t) regs[pos++], u++))
698 return -EFAULT;
699
700 if (count > 0 && pos == PT_MSR) {
701 reg = get_user_msr(target);
702 if (kbuf)
703 *k++ = reg;
704 else if (__put_user(reg, u++))
705 return -EFAULT;
706 ++pos;
707 --count;
708 }
709
710 if (kbuf)
711 for (; count > 0 && pos < PT_REGS_COUNT; --count)
712 *k++ = regs[pos++];
713 else
714 for (; count > 0 && pos < PT_REGS_COUNT; --count)
715 if (__put_user((compat_ulong_t) regs[pos++], u++))
716 return -EFAULT;
717
718 kbuf = k;
719 ubuf = u;
720 pos *= sizeof(reg);
721 count *= sizeof(reg);
722 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
723 PT_REGS_COUNT * sizeof(reg), -1);
724 }
725
726 static int gpr32_set(struct task_struct *target,
727 const struct user_regset *regset,
728 unsigned int pos, unsigned int count,
729 const void *kbuf, const void __user *ubuf)
730 {
731 unsigned long *regs = &target->thread.regs->gpr[0];
732 const compat_ulong_t *k = kbuf;
733 const compat_ulong_t __user *u = ubuf;
734 compat_ulong_t reg;
735
736 if (target->thread.regs == NULL)
737 return -EIO;
738
739 CHECK_FULL_REGS(target->thread.regs);
740
741 pos /= sizeof(reg);
742 count /= sizeof(reg);
743
744 if (kbuf)
745 for (; count > 0 && pos < PT_MSR; --count)
746 regs[pos++] = *k++;
747 else
748 for (; count > 0 && pos < PT_MSR; --count) {
749 if (__get_user(reg, u++))
750 return -EFAULT;
751 regs[pos++] = reg;
752 }
753
754
755 if (count > 0 && pos == PT_MSR) {
756 if (kbuf)
757 reg = *k++;
758 else if (__get_user(reg, u++))
759 return -EFAULT;
760 set_user_msr(target, reg);
761 ++pos;
762 --count;
763 }
764
765 if (kbuf) {
766 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
767 regs[pos++] = *k++;
768 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
769 ++k;
770 } else {
771 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
772 if (__get_user(reg, u++))
773 return -EFAULT;
774 regs[pos++] = reg;
775 }
776 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
777 if (__get_user(reg, u++))
778 return -EFAULT;
779 }
780
781 if (count > 0 && pos == PT_TRAP) {
782 if (kbuf)
783 reg = *k++;
784 else if (__get_user(reg, u++))
785 return -EFAULT;
786 set_user_trap(target, reg);
787 ++pos;
788 --count;
789 }
790
791 kbuf = k;
792 ubuf = u;
793 pos *= sizeof(reg);
794 count *= sizeof(reg);
795 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
796 (PT_TRAP + 1) * sizeof(reg), -1);
797 }
798
799 /*
800 * These are the regset flavors matching the CONFIG_PPC32 native set.
801 */
802 static const struct user_regset compat_regsets[] = {
803 [REGSET_GPR] = {
804 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
805 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
806 .get = gpr32_get, .set = gpr32_set
807 },
808 [REGSET_FPR] = {
809 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
810 .size = sizeof(double), .align = sizeof(double),
811 .get = fpr_get, .set = fpr_set
812 },
813 #ifdef CONFIG_ALTIVEC
814 [REGSET_VMX] = {
815 .core_note_type = NT_PPC_VMX, .n = 34,
816 .size = sizeof(vector128), .align = sizeof(vector128),
817 .active = vr_active, .get = vr_get, .set = vr_set
818 },
819 #endif
820 #ifdef CONFIG_SPE
821 [REGSET_SPE] = {
822 .core_note_type = NT_PPC_SPE, .n = 35,
823 .size = sizeof(u32), .align = sizeof(u32),
824 .active = evr_active, .get = evr_get, .set = evr_set
825 },
826 #endif
827 };
828
829 static const struct user_regset_view user_ppc_compat_view = {
830 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
831 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
832 };
833 #endif /* CONFIG_PPC64 */
834
835 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
836 {
837 #ifdef CONFIG_PPC64
838 if (test_tsk_thread_flag(task, TIF_32BIT))
839 return &user_ppc_compat_view;
840 #endif
841 return &user_ppc_native_view;
842 }
843
844
845 void user_enable_single_step(struct task_struct *task)
846 {
847 struct pt_regs *regs = task->thread.regs;
848
849 if (regs != NULL) {
850 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
851 task->thread.dbcr0 &= ~DBCR0_BT;
852 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
853 regs->msr |= MSR_DE;
854 #else
855 regs->msr &= ~MSR_BE;
856 regs->msr |= MSR_SE;
857 #endif
858 }
859 set_tsk_thread_flag(task, TIF_SINGLESTEP);
860 }
861
862 void user_enable_block_step(struct task_struct *task)
863 {
864 struct pt_regs *regs = task->thread.regs;
865
866 if (regs != NULL) {
867 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
868 task->thread.dbcr0 &= ~DBCR0_IC;
869 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
870 regs->msr |= MSR_DE;
871 #else
872 regs->msr &= ~MSR_SE;
873 regs->msr |= MSR_BE;
874 #endif
875 }
876 set_tsk_thread_flag(task, TIF_SINGLESTEP);
877 }
878
879 void user_disable_single_step(struct task_struct *task)
880 {
881 struct pt_regs *regs = task->thread.regs;
882
883 if (regs != NULL) {
884 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
885 /*
886 * The logic to disable single stepping should be as
887 * simple as turning off the Instruction Complete flag.
888 * And, after doing so, if all debug flags are off, turn
889 * off DBCR0(IDM) and MSR(DE) .... Torez
890 */
891 task->thread.dbcr0 &= ~DBCR0_IC;
892 /*
893 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
894 */
895 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
896 task->thread.dbcr1)) {
897 /*
898 * All debug events were off.....
899 */
900 task->thread.dbcr0 &= ~DBCR0_IDM;
901 regs->msr &= ~MSR_DE;
902 }
903 #else
904 regs->msr &= ~(MSR_SE | MSR_BE);
905 #endif
906 }
907 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
908 }
909
910 #ifdef CONFIG_HAVE_HW_BREAKPOINT
911 void ptrace_triggered(struct perf_event *bp,
912 struct perf_sample_data *data, struct pt_regs *regs)
913 {
914 struct perf_event_attr attr;
915
916 /*
917 * Disable the breakpoint request here since ptrace has defined a
918 * one-shot behaviour for breakpoint exceptions in PPC64.
919 * The SIGTRAP signal is generated automatically for us in do_dabr().
920 * We don't have to do anything about that here
921 */
922 attr = bp->attr;
923 attr.disabled = true;
924 modify_user_hw_breakpoint(bp, &attr);
925 }
926 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
927
928 int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
929 unsigned long data)
930 {
931 #ifdef CONFIG_HAVE_HW_BREAKPOINT
932 int ret;
933 struct thread_struct *thread = &(task->thread);
934 struct perf_event *bp;
935 struct perf_event_attr attr;
936 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
937 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
938 struct arch_hw_breakpoint hw_brk;
939 #endif
940
941 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
942 * For embedded processors we support one DAC and no IAC's at the
943 * moment.
944 */
945 if (addr > 0)
946 return -EINVAL;
947
948 /* The bottom 3 bits in dabr are flags */
949 if ((data & ~0x7UL) >= TASK_SIZE)
950 return -EIO;
951
952 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
953 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
954 * It was assumed, on previous implementations, that 3 bits were
955 * passed together with the data address, fitting the design of the
956 * DABR register, as follows:
957 *
958 * bit 0: Read flag
959 * bit 1: Write flag
960 * bit 2: Breakpoint translation
961 *
962 * Thus, we use them here as so.
963 */
964
965 /* Ensure breakpoint translation bit is set */
966 if (data && !(data & HW_BRK_TYPE_TRANSLATE))
967 return -EIO;
968 hw_brk.address = data & (~HW_BRK_TYPE_DABR);
969 hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
970 hw_brk.len = 8;
971 #ifdef CONFIG_HAVE_HW_BREAKPOINT
972 if (ptrace_get_breakpoints(task) < 0)
973 return -ESRCH;
974
975 bp = thread->ptrace_bps[0];
976 if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) {
977 if (bp) {
978 unregister_hw_breakpoint(bp);
979 thread->ptrace_bps[0] = NULL;
980 }
981 ptrace_put_breakpoints(task);
982 return 0;
983 }
984 if (bp) {
985 attr = bp->attr;
986 attr.bp_addr = hw_brk.address;
987 arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
988
989 /* Enable breakpoint */
990 attr.disabled = false;
991
992 ret = modify_user_hw_breakpoint(bp, &attr);
993 if (ret) {
994 ptrace_put_breakpoints(task);
995 return ret;
996 }
997 thread->ptrace_bps[0] = bp;
998 ptrace_put_breakpoints(task);
999 thread->hw_brk = hw_brk;
1000 return 0;
1001 }
1002
1003 /* Create a new breakpoint request if one doesn't exist already */
1004 hw_breakpoint_init(&attr);
1005 attr.bp_addr = hw_brk.address;
1006 arch_bp_generic_fields(hw_brk.type,
1007 &attr.bp_type);
1008
1009 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
1010 ptrace_triggered, NULL, task);
1011 if (IS_ERR(bp)) {
1012 thread->ptrace_bps[0] = NULL;
1013 ptrace_put_breakpoints(task);
1014 return PTR_ERR(bp);
1015 }
1016
1017 ptrace_put_breakpoints(task);
1018
1019 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1020 task->thread.hw_brk = hw_brk;
1021 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
1022 /* As described above, it was assumed 3 bits were passed with the data
1023 * address, but we will assume only the mode bits will be passed
1024 * as to not cause alignment restrictions for DAC-based processors.
1025 */
1026
1027 /* DAC's hold the whole address without any mode flags */
1028 task->thread.dac1 = data & ~0x3UL;
1029
1030 if (task->thread.dac1 == 0) {
1031 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1032 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
1033 task->thread.dbcr1)) {
1034 task->thread.regs->msr &= ~MSR_DE;
1035 task->thread.dbcr0 &= ~DBCR0_IDM;
1036 }
1037 return 0;
1038 }
1039
1040 /* Read or Write bits must be set */
1041
1042 if (!(data & 0x3UL))
1043 return -EINVAL;
1044
1045 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
1046 register */
1047 task->thread.dbcr0 |= DBCR0_IDM;
1048
1049 /* Check for write and read flags and set DBCR0
1050 accordingly */
1051 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
1052 if (data & 0x1UL)
1053 dbcr_dac(task) |= DBCR_DAC1R;
1054 if (data & 0x2UL)
1055 dbcr_dac(task) |= DBCR_DAC1W;
1056 task->thread.regs->msr |= MSR_DE;
1057 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1058 return 0;
1059 }
1060
1061 /*
1062 * Called by kernel/ptrace.c when detaching..
1063 *
1064 * Make sure single step bits etc are not set.
1065 */
1066 void ptrace_disable(struct task_struct *child)
1067 {
1068 /* make sure the single step bit is not set. */
1069 user_disable_single_step(child);
1070 }
1071
1072 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1073 static long set_instruction_bp(struct task_struct *child,
1074 struct ppc_hw_breakpoint *bp_info)
1075 {
1076 int slot;
1077 int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
1078 int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
1079 int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
1080 int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
1081
1082 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1083 slot2_in_use = 1;
1084 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1085 slot4_in_use = 1;
1086
1087 if (bp_info->addr >= TASK_SIZE)
1088 return -EIO;
1089
1090 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1091
1092 /* Make sure range is valid. */
1093 if (bp_info->addr2 >= TASK_SIZE)
1094 return -EIO;
1095
1096 /* We need a pair of IAC regsisters */
1097 if ((!slot1_in_use) && (!slot2_in_use)) {
1098 slot = 1;
1099 child->thread.iac1 = bp_info->addr;
1100 child->thread.iac2 = bp_info->addr2;
1101 child->thread.dbcr0 |= DBCR0_IAC1;
1102 if (bp_info->addr_mode ==
1103 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1104 dbcr_iac_range(child) |= DBCR_IAC12X;
1105 else
1106 dbcr_iac_range(child) |= DBCR_IAC12I;
1107 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1108 } else if ((!slot3_in_use) && (!slot4_in_use)) {
1109 slot = 3;
1110 child->thread.iac3 = bp_info->addr;
1111 child->thread.iac4 = bp_info->addr2;
1112 child->thread.dbcr0 |= DBCR0_IAC3;
1113 if (bp_info->addr_mode ==
1114 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1115 dbcr_iac_range(child) |= DBCR_IAC34X;
1116 else
1117 dbcr_iac_range(child) |= DBCR_IAC34I;
1118 #endif
1119 } else
1120 return -ENOSPC;
1121 } else {
1122 /* We only need one. If possible leave a pair free in
1123 * case a range is needed later
1124 */
1125 if (!slot1_in_use) {
1126 /*
1127 * Don't use iac1 if iac1-iac2 are free and either
1128 * iac3 or iac4 (but not both) are free
1129 */
1130 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
1131 slot = 1;
1132 child->thread.iac1 = bp_info->addr;
1133 child->thread.dbcr0 |= DBCR0_IAC1;
1134 goto out;
1135 }
1136 }
1137 if (!slot2_in_use) {
1138 slot = 2;
1139 child->thread.iac2 = bp_info->addr;
1140 child->thread.dbcr0 |= DBCR0_IAC2;
1141 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1142 } else if (!slot3_in_use) {
1143 slot = 3;
1144 child->thread.iac3 = bp_info->addr;
1145 child->thread.dbcr0 |= DBCR0_IAC3;
1146 } else if (!slot4_in_use) {
1147 slot = 4;
1148 child->thread.iac4 = bp_info->addr;
1149 child->thread.dbcr0 |= DBCR0_IAC4;
1150 #endif
1151 } else
1152 return -ENOSPC;
1153 }
1154 out:
1155 child->thread.dbcr0 |= DBCR0_IDM;
1156 child->thread.regs->msr |= MSR_DE;
1157
1158 return slot;
1159 }
1160
1161 static int del_instruction_bp(struct task_struct *child, int slot)
1162 {
1163 switch (slot) {
1164 case 1:
1165 if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
1166 return -ENOENT;
1167
1168 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
1169 /* address range - clear slots 1 & 2 */
1170 child->thread.iac2 = 0;
1171 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
1172 }
1173 child->thread.iac1 = 0;
1174 child->thread.dbcr0 &= ~DBCR0_IAC1;
1175 break;
1176 case 2:
1177 if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
1178 return -ENOENT;
1179
1180 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1181 /* used in a range */
1182 return -EINVAL;
1183 child->thread.iac2 = 0;
1184 child->thread.dbcr0 &= ~DBCR0_IAC2;
1185 break;
1186 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1187 case 3:
1188 if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
1189 return -ENOENT;
1190
1191 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
1192 /* address range - clear slots 3 & 4 */
1193 child->thread.iac4 = 0;
1194 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
1195 }
1196 child->thread.iac3 = 0;
1197 child->thread.dbcr0 &= ~DBCR0_IAC3;
1198 break;
1199 case 4:
1200 if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
1201 return -ENOENT;
1202
1203 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1204 /* Used in a range */
1205 return -EINVAL;
1206 child->thread.iac4 = 0;
1207 child->thread.dbcr0 &= ~DBCR0_IAC4;
1208 break;
1209 #endif
1210 default:
1211 return -EINVAL;
1212 }
1213 return 0;
1214 }
1215
1216 static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1217 {
1218 int byte_enable =
1219 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
1220 & 0xf;
1221 int condition_mode =
1222 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
1223 int slot;
1224
1225 if (byte_enable && (condition_mode == 0))
1226 return -EINVAL;
1227
1228 if (bp_info->addr >= TASK_SIZE)
1229 return -EIO;
1230
1231 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
1232 slot = 1;
1233 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1234 dbcr_dac(child) |= DBCR_DAC1R;
1235 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1236 dbcr_dac(child) |= DBCR_DAC1W;
1237 child->thread.dac1 = (unsigned long)bp_info->addr;
1238 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1239 if (byte_enable) {
1240 child->thread.dvc1 =
1241 (unsigned long)bp_info->condition_value;
1242 child->thread.dbcr2 |=
1243 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
1244 (condition_mode << DBCR2_DVC1M_SHIFT));
1245 }
1246 #endif
1247 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1248 } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1249 /* Both dac1 and dac2 are part of a range */
1250 return -ENOSPC;
1251 #endif
1252 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
1253 slot = 2;
1254 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1255 dbcr_dac(child) |= DBCR_DAC2R;
1256 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1257 dbcr_dac(child) |= DBCR_DAC2W;
1258 child->thread.dac2 = (unsigned long)bp_info->addr;
1259 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1260 if (byte_enable) {
1261 child->thread.dvc2 =
1262 (unsigned long)bp_info->condition_value;
1263 child->thread.dbcr2 |=
1264 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
1265 (condition_mode << DBCR2_DVC2M_SHIFT));
1266 }
1267 #endif
1268 } else
1269 return -ENOSPC;
1270 child->thread.dbcr0 |= DBCR0_IDM;
1271 child->thread.regs->msr |= MSR_DE;
1272
1273 return slot + 4;
1274 }
1275
1276 static int del_dac(struct task_struct *child, int slot)
1277 {
1278 if (slot == 1) {
1279 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
1280 return -ENOENT;
1281
1282 child->thread.dac1 = 0;
1283 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1284 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1285 if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1286 child->thread.dac2 = 0;
1287 child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1288 }
1289 child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
1290 #endif
1291 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1292 child->thread.dvc1 = 0;
1293 #endif
1294 } else if (slot == 2) {
1295 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
1296 return -ENOENT;
1297
1298 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1299 if (child->thread.dbcr2 & DBCR2_DAC12MODE)
1300 /* Part of a range */
1301 return -EINVAL;
1302 child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
1303 #endif
1304 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1305 child->thread.dvc2 = 0;
1306 #endif
1307 child->thread.dac2 = 0;
1308 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1309 } else
1310 return -EINVAL;
1311
1312 return 0;
1313 }
1314 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1315
1316 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1317 static int set_dac_range(struct task_struct *child,
1318 struct ppc_hw_breakpoint *bp_info)
1319 {
1320 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
1321
1322 /* We don't allow range watchpoints to be used with DVC */
1323 if (bp_info->condition_mode)
1324 return -EINVAL;
1325
1326 /*
1327 * Best effort to verify the address range. The user/supervisor bits
1328 * prevent trapping in kernel space, but let's fail on an obvious bad
1329 * range. The simple test on the mask is not fool-proof, and any
1330 * exclusive range will spill over into kernel space.
1331 */
1332 if (bp_info->addr >= TASK_SIZE)
1333 return -EIO;
1334 if (mode == PPC_BREAKPOINT_MODE_MASK) {
1335 /*
1336 * dac2 is a bitmask. Don't allow a mask that makes a
1337 * kernel space address from a valid dac1 value
1338 */
1339 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
1340 return -EIO;
1341 } else {
1342 /*
1343 * For range breakpoints, addr2 must also be a valid address
1344 */
1345 if (bp_info->addr2 >= TASK_SIZE)
1346 return -EIO;
1347 }
1348
1349 if (child->thread.dbcr0 &
1350 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
1351 return -ENOSPC;
1352
1353 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1354 child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
1355 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1356 child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
1357 child->thread.dac1 = bp_info->addr;
1358 child->thread.dac2 = bp_info->addr2;
1359 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
1360 child->thread.dbcr2 |= DBCR2_DAC12M;
1361 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1362 child->thread.dbcr2 |= DBCR2_DAC12MX;
1363 else /* PPC_BREAKPOINT_MODE_MASK */
1364 child->thread.dbcr2 |= DBCR2_DAC12MM;
1365 child->thread.regs->msr |= MSR_DE;
1366
1367 return 5;
1368 }
1369 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
1370
1371 static long ppc_set_hwdebug(struct task_struct *child,
1372 struct ppc_hw_breakpoint *bp_info)
1373 {
1374 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1375 int len = 0;
1376 struct thread_struct *thread = &(child->thread);
1377 struct perf_event *bp;
1378 struct perf_event_attr attr;
1379 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1380 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
1381 struct arch_hw_breakpoint brk;
1382 #endif
1383
1384 if (bp_info->version != 1)
1385 return -ENOTSUPP;
1386 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1387 /*
1388 * Check for invalid flags and combinations
1389 */
1390 if ((bp_info->trigger_type == 0) ||
1391 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
1392 PPC_BREAKPOINT_TRIGGER_RW)) ||
1393 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
1394 (bp_info->condition_mode &
1395 ~(PPC_BREAKPOINT_CONDITION_MODE |
1396 PPC_BREAKPOINT_CONDITION_BE_ALL)))
1397 return -EINVAL;
1398 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
1399 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1400 return -EINVAL;
1401 #endif
1402
1403 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
1404 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
1405 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
1406 return -EINVAL;
1407 return set_instruction_bp(child, bp_info);
1408 }
1409 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
1410 return set_dac(child, bp_info);
1411
1412 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1413 return set_dac_range(child, bp_info);
1414 #else
1415 return -EINVAL;
1416 #endif
1417 #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
1418 /*
1419 * We only support one data breakpoint
1420 */
1421 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
1422 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
1423 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1424 return -EINVAL;
1425
1426 if ((unsigned long)bp_info->addr >= TASK_SIZE)
1427 return -EIO;
1428
1429 brk.address = bp_info->addr & ~7UL;
1430 brk.type = HW_BRK_TYPE_TRANSLATE;
1431 brk.len = 8;
1432 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1433 brk.type |= HW_BRK_TYPE_READ;
1434 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1435 brk.type |= HW_BRK_TYPE_WRITE;
1436 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1437 if (ptrace_get_breakpoints(child) < 0)
1438 return -ESRCH;
1439
1440 /*
1441 * Check if the request is for 'range' breakpoints. We can
1442 * support it if range < 8 bytes.
1443 */
1444 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) {
1445 len = bp_info->addr2 - bp_info->addr;
1446 } else if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1447 ptrace_put_breakpoints(child);
1448 return -EINVAL;
1449 }
1450 bp = thread->ptrace_bps[0];
1451 if (bp) {
1452 ptrace_put_breakpoints(child);
1453 return -ENOSPC;
1454 }
1455
1456 /* Create a new breakpoint request if one doesn't exist already */
1457 hw_breakpoint_init(&attr);
1458 attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
1459 attr.bp_len = len;
1460 arch_bp_generic_fields(brk.type, &attr.bp_type);
1461
1462 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
1463 ptrace_triggered, NULL, child);
1464 if (IS_ERR(bp)) {
1465 thread->ptrace_bps[0] = NULL;
1466 ptrace_put_breakpoints(child);
1467 return PTR_ERR(bp);
1468 }
1469
1470 ptrace_put_breakpoints(child);
1471 return 1;
1472 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1473
1474 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
1475 return -EINVAL;
1476
1477 if (child->thread.hw_brk.address)
1478 return -ENOSPC;
1479
1480 child->thread.hw_brk = brk;
1481
1482 return 1;
1483 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
1484 }
1485
1486 static long ppc_del_hwdebug(struct task_struct *child, long data)
1487 {
1488 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1489 int ret = 0;
1490 struct thread_struct *thread = &(child->thread);
1491 struct perf_event *bp;
1492 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1493 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1494 int rc;
1495
1496 if (data <= 4)
1497 rc = del_instruction_bp(child, (int)data);
1498 else
1499 rc = del_dac(child, (int)data - 4);
1500
1501 if (!rc) {
1502 if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
1503 child->thread.dbcr1)) {
1504 child->thread.dbcr0 &= ~DBCR0_IDM;
1505 child->thread.regs->msr &= ~MSR_DE;
1506 }
1507 }
1508 return rc;
1509 #else
1510 if (data != 1)
1511 return -EINVAL;
1512
1513 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1514 if (ptrace_get_breakpoints(child) < 0)
1515 return -ESRCH;
1516
1517 bp = thread->ptrace_bps[0];
1518 if (bp) {
1519 unregister_hw_breakpoint(bp);
1520 thread->ptrace_bps[0] = NULL;
1521 } else
1522 ret = -ENOENT;
1523 ptrace_put_breakpoints(child);
1524 return ret;
1525 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1526 if (child->thread.hw_brk.address == 0)
1527 return -ENOENT;
1528
1529 child->thread.hw_brk.address = 0;
1530 child->thread.hw_brk.type = 0;
1531 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1532
1533 return 0;
1534 #endif
1535 }
1536
1537 long arch_ptrace(struct task_struct *child, long request,
1538 unsigned long addr, unsigned long data)
1539 {
1540 int ret = -EPERM;
1541 void __user *datavp = (void __user *) data;
1542 unsigned long __user *datalp = datavp;
1543
1544 switch (request) {
1545 /* read the word at location addr in the USER area. */
1546 case PTRACE_PEEKUSR: {
1547 unsigned long index, tmp;
1548
1549 ret = -EIO;
1550 /* convert to index and check */
1551 #ifdef CONFIG_PPC32
1552 index = addr >> 2;
1553 if ((addr & 3) || (index > PT_FPSCR)
1554 || (child->thread.regs == NULL))
1555 #else
1556 index = addr >> 3;
1557 if ((addr & 7) || (index > PT_FPSCR))
1558 #endif
1559 break;
1560
1561 CHECK_FULL_REGS(child->thread.regs);
1562 if (index < PT_FPR0) {
1563 tmp = ptrace_get_reg(child, (int) index);
1564 } else {
1565 unsigned int fpidx = index - PT_FPR0;
1566
1567 flush_fp_to_thread(child);
1568 if (fpidx < (PT_FPSCR - PT_FPR0))
1569 tmp = ((unsigned long *)child->thread.fpr)
1570 [fpidx * TS_FPRWIDTH];
1571 else
1572 tmp = child->thread.fpscr.val;
1573 }
1574 ret = put_user(tmp, datalp);
1575 break;
1576 }
1577
1578 /* write the word at location addr in the USER area */
1579 case PTRACE_POKEUSR: {
1580 unsigned long index;
1581
1582 ret = -EIO;
1583 /* convert to index and check */
1584 #ifdef CONFIG_PPC32
1585 index = addr >> 2;
1586 if ((addr & 3) || (index > PT_FPSCR)
1587 || (child->thread.regs == NULL))
1588 #else
1589 index = addr >> 3;
1590 if ((addr & 7) || (index > PT_FPSCR))
1591 #endif
1592 break;
1593
1594 CHECK_FULL_REGS(child->thread.regs);
1595 if (index < PT_FPR0) {
1596 ret = ptrace_put_reg(child, index, data);
1597 } else {
1598 unsigned int fpidx = index - PT_FPR0;
1599
1600 flush_fp_to_thread(child);
1601 if (fpidx < (PT_FPSCR - PT_FPR0))
1602 ((unsigned long *)child->thread.fpr)
1603 [fpidx * TS_FPRWIDTH] = data;
1604 else
1605 child->thread.fpscr.val = data;
1606 ret = 0;
1607 }
1608 break;
1609 }
1610
1611 case PPC_PTRACE_GETHWDBGINFO: {
1612 struct ppc_debug_info dbginfo;
1613
1614 dbginfo.version = 1;
1615 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1616 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
1617 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
1618 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
1619 dbginfo.data_bp_alignment = 4;
1620 dbginfo.sizeof_condition = 4;
1621 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
1622 PPC_DEBUG_FEATURE_INSN_BP_MASK;
1623 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1624 dbginfo.features |=
1625 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
1626 PPC_DEBUG_FEATURE_DATA_BP_MASK;
1627 #endif
1628 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
1629 dbginfo.num_instruction_bps = 0;
1630 dbginfo.num_data_bps = 1;
1631 dbginfo.num_condition_regs = 0;
1632 #ifdef CONFIG_PPC64
1633 dbginfo.data_bp_alignment = 8;
1634 #else
1635 dbginfo.data_bp_alignment = 4;
1636 #endif
1637 dbginfo.sizeof_condition = 0;
1638 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1639 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
1640 #else
1641 dbginfo.features = 0;
1642 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1643 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1644
1645 if (!access_ok(VERIFY_WRITE, datavp,
1646 sizeof(struct ppc_debug_info)))
1647 return -EFAULT;
1648 ret = __copy_to_user(datavp, &dbginfo,
1649 sizeof(struct ppc_debug_info)) ?
1650 -EFAULT : 0;
1651 break;
1652 }
1653
1654 case PPC_PTRACE_SETHWDEBUG: {
1655 struct ppc_hw_breakpoint bp_info;
1656
1657 if (!access_ok(VERIFY_READ, datavp,
1658 sizeof(struct ppc_hw_breakpoint)))
1659 return -EFAULT;
1660 ret = __copy_from_user(&bp_info, datavp,
1661 sizeof(struct ppc_hw_breakpoint)) ?
1662 -EFAULT : 0;
1663 if (!ret)
1664 ret = ppc_set_hwdebug(child, &bp_info);
1665 break;
1666 }
1667
1668 case PPC_PTRACE_DELHWDEBUG: {
1669 ret = ppc_del_hwdebug(child, data);
1670 break;
1671 }
1672
1673 case PTRACE_GET_DEBUGREG: {
1674 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
1675 unsigned long dabr_fake;
1676 #endif
1677 ret = -EINVAL;
1678 /* We only support one DABR and no IABRS at the moment */
1679 if (addr > 0)
1680 break;
1681 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1682 ret = put_user(child->thread.dac1, datalp);
1683 #else
1684 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
1685 (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
1686 ret = put_user(dabr_fake, datalp);
1687 #endif
1688 break;
1689 }
1690
1691 case PTRACE_SET_DEBUGREG:
1692 ret = ptrace_set_debugreg(child, addr, data);
1693 break;
1694
1695 #ifdef CONFIG_PPC64
1696 case PTRACE_GETREGS64:
1697 #endif
1698 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
1699 return copy_regset_to_user(child, &user_ppc_native_view,
1700 REGSET_GPR,
1701 0, sizeof(struct pt_regs),
1702 datavp);
1703
1704 #ifdef CONFIG_PPC64
1705 case PTRACE_SETREGS64:
1706 #endif
1707 case PTRACE_SETREGS: /* Set all gp regs in the child. */
1708 return copy_regset_from_user(child, &user_ppc_native_view,
1709 REGSET_GPR,
1710 0, sizeof(struct pt_regs),
1711 datavp);
1712
1713 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
1714 return copy_regset_to_user(child, &user_ppc_native_view,
1715 REGSET_FPR,
1716 0, sizeof(elf_fpregset_t),
1717 datavp);
1718
1719 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
1720 return copy_regset_from_user(child, &user_ppc_native_view,
1721 REGSET_FPR,
1722 0, sizeof(elf_fpregset_t),
1723 datavp);
1724
1725 #ifdef CONFIG_ALTIVEC
1726 case PTRACE_GETVRREGS:
1727 return copy_regset_to_user(child, &user_ppc_native_view,
1728 REGSET_VMX,
1729 0, (33 * sizeof(vector128) +
1730 sizeof(u32)),
1731 datavp);
1732
1733 case PTRACE_SETVRREGS:
1734 return copy_regset_from_user(child, &user_ppc_native_view,
1735 REGSET_VMX,
1736 0, (33 * sizeof(vector128) +
1737 sizeof(u32)),
1738 datavp);
1739 #endif
1740 #ifdef CONFIG_VSX
1741 case PTRACE_GETVSRREGS:
1742 return copy_regset_to_user(child, &user_ppc_native_view,
1743 REGSET_VSX,
1744 0, 32 * sizeof(double),
1745 datavp);
1746
1747 case PTRACE_SETVSRREGS:
1748 return copy_regset_from_user(child, &user_ppc_native_view,
1749 REGSET_VSX,
1750 0, 32 * sizeof(double),
1751 datavp);
1752 #endif
1753 #ifdef CONFIG_SPE
1754 case PTRACE_GETEVRREGS:
1755 /* Get the child spe register state. */
1756 return copy_regset_to_user(child, &user_ppc_native_view,
1757 REGSET_SPE, 0, 35 * sizeof(u32),
1758 datavp);
1759
1760 case PTRACE_SETEVRREGS:
1761 /* Set the child spe register state. */
1762 return copy_regset_from_user(child, &user_ppc_native_view,
1763 REGSET_SPE, 0, 35 * sizeof(u32),
1764 datavp);
1765 #endif
1766
1767 default:
1768 ret = ptrace_request(child, request, addr, data);
1769 break;
1770 }
1771 return ret;
1772 }
1773
1774 /*
1775 * We must return the syscall number to actually look up in the table.
1776 * This can be -1L to skip running any syscall at all.
1777 */
1778 long do_syscall_trace_enter(struct pt_regs *regs)
1779 {
1780 long ret = 0;
1781
1782 secure_computing_strict(regs->gpr[0]);
1783
1784 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
1785 tracehook_report_syscall_entry(regs))
1786 /*
1787 * Tracing decided this syscall should not happen.
1788 * We'll return a bogus call number to get an ENOSYS
1789 * error, but leave the original number in regs->gpr[0].
1790 */
1791 ret = -1L;
1792
1793 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1794 trace_sys_enter(regs, regs->gpr[0]);
1795
1796 #ifdef CONFIG_PPC64
1797 if (!is_32bit_task())
1798 audit_syscall_entry(AUDIT_ARCH_PPC64,
1799 regs->gpr[0],
1800 regs->gpr[3], regs->gpr[4],
1801 regs->gpr[5], regs->gpr[6]);
1802 else
1803 #endif
1804 audit_syscall_entry(AUDIT_ARCH_PPC,
1805 regs->gpr[0],
1806 regs->gpr[3] & 0xffffffff,
1807 regs->gpr[4] & 0xffffffff,
1808 regs->gpr[5] & 0xffffffff,
1809 regs->gpr[6] & 0xffffffff);
1810
1811 return ret ?: regs->gpr[0];
1812 }
1813
1814 void do_syscall_trace_leave(struct pt_regs *regs)
1815 {
1816 int step;
1817
1818 audit_syscall_exit(regs);
1819
1820 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1821 trace_sys_exit(regs, regs->result);
1822
1823 step = test_thread_flag(TIF_SINGLESTEP);
1824 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
1825 tracehook_report_syscall_exit(regs, step);
1826 }
Linux kernel - Deliverables
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