3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
21 #include <linux/smp.h>
22 #include <linux/errno.h>
23 #include <linux/ptrace.h>
24 #include <linux/regset.h>
25 #include <linux/tracehook.h>
26 #include <linux/elf.h>
27 #include <linux/user.h>
28 #include <linux/security.h>
29 #include <linux/signal.h>
30 #include <linux/seccomp.h>
31 #include <linux/audit.h>
32 #include <trace/syscall.h>
33 #include <linux/hw_breakpoint.h>
34 #include <linux/perf_event.h>
35 #include <linux/context_tracking.h>
37 #include <asm/uaccess.h>
39 #include <asm/pgtable.h>
40 #include <asm/switch_to.h>
42 #define CREATE_TRACE_POINTS
43 #include <trace/events/syscalls.h>
46 * The parameter save area on the stack is used to store arguments being passed
47 * to callee function and is located at fixed offset from stack pointer.
50 #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
51 #else /* CONFIG_PPC32 */
52 #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
55 struct pt_regs_offset
{
60 #define STR(s) #s /* convert to string */
61 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
62 #define GPR_OFFSET_NAME(num) \
63 {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \
64 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
65 #define REG_OFFSET_END {.name = NULL, .offset = 0}
67 #define TVSO(f) (offsetof(struct thread_vr_state, f))
68 #define TFSO(f) (offsetof(struct thread_fp_state, f))
69 #define TSO(f) (offsetof(struct thread_struct, f))
71 static const struct pt_regs_offset regoffset_table
[] = {
104 REG_OFFSET_NAME(nip
),
105 REG_OFFSET_NAME(msr
),
106 REG_OFFSET_NAME(ctr
),
107 REG_OFFSET_NAME(link
),
108 REG_OFFSET_NAME(xer
),
109 REG_OFFSET_NAME(ccr
),
111 REG_OFFSET_NAME(softe
),
115 REG_OFFSET_NAME(trap
),
116 REG_OFFSET_NAME(dar
),
117 REG_OFFSET_NAME(dsisr
),
122 * regs_query_register_offset() - query register offset from its name
123 * @name: the name of a register
125 * regs_query_register_offset() returns the offset of a register in struct
126 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
128 int regs_query_register_offset(const char *name
)
130 const struct pt_regs_offset
*roff
;
131 for (roff
= regoffset_table
; roff
->name
!= NULL
; roff
++)
132 if (!strcmp(roff
->name
, name
))
138 * regs_query_register_name() - query register name from its offset
139 * @offset: the offset of a register in struct pt_regs.
141 * regs_query_register_name() returns the name of a register from its
142 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
144 const char *regs_query_register_name(unsigned int offset
)
146 const struct pt_regs_offset
*roff
;
147 for (roff
= regoffset_table
; roff
->name
!= NULL
; roff
++)
148 if (roff
->offset
== offset
)
154 * does not yet catch signals sent when the child dies.
155 * in exit.c or in signal.c.
159 * Set of msr bits that gdb can change on behalf of a process.
161 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
162 #define MSR_DEBUGCHANGE 0
164 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
168 * Max register writeable via put_reg
171 #define PT_MAX_PUT_REG PT_MQ
173 #define PT_MAX_PUT_REG PT_CCR
176 static unsigned long get_user_msr(struct task_struct
*task
)
178 return task
->thread
.regs
->msr
| task
->thread
.fpexc_mode
;
181 static int set_user_msr(struct task_struct
*task
, unsigned long msr
)
183 task
->thread
.regs
->msr
&= ~MSR_DEBUGCHANGE
;
184 task
->thread
.regs
->msr
|= msr
& MSR_DEBUGCHANGE
;
188 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
189 static unsigned long get_user_ckpt_msr(struct task_struct
*task
)
191 return task
->thread
.ckpt_regs
.msr
| task
->thread
.fpexc_mode
;
194 static int set_user_ckpt_msr(struct task_struct
*task
, unsigned long msr
)
196 task
->thread
.ckpt_regs
.msr
&= ~MSR_DEBUGCHANGE
;
197 task
->thread
.ckpt_regs
.msr
|= msr
& MSR_DEBUGCHANGE
;
201 static int set_user_ckpt_trap(struct task_struct
*task
, unsigned long trap
)
203 task
->thread
.ckpt_regs
.trap
= trap
& 0xfff0;
209 static int get_user_dscr(struct task_struct
*task
, unsigned long *data
)
211 *data
= task
->thread
.dscr
;
215 static int set_user_dscr(struct task_struct
*task
, unsigned long dscr
)
217 task
->thread
.dscr
= dscr
;
218 task
->thread
.dscr_inherit
= 1;
222 static int get_user_dscr(struct task_struct
*task
, unsigned long *data
)
227 static int set_user_dscr(struct task_struct
*task
, unsigned long dscr
)
234 * We prevent mucking around with the reserved area of trap
235 * which are used internally by the kernel.
237 static int set_user_trap(struct task_struct
*task
, unsigned long trap
)
239 task
->thread
.regs
->trap
= trap
& 0xfff0;
244 * Get contents of register REGNO in task TASK.
246 int ptrace_get_reg(struct task_struct
*task
, int regno
, unsigned long *data
)
248 if ((task
->thread
.regs
== NULL
) || !data
)
251 if (regno
== PT_MSR
) {
252 *data
= get_user_msr(task
);
256 if (regno
== PT_DSCR
)
257 return get_user_dscr(task
, data
);
259 if (regno
< (sizeof(struct pt_regs
) / sizeof(unsigned long))) {
260 *data
= ((unsigned long *)task
->thread
.regs
)[regno
];
268 * Write contents of register REGNO in task TASK.
270 int ptrace_put_reg(struct task_struct
*task
, int regno
, unsigned long data
)
272 if (task
->thread
.regs
== NULL
)
276 return set_user_msr(task
, data
);
277 if (regno
== PT_TRAP
)
278 return set_user_trap(task
, data
);
279 if (regno
== PT_DSCR
)
280 return set_user_dscr(task
, data
);
282 if (regno
<= PT_MAX_PUT_REG
) {
283 ((unsigned long *)task
->thread
.regs
)[regno
] = data
;
289 static int gpr_get(struct task_struct
*target
, const struct user_regset
*regset
,
290 unsigned int pos
, unsigned int count
,
291 void *kbuf
, void __user
*ubuf
)
295 if (target
->thread
.regs
== NULL
)
298 if (!FULL_REGS(target
->thread
.regs
)) {
299 /* We have a partial register set. Fill 14-31 with bogus values */
300 for (i
= 14; i
< 32; i
++)
301 target
->thread
.regs
->gpr
[i
] = NV_REG_POISON
;
304 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
306 0, offsetof(struct pt_regs
, msr
));
308 unsigned long msr
= get_user_msr(target
);
309 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, &msr
,
310 offsetof(struct pt_regs
, msr
),
311 offsetof(struct pt_regs
, msr
) +
315 BUILD_BUG_ON(offsetof(struct pt_regs
, orig_gpr3
) !=
316 offsetof(struct pt_regs
, msr
) + sizeof(long));
319 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
320 &target
->thread
.regs
->orig_gpr3
,
321 offsetof(struct pt_regs
, orig_gpr3
),
322 sizeof(struct pt_regs
));
324 ret
= user_regset_copyout_zero(&pos
, &count
, &kbuf
, &ubuf
,
325 sizeof(struct pt_regs
), -1);
330 static int gpr_set(struct task_struct
*target
, const struct user_regset
*regset
,
331 unsigned int pos
, unsigned int count
,
332 const void *kbuf
, const void __user
*ubuf
)
337 if (target
->thread
.regs
== NULL
)
340 CHECK_FULL_REGS(target
->thread
.regs
);
342 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
344 0, PT_MSR
* sizeof(reg
));
346 if (!ret
&& count
> 0) {
347 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, ®
,
348 PT_MSR
* sizeof(reg
),
349 (PT_MSR
+ 1) * sizeof(reg
));
351 ret
= set_user_msr(target
, reg
);
354 BUILD_BUG_ON(offsetof(struct pt_regs
, orig_gpr3
) !=
355 offsetof(struct pt_regs
, msr
) + sizeof(long));
358 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
359 &target
->thread
.regs
->orig_gpr3
,
360 PT_ORIG_R3
* sizeof(reg
),
361 (PT_MAX_PUT_REG
+ 1) * sizeof(reg
));
363 if (PT_MAX_PUT_REG
+ 1 < PT_TRAP
&& !ret
)
364 ret
= user_regset_copyin_ignore(
365 &pos
, &count
, &kbuf
, &ubuf
,
366 (PT_MAX_PUT_REG
+ 1) * sizeof(reg
),
367 PT_TRAP
* sizeof(reg
));
369 if (!ret
&& count
> 0) {
370 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, ®
,
371 PT_TRAP
* sizeof(reg
),
372 (PT_TRAP
+ 1) * sizeof(reg
));
374 ret
= set_user_trap(target
, reg
);
378 ret
= user_regset_copyin_ignore(
379 &pos
, &count
, &kbuf
, &ubuf
,
380 (PT_TRAP
+ 1) * sizeof(reg
), -1);
386 * When the transaction is active, 'transact_fp' holds the current running
387 * value of all FPR registers and 'fp_state' holds the last checkpointed
388 * value of all FPR registers for the current transaction. When transaction
389 * is not active 'fp_state' holds the current running state of all the FPR
390 * registers. So this function which returns the current running values of
391 * all the FPR registers, needs to know whether any transaction is active
394 * Userspace interface buffer layout:
401 * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
402 * which determines the final code in this function. All the combinations of
403 * these two config options are possible except the one below as transactional
404 * memory config pulls in CONFIG_VSX automatically.
406 * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
408 static int fpr_get(struct task_struct
*target
, const struct user_regset
*regset
,
409 unsigned int pos
, unsigned int count
,
410 void *kbuf
, void __user
*ubuf
)
416 flush_fp_to_thread(target
);
418 #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
419 /* copy to local buffer then write that out */
420 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
)) {
421 flush_altivec_to_thread(target
);
422 flush_tmregs_to_thread(target
);
423 for (i
= 0; i
< 32 ; i
++)
424 buf
[i
] = target
->thread
.TS_TRANS_FPR(i
);
425 buf
[32] = target
->thread
.transact_fp
.fpscr
;
427 for (i
= 0; i
< 32 ; i
++)
428 buf
[i
] = target
->thread
.TS_FPR(i
);
429 buf
[32] = target
->thread
.fp_state
.fpscr
;
431 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
434 #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
435 /* copy to local buffer then write that out */
436 for (i
= 0; i
< 32 ; i
++)
437 buf
[i
] = target
->thread
.TS_FPR(i
);
438 buf
[32] = target
->thread
.fp_state
.fpscr
;
439 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
442 #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
443 BUILD_BUG_ON(offsetof(struct thread_fp_state
, fpscr
) !=
444 offsetof(struct thread_fp_state
, fpr
[32]));
446 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
447 &target
->thread
.fp_state
, 0, -1);
452 * When the transaction is active, 'transact_fp' holds the current running
453 * value of all FPR registers and 'fp_state' holds the last checkpointed
454 * value of all FPR registers for the current transaction. When transaction
455 * is not active 'fp_state' holds the current running state of all the FPR
456 * registers. So this function which setss the current running values of
457 * all the FPR registers, needs to know whether any transaction is active
460 * Userspace interface buffer layout:
467 * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
468 * which determines the final code in this function. All the combinations of
469 * these two config options are possible except the one below as transactional
470 * memory config pulls in CONFIG_VSX automatically.
472 * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
474 static int fpr_set(struct task_struct
*target
, const struct user_regset
*regset
,
475 unsigned int pos
, unsigned int count
,
476 const void *kbuf
, const void __user
*ubuf
)
482 flush_fp_to_thread(target
);
484 #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
485 /* copy to local buffer then write that out */
486 i
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
490 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
)) {
491 flush_altivec_to_thread(target
);
492 flush_tmregs_to_thread(target
);
493 for (i
= 0; i
< 32 ; i
++)
494 target
->thread
.TS_TRANS_FPR(i
) = buf
[i
];
495 target
->thread
.transact_fp
.fpscr
= buf
[32];
497 for (i
= 0; i
< 32 ; i
++)
498 target
->thread
.TS_FPR(i
) = buf
[i
];
499 target
->thread
.fp_state
.fpscr
= buf
[32];
504 #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
505 /* copy to local buffer then write that out */
506 i
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
509 for (i
= 0; i
< 32 ; i
++)
510 target
->thread
.TS_FPR(i
) = buf
[i
];
511 target
->thread
.fp_state
.fpscr
= buf
[32];
515 #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
516 BUILD_BUG_ON(offsetof(struct thread_fp_state
, fpscr
) !=
517 offsetof(struct thread_fp_state
, fpr
[32]));
519 return user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
520 &target
->thread
.fp_state
, 0, -1);
524 #ifdef CONFIG_ALTIVEC
526 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
527 * The transfer totals 34 quadword. Quadwords 0-31 contain the
528 * corresponding vector registers. Quadword 32 contains the vscr as the
529 * last word (offset 12) within that quadword. Quadword 33 contains the
530 * vrsave as the first word (offset 0) within the quadword.
532 * This definition of the VMX state is compatible with the current PPC32
533 * ptrace interface. This allows signal handling and ptrace to use the
534 * same structures. This also simplifies the implementation of a bi-arch
535 * (combined (32- and 64-bit) gdb.
538 static int vr_active(struct task_struct
*target
,
539 const struct user_regset
*regset
)
541 flush_altivec_to_thread(target
);
542 return target
->thread
.used_vr
? regset
->n
: 0;
546 * When the transaction is active, 'transact_vr' holds the current running
547 * value of all the VMX registers and 'vr_state' holds the last checkpointed
548 * value of all the VMX registers for the current transaction to fall back
549 * on in case it aborts. When transaction is not active 'vr_state' holds
550 * the current running state of all the VMX registers. So this function which
551 * gets the current running values of all the VMX registers, needs to know
552 * whether any transaction is active or not.
554 * Userspace interface buffer layout:
562 static int vr_get(struct task_struct
*target
, const struct user_regset
*regset
,
563 unsigned int pos
, unsigned int count
,
564 void *kbuf
, void __user
*ubuf
)
566 struct thread_vr_state
*addr
;
569 flush_altivec_to_thread(target
);
571 BUILD_BUG_ON(offsetof(struct thread_vr_state
, vscr
) !=
572 offsetof(struct thread_vr_state
, vr
[32]));
574 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
575 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
)) {
576 flush_fp_to_thread(target
);
577 flush_tmregs_to_thread(target
);
578 addr
= &target
->thread
.transact_vr
;
580 addr
= &target
->thread
.vr_state
;
583 addr
= &target
->thread
.vr_state
;
585 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
587 33 * sizeof(vector128
));
590 * Copy out only the low-order word of vrsave.
596 memset(&vrsave
, 0, sizeof(vrsave
));
598 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
599 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
600 vrsave
.word
= target
->thread
.transact_vrsave
;
602 vrsave
.word
= target
->thread
.vrsave
;
604 vrsave
.word
= target
->thread
.vrsave
;
607 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, &vrsave
,
608 33 * sizeof(vector128
), -1);
615 * When the transaction is active, 'transact_vr' holds the current running
616 * value of all the VMX registers and 'vr_state' holds the last checkpointed
617 * value of all the VMX registers for the current transaction to fall back
618 * on in case it aborts. When transaction is not active 'vr_state' holds
619 * the current running state of all the VMX registers. So this function which
620 * sets the current running values of all the VMX registers, needs to know
621 * whether any transaction is active or not.
623 * Userspace interface buffer layout:
631 static int vr_set(struct task_struct
*target
, const struct user_regset
*regset
,
632 unsigned int pos
, unsigned int count
,
633 const void *kbuf
, const void __user
*ubuf
)
635 struct thread_vr_state
*addr
;
638 flush_altivec_to_thread(target
);
640 BUILD_BUG_ON(offsetof(struct thread_vr_state
, vscr
) !=
641 offsetof(struct thread_vr_state
, vr
[32]));
643 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
644 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
)) {
645 flush_fp_to_thread(target
);
646 flush_tmregs_to_thread(target
);
647 addr
= &target
->thread
.transact_vr
;
649 addr
= &target
->thread
.vr_state
;
652 addr
= &target
->thread
.vr_state
;
654 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
656 33 * sizeof(vector128
));
657 if (!ret
&& count
> 0) {
659 * We use only the first word of vrsave.
665 memset(&vrsave
, 0, sizeof(vrsave
));
667 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
668 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
669 vrsave
.word
= target
->thread
.transact_vrsave
;
671 vrsave
.word
= target
->thread
.vrsave
;
673 vrsave
.word
= target
->thread
.vrsave
;
675 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, &vrsave
,
676 33 * sizeof(vector128
), -1);
679 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
680 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
681 target
->thread
.transact_vrsave
= vrsave
.word
;
683 target
->thread
.vrsave
= vrsave
.word
;
685 target
->thread
.vrsave
= vrsave
.word
;
692 #endif /* CONFIG_ALTIVEC */
696 * Currently to set and and get all the vsx state, you need to call
697 * the fp and VMX calls as well. This only get/sets the lower 32
698 * 128bit VSX registers.
701 static int vsr_active(struct task_struct
*target
,
702 const struct user_regset
*regset
)
704 flush_vsx_to_thread(target
);
705 return target
->thread
.used_vsr
? regset
->n
: 0;
709 * When the transaction is active, 'transact_fp' holds the current running
710 * value of all FPR registers and 'fp_state' holds the last checkpointed
711 * value of all FPR registers for the current transaction. When transaction
712 * is not active 'fp_state' holds the current running state of all the FPR
713 * registers. So this function which returns the current running values of
714 * all the FPR registers, needs to know whether any transaction is active
717 * Userspace interface buffer layout:
723 static int vsr_get(struct task_struct
*target
, const struct user_regset
*regset
,
724 unsigned int pos
, unsigned int count
,
725 void *kbuf
, void __user
*ubuf
)
730 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
731 flush_fp_to_thread(target
);
732 flush_altivec_to_thread(target
);
733 flush_tmregs_to_thread(target
);
735 flush_vsx_to_thread(target
);
737 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
738 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
)) {
739 for (i
= 0; i
< 32 ; i
++)
740 buf
[i
] = target
->thread
.
741 transact_fp
.fpr
[i
][TS_VSRLOWOFFSET
];
743 for (i
= 0; i
< 32 ; i
++)
744 buf
[i
] = target
->thread
.
745 fp_state
.fpr
[i
][TS_VSRLOWOFFSET
];
748 for (i
= 0; i
< 32 ; i
++)
749 buf
[i
] = target
->thread
.fp_state
.fpr
[i
][TS_VSRLOWOFFSET
];
751 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
752 buf
, 0, 32 * sizeof(double));
758 * When the transaction is active, 'transact_fp' holds the current running
759 * value of all FPR registers and 'fp_state' holds the last checkpointed
760 * value of all FPR registers for the current transaction. When transaction
761 * is not active 'fp_state' holds the current running state of all the FPR
762 * registers. So this function which sets the current running values of all
763 * the FPR registers, needs to know whether any transaction is active or not.
765 * Userspace interface buffer layout:
771 static int vsr_set(struct task_struct
*target
, const struct user_regset
*regset
,
772 unsigned int pos
, unsigned int count
,
773 const void *kbuf
, const void __user
*ubuf
)
778 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
779 flush_fp_to_thread(target
);
780 flush_altivec_to_thread(target
);
781 flush_tmregs_to_thread(target
);
783 flush_vsx_to_thread(target
);
785 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
786 buf
, 0, 32 * sizeof(double));
788 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
789 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
)) {
790 for (i
= 0; i
< 32 ; i
++)
791 target
->thread
.transact_fp
.
792 fpr
[i
][TS_VSRLOWOFFSET
] = buf
[i
];
794 for (i
= 0; i
< 32 ; i
++)
795 target
->thread
.fp_state
.
796 fpr
[i
][TS_VSRLOWOFFSET
] = buf
[i
];
799 for (i
= 0; i
< 32 ; i
++)
800 target
->thread
.fp_state
.fpr
[i
][TS_VSRLOWOFFSET
] = buf
[i
];
806 #endif /* CONFIG_VSX */
811 * For get_evrregs/set_evrregs functions 'data' has the following layout:
820 static int evr_active(struct task_struct
*target
,
821 const struct user_regset
*regset
)
823 flush_spe_to_thread(target
);
824 return target
->thread
.used_spe
? regset
->n
: 0;
827 static int evr_get(struct task_struct
*target
, const struct user_regset
*regset
,
828 unsigned int pos
, unsigned int count
,
829 void *kbuf
, void __user
*ubuf
)
833 flush_spe_to_thread(target
);
835 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
837 0, sizeof(target
->thread
.evr
));
839 BUILD_BUG_ON(offsetof(struct thread_struct
, acc
) + sizeof(u64
) !=
840 offsetof(struct thread_struct
, spefscr
));
843 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
845 sizeof(target
->thread
.evr
), -1);
850 static int evr_set(struct task_struct
*target
, const struct user_regset
*regset
,
851 unsigned int pos
, unsigned int count
,
852 const void *kbuf
, const void __user
*ubuf
)
856 flush_spe_to_thread(target
);
858 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
860 0, sizeof(target
->thread
.evr
));
862 BUILD_BUG_ON(offsetof(struct thread_struct
, acc
) + sizeof(u64
) !=
863 offsetof(struct thread_struct
, spefscr
));
866 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
868 sizeof(target
->thread
.evr
), -1);
872 #endif /* CONFIG_SPE */
874 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
876 * tm_cgpr_active - get active number of registers in CGPR
877 * @target: The target task.
878 * @regset: The user regset structure.
880 * This function checks for the active number of available
881 * regisers in transaction checkpointed GPR category.
883 static int tm_cgpr_active(struct task_struct
*target
,
884 const struct user_regset
*regset
)
886 if (!cpu_has_feature(CPU_FTR_TM
))
889 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
896 * tm_cgpr_get - get CGPR registers
897 * @target: The target task.
898 * @regset: The user regset structure.
899 * @pos: The buffer position.
900 * @count: Number of bytes to copy.
901 * @kbuf: Kernel buffer to copy from.
902 * @ubuf: User buffer to copy into.
904 * This function gets transaction checkpointed GPR registers.
906 * When the transaction is active, 'ckpt_regs' holds all the checkpointed
907 * GPR register values for the current transaction to fall back on if it
908 * aborts in between. This function gets those checkpointed GPR registers.
909 * The userspace interface buffer layout is as follows.
912 * struct pt_regs ckpt_regs;
915 static int tm_cgpr_get(struct task_struct
*target
,
916 const struct user_regset
*regset
,
917 unsigned int pos
, unsigned int count
,
918 void *kbuf
, void __user
*ubuf
)
922 if (!cpu_has_feature(CPU_FTR_TM
))
925 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
928 flush_fp_to_thread(target
);
929 flush_altivec_to_thread(target
);
930 flush_tmregs_to_thread(target
);
932 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
933 &target
->thread
.ckpt_regs
,
934 0, offsetof(struct pt_regs
, msr
));
936 unsigned long msr
= get_user_ckpt_msr(target
);
938 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, &msr
,
939 offsetof(struct pt_regs
, msr
),
940 offsetof(struct pt_regs
, msr
) +
944 BUILD_BUG_ON(offsetof(struct pt_regs
, orig_gpr3
) !=
945 offsetof(struct pt_regs
, msr
) + sizeof(long));
948 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
949 &target
->thread
.ckpt_regs
.orig_gpr3
,
950 offsetof(struct pt_regs
, orig_gpr3
),
951 sizeof(struct pt_regs
));
953 ret
= user_regset_copyout_zero(&pos
, &count
, &kbuf
, &ubuf
,
954 sizeof(struct pt_regs
), -1);
960 * tm_cgpr_set - set the CGPR registers
961 * @target: The target task.
962 * @regset: The user regset structure.
963 * @pos: The buffer position.
964 * @count: Number of bytes to copy.
965 * @kbuf: Kernel buffer to copy into.
966 * @ubuf: User buffer to copy from.
968 * This function sets in transaction checkpointed GPR registers.
970 * When the transaction is active, 'ckpt_regs' holds the checkpointed
971 * GPR register values for the current transaction to fall back on if it
972 * aborts in between. This function sets those checkpointed GPR registers.
973 * The userspace interface buffer layout is as follows.
976 * struct pt_regs ckpt_regs;
979 static int tm_cgpr_set(struct task_struct
*target
,
980 const struct user_regset
*regset
,
981 unsigned int pos
, unsigned int count
,
982 const void *kbuf
, const void __user
*ubuf
)
987 if (!cpu_has_feature(CPU_FTR_TM
))
990 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
993 flush_fp_to_thread(target
);
994 flush_altivec_to_thread(target
);
995 flush_tmregs_to_thread(target
);
997 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
998 &target
->thread
.ckpt_regs
,
999 0, PT_MSR
* sizeof(reg
));
1001 if (!ret
&& count
> 0) {
1002 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, ®
,
1003 PT_MSR
* sizeof(reg
),
1004 (PT_MSR
+ 1) * sizeof(reg
));
1006 ret
= set_user_ckpt_msr(target
, reg
);
1009 BUILD_BUG_ON(offsetof(struct pt_regs
, orig_gpr3
) !=
1010 offsetof(struct pt_regs
, msr
) + sizeof(long));
1013 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1014 &target
->thread
.ckpt_regs
.orig_gpr3
,
1015 PT_ORIG_R3
* sizeof(reg
),
1016 (PT_MAX_PUT_REG
+ 1) * sizeof(reg
));
1018 if (PT_MAX_PUT_REG
+ 1 < PT_TRAP
&& !ret
)
1019 ret
= user_regset_copyin_ignore(
1020 &pos
, &count
, &kbuf
, &ubuf
,
1021 (PT_MAX_PUT_REG
+ 1) * sizeof(reg
),
1022 PT_TRAP
* sizeof(reg
));
1024 if (!ret
&& count
> 0) {
1025 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, ®
,
1026 PT_TRAP
* sizeof(reg
),
1027 (PT_TRAP
+ 1) * sizeof(reg
));
1029 ret
= set_user_ckpt_trap(target
, reg
);
1033 ret
= user_regset_copyin_ignore(
1034 &pos
, &count
, &kbuf
, &ubuf
,
1035 (PT_TRAP
+ 1) * sizeof(reg
), -1);
1041 * tm_cfpr_active - get active number of registers in CFPR
1042 * @target: The target task.
1043 * @regset: The user regset structure.
1045 * This function checks for the active number of available
1046 * regisers in transaction checkpointed FPR category.
1048 static int tm_cfpr_active(struct task_struct
*target
,
1049 const struct user_regset
*regset
)
1051 if (!cpu_has_feature(CPU_FTR_TM
))
1054 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1061 * tm_cfpr_get - get CFPR registers
1062 * @target: The target task.
1063 * @regset: The user regset structure.
1064 * @pos: The buffer position.
1065 * @count: Number of bytes to copy.
1066 * @kbuf: Kernel buffer to copy from.
1067 * @ubuf: User buffer to copy into.
1069 * This function gets in transaction checkpointed FPR registers.
1071 * When the transaction is active 'fp_state' holds the checkpointed
1072 * values for the current transaction to fall back on if it aborts
1073 * in between. This function gets those checkpointed FPR registers.
1074 * The userspace interface buffer layout is as follows.
1081 static int tm_cfpr_get(struct task_struct
*target
,
1082 const struct user_regset
*regset
,
1083 unsigned int pos
, unsigned int count
,
1084 void *kbuf
, void __user
*ubuf
)
1089 if (!cpu_has_feature(CPU_FTR_TM
))
1092 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1095 flush_fp_to_thread(target
);
1096 flush_altivec_to_thread(target
);
1097 flush_tmregs_to_thread(target
);
1099 /* copy to local buffer then write that out */
1100 for (i
= 0; i
< 32 ; i
++)
1101 buf
[i
] = target
->thread
.TS_FPR(i
);
1102 buf
[32] = target
->thread
.fp_state
.fpscr
;
1103 return user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
1107 * tm_cfpr_set - set CFPR registers
1108 * @target: The target task.
1109 * @regset: The user regset structure.
1110 * @pos: The buffer position.
1111 * @count: Number of bytes to copy.
1112 * @kbuf: Kernel buffer to copy into.
1113 * @ubuf: User buffer to copy from.
1115 * This function sets in transaction checkpointed FPR registers.
1117 * When the transaction is active 'fp_state' holds the checkpointed
1118 * FPR register values for the current transaction to fall back on
1119 * if it aborts in between. This function sets these checkpointed
1120 * FPR registers. The userspace interface buffer layout is as follows.
1127 static int tm_cfpr_set(struct task_struct
*target
,
1128 const struct user_regset
*regset
,
1129 unsigned int pos
, unsigned int count
,
1130 const void *kbuf
, const void __user
*ubuf
)
1135 if (!cpu_has_feature(CPU_FTR_TM
))
1138 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1141 flush_fp_to_thread(target
);
1142 flush_altivec_to_thread(target
);
1143 flush_tmregs_to_thread(target
);
1145 /* copy to local buffer then write that out */
1146 i
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, buf
, 0, -1);
1149 for (i
= 0; i
< 32 ; i
++)
1150 target
->thread
.TS_FPR(i
) = buf
[i
];
1151 target
->thread
.fp_state
.fpscr
= buf
[32];
1156 * tm_cvmx_active - get active number of registers in CVMX
1157 * @target: The target task.
1158 * @regset: The user regset structure.
1160 * This function checks for the active number of available
1161 * regisers in checkpointed VMX category.
1163 static int tm_cvmx_active(struct task_struct
*target
,
1164 const struct user_regset
*regset
)
1166 if (!cpu_has_feature(CPU_FTR_TM
))
1169 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1176 * tm_cvmx_get - get CMVX registers
1177 * @target: The target task.
1178 * @regset: The user regset structure.
1179 * @pos: The buffer position.
1180 * @count: Number of bytes to copy.
1181 * @kbuf: Kernel buffer to copy from.
1182 * @ubuf: User buffer to copy into.
1184 * This function gets in transaction checkpointed VMX registers.
1186 * When the transaction is active 'vr_state' and 'vr_save' hold
1187 * the checkpointed values for the current transaction to fall
1188 * back on if it aborts in between. The userspace interface buffer
1189 * layout is as follows.
1197 static int tm_cvmx_get(struct task_struct
*target
,
1198 const struct user_regset
*regset
,
1199 unsigned int pos
, unsigned int count
,
1200 void *kbuf
, void __user
*ubuf
)
1204 BUILD_BUG_ON(TVSO(vscr
) != TVSO(vr
[32]));
1206 if (!cpu_has_feature(CPU_FTR_TM
))
1209 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1212 /* Flush the state */
1213 flush_fp_to_thread(target
);
1214 flush_altivec_to_thread(target
);
1215 flush_tmregs_to_thread(target
);
1217 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1218 &target
->thread
.vr_state
, 0,
1219 33 * sizeof(vector128
));
1222 * Copy out only the low-order word of vrsave.
1228 memset(&vrsave
, 0, sizeof(vrsave
));
1229 vrsave
.word
= target
->thread
.vrsave
;
1230 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
, &vrsave
,
1231 33 * sizeof(vector128
), -1);
1238 * tm_cvmx_set - set CMVX registers
1239 * @target: The target task.
1240 * @regset: The user regset structure.
1241 * @pos: The buffer position.
1242 * @count: Number of bytes to copy.
1243 * @kbuf: Kernel buffer to copy into.
1244 * @ubuf: User buffer to copy from.
1246 * This function sets in transaction checkpointed VMX registers.
1248 * When the transaction is active 'vr_state' and 'vr_save' hold
1249 * the checkpointed values for the current transaction to fall
1250 * back on if it aborts in between. The userspace interface buffer
1251 * layout is as follows.
1259 static int tm_cvmx_set(struct task_struct
*target
,
1260 const struct user_regset
*regset
,
1261 unsigned int pos
, unsigned int count
,
1262 const void *kbuf
, const void __user
*ubuf
)
1266 BUILD_BUG_ON(TVSO(vscr
) != TVSO(vr
[32]));
1268 if (!cpu_has_feature(CPU_FTR_TM
))
1271 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1274 flush_fp_to_thread(target
);
1275 flush_altivec_to_thread(target
);
1276 flush_tmregs_to_thread(target
);
1278 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1279 &target
->thread
.vr_state
, 0,
1280 33 * sizeof(vector128
));
1281 if (!ret
&& count
> 0) {
1283 * We use only the low-order word of vrsave.
1289 memset(&vrsave
, 0, sizeof(vrsave
));
1290 vrsave
.word
= target
->thread
.vrsave
;
1291 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
, &vrsave
,
1292 33 * sizeof(vector128
), -1);
1294 target
->thread
.vrsave
= vrsave
.word
;
1301 * tm_cvsx_active - get active number of registers in CVSX
1302 * @target: The target task.
1303 * @regset: The user regset structure.
1305 * This function checks for the active number of available
1306 * regisers in transaction checkpointed VSX category.
1308 static int tm_cvsx_active(struct task_struct
*target
,
1309 const struct user_regset
*regset
)
1311 if (!cpu_has_feature(CPU_FTR_TM
))
1314 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1317 flush_vsx_to_thread(target
);
1318 return target
->thread
.used_vsr
? regset
->n
: 0;
1322 * tm_cvsx_get - get CVSX registers
1323 * @target: The target task.
1324 * @regset: The user regset structure.
1325 * @pos: The buffer position.
1326 * @count: Number of bytes to copy.
1327 * @kbuf: Kernel buffer to copy from.
1328 * @ubuf: User buffer to copy into.
1330 * This function gets in transaction checkpointed VSX registers.
1332 * When the transaction is active 'fp_state' holds the checkpointed
1333 * values for the current transaction to fall back on if it aborts
1334 * in between. This function gets those checkpointed VSX registers.
1335 * The userspace interface buffer layout is as follows.
1341 static int tm_cvsx_get(struct task_struct
*target
,
1342 const struct user_regset
*regset
,
1343 unsigned int pos
, unsigned int count
,
1344 void *kbuf
, void __user
*ubuf
)
1349 if (!cpu_has_feature(CPU_FTR_TM
))
1352 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1355 /* Flush the state */
1356 flush_fp_to_thread(target
);
1357 flush_altivec_to_thread(target
);
1358 flush_tmregs_to_thread(target
);
1359 flush_vsx_to_thread(target
);
1361 for (i
= 0; i
< 32 ; i
++)
1362 buf
[i
] = target
->thread
.fp_state
.fpr
[i
][TS_VSRLOWOFFSET
];
1363 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1364 buf
, 0, 32 * sizeof(double));
1370 * tm_cvsx_set - set CFPR registers
1371 * @target: The target task.
1372 * @regset: The user regset structure.
1373 * @pos: The buffer position.
1374 * @count: Number of bytes to copy.
1375 * @kbuf: Kernel buffer to copy into.
1376 * @ubuf: User buffer to copy from.
1378 * This function sets in transaction checkpointed VSX registers.
1380 * When the transaction is active 'fp_state' holds the checkpointed
1381 * VSX register values for the current transaction to fall back on
1382 * if it aborts in between. This function sets these checkpointed
1383 * FPR registers. The userspace interface buffer layout is as follows.
1389 static int tm_cvsx_set(struct task_struct
*target
,
1390 const struct user_regset
*regset
,
1391 unsigned int pos
, unsigned int count
,
1392 const void *kbuf
, const void __user
*ubuf
)
1397 if (!cpu_has_feature(CPU_FTR_TM
))
1400 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1403 /* Flush the state */
1404 flush_fp_to_thread(target
);
1405 flush_altivec_to_thread(target
);
1406 flush_tmregs_to_thread(target
);
1407 flush_vsx_to_thread(target
);
1409 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1410 buf
, 0, 32 * sizeof(double));
1411 for (i
= 0; i
< 32 ; i
++)
1412 target
->thread
.fp_state
.fpr
[i
][TS_VSRLOWOFFSET
] = buf
[i
];
1418 * tm_spr_active - get active number of registers in TM SPR
1419 * @target: The target task.
1420 * @regset: The user regset structure.
1422 * This function checks the active number of available
1423 * regisers in the transactional memory SPR category.
1425 static int tm_spr_active(struct task_struct
*target
,
1426 const struct user_regset
*regset
)
1428 if (!cpu_has_feature(CPU_FTR_TM
))
1435 * tm_spr_get - get the TM related SPR registers
1436 * @target: The target task.
1437 * @regset: The user regset structure.
1438 * @pos: The buffer position.
1439 * @count: Number of bytes to copy.
1440 * @kbuf: Kernel buffer to copy from.
1441 * @ubuf: User buffer to copy into.
1443 * This function gets transactional memory related SPR registers.
1444 * The userspace interface buffer layout is as follows.
1452 static int tm_spr_get(struct task_struct
*target
,
1453 const struct user_regset
*regset
,
1454 unsigned int pos
, unsigned int count
,
1455 void *kbuf
, void __user
*ubuf
)
1460 BUILD_BUG_ON(TSO(tm_tfhar
) + sizeof(u64
) != TSO(tm_texasr
));
1461 BUILD_BUG_ON(TSO(tm_texasr
) + sizeof(u64
) != TSO(tm_tfiar
));
1462 BUILD_BUG_ON(TSO(tm_tfiar
) + sizeof(u64
) != TSO(ckpt_regs
));
1464 if (!cpu_has_feature(CPU_FTR_TM
))
1467 /* Flush the states */
1468 flush_fp_to_thread(target
);
1469 flush_altivec_to_thread(target
);
1470 flush_tmregs_to_thread(target
);
1472 /* TFHAR register */
1473 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1474 &target
->thread
.tm_tfhar
, 0, sizeof(u64
));
1476 /* TEXASR register */
1478 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1479 &target
->thread
.tm_texasr
, sizeof(u64
),
1482 /* TFIAR register */
1484 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1485 &target
->thread
.tm_tfiar
,
1486 2 * sizeof(u64
), 3 * sizeof(u64
));
1491 * tm_spr_set - set the TM related SPR registers
1492 * @target: The target task.
1493 * @regset: The user regset structure.
1494 * @pos: The buffer position.
1495 * @count: Number of bytes to copy.
1496 * @kbuf: Kernel buffer to copy into.
1497 * @ubuf: User buffer to copy from.
1499 * This function sets transactional memory related SPR registers.
1500 * The userspace interface buffer layout is as follows.
1508 static int tm_spr_set(struct task_struct
*target
,
1509 const struct user_regset
*regset
,
1510 unsigned int pos
, unsigned int count
,
1511 const void *kbuf
, const void __user
*ubuf
)
1516 BUILD_BUG_ON(TSO(tm_tfhar
) + sizeof(u64
) != TSO(tm_texasr
));
1517 BUILD_BUG_ON(TSO(tm_texasr
) + sizeof(u64
) != TSO(tm_tfiar
));
1518 BUILD_BUG_ON(TSO(tm_tfiar
) + sizeof(u64
) != TSO(ckpt_regs
));
1520 if (!cpu_has_feature(CPU_FTR_TM
))
1523 /* Flush the states */
1524 flush_fp_to_thread(target
);
1525 flush_altivec_to_thread(target
);
1526 flush_tmregs_to_thread(target
);
1528 /* TFHAR register */
1529 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1530 &target
->thread
.tm_tfhar
, 0, sizeof(u64
));
1532 /* TEXASR register */
1534 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1535 &target
->thread
.tm_texasr
, sizeof(u64
),
1538 /* TFIAR register */
1540 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1541 &target
->thread
.tm_tfiar
,
1542 2 * sizeof(u64
), 3 * sizeof(u64
));
1546 static int tm_tar_active(struct task_struct
*target
,
1547 const struct user_regset
*regset
)
1549 if (!cpu_has_feature(CPU_FTR_TM
))
1552 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1558 static int tm_tar_get(struct task_struct
*target
,
1559 const struct user_regset
*regset
,
1560 unsigned int pos
, unsigned int count
,
1561 void *kbuf
, void __user
*ubuf
)
1565 if (!cpu_has_feature(CPU_FTR_TM
))
1568 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1571 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1572 &target
->thread
.tm_tar
, 0, sizeof(u64
));
1576 static int tm_tar_set(struct task_struct
*target
,
1577 const struct user_regset
*regset
,
1578 unsigned int pos
, unsigned int count
,
1579 const void *kbuf
, const void __user
*ubuf
)
1583 if (!cpu_has_feature(CPU_FTR_TM
))
1586 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1589 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1590 &target
->thread
.tm_tar
, 0, sizeof(u64
));
1594 static int tm_ppr_active(struct task_struct
*target
,
1595 const struct user_regset
*regset
)
1597 if (!cpu_has_feature(CPU_FTR_TM
))
1600 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1607 static int tm_ppr_get(struct task_struct
*target
,
1608 const struct user_regset
*regset
,
1609 unsigned int pos
, unsigned int count
,
1610 void *kbuf
, void __user
*ubuf
)
1614 if (!cpu_has_feature(CPU_FTR_TM
))
1617 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1620 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1621 &target
->thread
.tm_ppr
, 0, sizeof(u64
));
1625 static int tm_ppr_set(struct task_struct
*target
,
1626 const struct user_regset
*regset
,
1627 unsigned int pos
, unsigned int count
,
1628 const void *kbuf
, const void __user
*ubuf
)
1632 if (!cpu_has_feature(CPU_FTR_TM
))
1635 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1638 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1639 &target
->thread
.tm_ppr
, 0, sizeof(u64
));
1643 static int tm_dscr_active(struct task_struct
*target
,
1644 const struct user_regset
*regset
)
1646 if (!cpu_has_feature(CPU_FTR_TM
))
1649 if (MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1655 static int tm_dscr_get(struct task_struct
*target
,
1656 const struct user_regset
*regset
,
1657 unsigned int pos
, unsigned int count
,
1658 void *kbuf
, void __user
*ubuf
)
1662 if (!cpu_has_feature(CPU_FTR_TM
))
1665 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1668 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1669 &target
->thread
.tm_dscr
, 0, sizeof(u64
));
1673 static int tm_dscr_set(struct task_struct
*target
,
1674 const struct user_regset
*regset
,
1675 unsigned int pos
, unsigned int count
,
1676 const void *kbuf
, const void __user
*ubuf
)
1680 if (!cpu_has_feature(CPU_FTR_TM
))
1683 if (!MSR_TM_ACTIVE(target
->thread
.regs
->msr
))
1686 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1687 &target
->thread
.tm_dscr
, 0, sizeof(u64
));
1690 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1693 static int ppr_get(struct task_struct
*target
,
1694 const struct user_regset
*regset
,
1695 unsigned int pos
, unsigned int count
,
1696 void *kbuf
, void __user
*ubuf
)
1700 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1701 &target
->thread
.ppr
, 0, sizeof(u64
));
1705 static int ppr_set(struct task_struct
*target
,
1706 const struct user_regset
*regset
,
1707 unsigned int pos
, unsigned int count
,
1708 const void *kbuf
, const void __user
*ubuf
)
1712 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1713 &target
->thread
.ppr
, 0, sizeof(u64
));
1717 static int dscr_get(struct task_struct
*target
,
1718 const struct user_regset
*regset
,
1719 unsigned int pos
, unsigned int count
,
1720 void *kbuf
, void __user
*ubuf
)
1724 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1725 &target
->thread
.dscr
, 0, sizeof(u64
));
1728 static int dscr_set(struct task_struct
*target
,
1729 const struct user_regset
*regset
,
1730 unsigned int pos
, unsigned int count
,
1731 const void *kbuf
, const void __user
*ubuf
)
1735 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1736 &target
->thread
.dscr
, 0, sizeof(u64
));
1740 #ifdef CONFIG_PPC_BOOK3S_64
1741 static int tar_get(struct task_struct
*target
,
1742 const struct user_regset
*regset
,
1743 unsigned int pos
, unsigned int count
,
1744 void *kbuf
, void __user
*ubuf
)
1748 ret
= user_regset_copyout(&pos
, &count
, &kbuf
, &ubuf
,
1749 &target
->thread
.tar
, 0, sizeof(u64
));
1752 static int tar_set(struct task_struct
*target
,
1753 const struct user_regset
*regset
,
1754 unsigned int pos
, unsigned int count
,
1755 const void *kbuf
, const void __user
*ubuf
)
1759 ret
= user_regset_copyin(&pos
, &count
, &kbuf
, &ubuf
,
1760 &target
->thread
.tar
, 0, sizeof(u64
));
1765 * These are our native regset flavors.
1767 enum powerpc_regset
{
1770 #ifdef CONFIG_ALTIVEC
1779 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1780 REGSET_TM_CGPR
, /* TM checkpointed GPR registers */
1781 REGSET_TM_CFPR
, /* TM checkpointed FPR registers */
1782 REGSET_TM_CVMX
, /* TM checkpointed VMX registers */
1783 REGSET_TM_CVSX
, /* TM checkpointed VSX registers */
1784 REGSET_TM_SPR
, /* TM specific SPR registers */
1785 REGSET_TM_CTAR
, /* TM checkpointed TAR register */
1786 REGSET_TM_CPPR
, /* TM checkpointed PPR register */
1787 REGSET_TM_CDSCR
, /* TM checkpointed DSCR register */
1790 REGSET_PPR
, /* PPR register */
1791 REGSET_DSCR
, /* DSCR register */
1793 #ifdef CONFIG_PPC_BOOK3S_64
1794 REGSET_TAR
, /* TAR register */
1798 static const struct user_regset native_regsets
[] = {
1800 .core_note_type
= NT_PRSTATUS
, .n
= ELF_NGREG
,
1801 .size
= sizeof(long), .align
= sizeof(long),
1802 .get
= gpr_get
, .set
= gpr_set
1805 .core_note_type
= NT_PRFPREG
, .n
= ELF_NFPREG
,
1806 .size
= sizeof(double), .align
= sizeof(double),
1807 .get
= fpr_get
, .set
= fpr_set
1809 #ifdef CONFIG_ALTIVEC
1811 .core_note_type
= NT_PPC_VMX
, .n
= 34,
1812 .size
= sizeof(vector128
), .align
= sizeof(vector128
),
1813 .active
= vr_active
, .get
= vr_get
, .set
= vr_set
1818 .core_note_type
= NT_PPC_VSX
, .n
= 32,
1819 .size
= sizeof(double), .align
= sizeof(double),
1820 .active
= vsr_active
, .get
= vsr_get
, .set
= vsr_set
1825 .core_note_type
= NT_PPC_SPE
, .n
= 35,
1826 .size
= sizeof(u32
), .align
= sizeof(u32
),
1827 .active
= evr_active
, .get
= evr_get
, .set
= evr_set
1830 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1831 [REGSET_TM_CGPR
] = {
1832 .core_note_type
= NT_PPC_TM_CGPR
, .n
= ELF_NGREG
,
1833 .size
= sizeof(long), .align
= sizeof(long),
1834 .active
= tm_cgpr_active
, .get
= tm_cgpr_get
, .set
= tm_cgpr_set
1836 [REGSET_TM_CFPR
] = {
1837 .core_note_type
= NT_PPC_TM_CFPR
, .n
= ELF_NFPREG
,
1838 .size
= sizeof(double), .align
= sizeof(double),
1839 .active
= tm_cfpr_active
, .get
= tm_cfpr_get
, .set
= tm_cfpr_set
1841 [REGSET_TM_CVMX
] = {
1842 .core_note_type
= NT_PPC_TM_CVMX
, .n
= ELF_NVMX
,
1843 .size
= sizeof(vector128
), .align
= sizeof(vector128
),
1844 .active
= tm_cvmx_active
, .get
= tm_cvmx_get
, .set
= tm_cvmx_set
1846 [REGSET_TM_CVSX
] = {
1847 .core_note_type
= NT_PPC_TM_CVSX
, .n
= ELF_NVSX
,
1848 .size
= sizeof(double), .align
= sizeof(double),
1849 .active
= tm_cvsx_active
, .get
= tm_cvsx_get
, .set
= tm_cvsx_set
1852 .core_note_type
= NT_PPC_TM_SPR
, .n
= ELF_NTMSPRREG
,
1853 .size
= sizeof(u64
), .align
= sizeof(u64
),
1854 .active
= tm_spr_active
, .get
= tm_spr_get
, .set
= tm_spr_set
1856 [REGSET_TM_CTAR
] = {
1857 .core_note_type
= NT_PPC_TM_CTAR
, .n
= 1,
1858 .size
= sizeof(u64
), .align
= sizeof(u64
),
1859 .active
= tm_tar_active
, .get
= tm_tar_get
, .set
= tm_tar_set
1861 [REGSET_TM_CPPR
] = {
1862 .core_note_type
= NT_PPC_TM_CPPR
, .n
= 1,
1863 .size
= sizeof(u64
), .align
= sizeof(u64
),
1864 .active
= tm_ppr_active
, .get
= tm_ppr_get
, .set
= tm_ppr_set
1866 [REGSET_TM_CDSCR
] = {
1867 .core_note_type
= NT_PPC_TM_CDSCR
, .n
= 1,
1868 .size
= sizeof(u64
), .align
= sizeof(u64
),
1869 .active
= tm_dscr_active
, .get
= tm_dscr_get
, .set
= tm_dscr_set
1874 .core_note_type
= NT_PPC_PPR
, .n
= 1,
1875 .size
= sizeof(u64
), .align
= sizeof(u64
),
1876 .get
= ppr_get
, .set
= ppr_set
1879 .core_note_type
= NT_PPC_DSCR
, .n
= 1,
1880 .size
= sizeof(u64
), .align
= sizeof(u64
),
1881 .get
= dscr_get
, .set
= dscr_set
1884 #ifdef CONFIG_PPC_BOOK3S_64
1886 .core_note_type
= NT_PPC_TAR
, .n
= 1,
1887 .size
= sizeof(u64
), .align
= sizeof(u64
),
1888 .get
= tar_get
, .set
= tar_set
1893 static const struct user_regset_view user_ppc_native_view
= {
1894 .name
= UTS_MACHINE
, .e_machine
= ELF_ARCH
, .ei_osabi
= ELF_OSABI
,
1895 .regsets
= native_regsets
, .n
= ARRAY_SIZE(native_regsets
)
1899 #include <linux/compat.h>
1901 static int gpr32_get_common(struct task_struct
*target
,
1902 const struct user_regset
*regset
,
1903 unsigned int pos
, unsigned int count
,
1904 void *kbuf
, void __user
*ubuf
, bool tm_active
)
1906 const unsigned long *regs
= &target
->thread
.regs
->gpr
[0];
1907 const unsigned long *ckpt_regs
;
1908 compat_ulong_t
*k
= kbuf
;
1909 compat_ulong_t __user
*u
= ubuf
;
1913 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1914 ckpt_regs
= &target
->thread
.ckpt_regs
.gpr
[0];
1919 if (target
->thread
.regs
== NULL
)
1922 if (!FULL_REGS(target
->thread
.regs
)) {
1924 * We have a partial register set.
1925 * Fill 14-31 with bogus values.
1927 for (i
= 14; i
< 32; i
++)
1928 target
->thread
.regs
->gpr
[i
] = NV_REG_POISON
;
1933 count
/= sizeof(reg
);
1936 for (; count
> 0 && pos
< PT_MSR
; --count
)
1939 for (; count
> 0 && pos
< PT_MSR
; --count
)
1940 if (__put_user((compat_ulong_t
) regs
[pos
++], u
++))
1943 if (count
> 0 && pos
== PT_MSR
) {
1944 reg
= get_user_msr(target
);
1947 else if (__put_user(reg
, u
++))
1954 for (; count
> 0 && pos
< PT_REGS_COUNT
; --count
)
1957 for (; count
> 0 && pos
< PT_REGS_COUNT
; --count
)
1958 if (__put_user((compat_ulong_t
) regs
[pos
++], u
++))
1964 count
*= sizeof(reg
);
1965 return user_regset_copyout_zero(&pos
, &count
, &kbuf
, &ubuf
,
1966 PT_REGS_COUNT
* sizeof(reg
), -1);
1969 static int gpr32_set_common(struct task_struct
*target
,
1970 const struct user_regset
*regset
,
1971 unsigned int pos
, unsigned int count
,
1972 const void *kbuf
, const void __user
*ubuf
, bool tm_active
)
1974 unsigned long *regs
= &target
->thread
.regs
->gpr
[0];
1975 unsigned long *ckpt_regs
;
1976 const compat_ulong_t
*k
= kbuf
;
1977 const compat_ulong_t __user
*u
= ubuf
;
1980 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1981 ckpt_regs
= &target
->thread
.ckpt_regs
.gpr
[0];
1987 regs
= &target
->thread
.regs
->gpr
[0];
1989 if (target
->thread
.regs
== NULL
)
1992 CHECK_FULL_REGS(target
->thread
.regs
);
1996 count
/= sizeof(reg
);
1999 for (; count
> 0 && pos
< PT_MSR
; --count
)
2002 for (; count
> 0 && pos
< PT_MSR
; --count
) {
2003 if (__get_user(reg
, u
++))
2009 if (count
> 0 && pos
== PT_MSR
) {
2012 else if (__get_user(reg
, u
++))
2014 set_user_msr(target
, reg
);
2020 for (; count
> 0 && pos
<= PT_MAX_PUT_REG
; --count
)
2022 for (; count
> 0 && pos
< PT_TRAP
; --count
, ++pos
)
2025 for (; count
> 0 && pos
<= PT_MAX_PUT_REG
; --count
) {
2026 if (__get_user(reg
, u
++))
2030 for (; count
> 0 && pos
< PT_TRAP
; --count
, ++pos
)
2031 if (__get_user(reg
, u
++))
2035 if (count
> 0 && pos
== PT_TRAP
) {
2038 else if (__get_user(reg
, u
++))
2040 set_user_trap(target
, reg
);
2048 count
*= sizeof(reg
);
2049 return user_regset_copyin_ignore(&pos
, &count
, &kbuf
, &ubuf
,
2050 (PT_TRAP
+ 1) * sizeof(reg
), -1);
2053 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2054 static int tm_cgpr32_get(struct task_struct
*target
,
2055 const struct user_regset
*regset
,
2056 unsigned int pos
, unsigned int count
,
2057 void *kbuf
, void __user
*ubuf
)
2059 return gpr32_get_common(target
, regset
, pos
, count
, kbuf
, ubuf
, 1);
2062 static int tm_cgpr32_set(struct task_struct
*target
,
2063 const struct user_regset
*regset
,
2064 unsigned int pos
, unsigned int count
,
2065 const void *kbuf
, const void __user
*ubuf
)
2067 return gpr32_set_common(target
, regset
, pos
, count
, kbuf
, ubuf
, 1);
2069 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2071 static int gpr32_get(struct task_struct
*target
,
2072 const struct user_regset
*regset
,
2073 unsigned int pos
, unsigned int count
,
2074 void *kbuf
, void __user
*ubuf
)
2076 return gpr32_get_common(target
, regset
, pos
, count
, kbuf
, ubuf
, 0);
2079 static int gpr32_set(struct task_struct
*target
,
2080 const struct user_regset
*regset
,
2081 unsigned int pos
, unsigned int count
,
2082 const void *kbuf
, const void __user
*ubuf
)
2084 return gpr32_set_common(target
, regset
, pos
, count
, kbuf
, ubuf
, 0);
2088 * These are the regset flavors matching the CONFIG_PPC32 native set.
2090 static const struct user_regset compat_regsets
[] = {
2092 .core_note_type
= NT_PRSTATUS
, .n
= ELF_NGREG
,
2093 .size
= sizeof(compat_long_t
), .align
= sizeof(compat_long_t
),
2094 .get
= gpr32_get
, .set
= gpr32_set
2097 .core_note_type
= NT_PRFPREG
, .n
= ELF_NFPREG
,
2098 .size
= sizeof(double), .align
= sizeof(double),
2099 .get
= fpr_get
, .set
= fpr_set
2101 #ifdef CONFIG_ALTIVEC
2103 .core_note_type
= NT_PPC_VMX
, .n
= 34,
2104 .size
= sizeof(vector128
), .align
= sizeof(vector128
),
2105 .active
= vr_active
, .get
= vr_get
, .set
= vr_set
2110 .core_note_type
= NT_PPC_SPE
, .n
= 35,
2111 .size
= sizeof(u32
), .align
= sizeof(u32
),
2112 .active
= evr_active
, .get
= evr_get
, .set
= evr_set
2115 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2116 [REGSET_TM_CGPR
] = {
2117 .core_note_type
= NT_PPC_TM_CGPR
, .n
= ELF_NGREG
,
2118 .size
= sizeof(long), .align
= sizeof(long),
2119 .active
= tm_cgpr_active
,
2120 .get
= tm_cgpr32_get
, .set
= tm_cgpr32_set
2122 [REGSET_TM_CFPR
] = {
2123 .core_note_type
= NT_PPC_TM_CFPR
, .n
= ELF_NFPREG
,
2124 .size
= sizeof(double), .align
= sizeof(double),
2125 .active
= tm_cfpr_active
, .get
= tm_cfpr_get
, .set
= tm_cfpr_set
2127 [REGSET_TM_CVMX
] = {
2128 .core_note_type
= NT_PPC_TM_CVMX
, .n
= ELF_NVMX
,
2129 .size
= sizeof(vector128
), .align
= sizeof(vector128
),
2130 .active
= tm_cvmx_active
, .get
= tm_cvmx_get
, .set
= tm_cvmx_set
2132 [REGSET_TM_CVSX
] = {
2133 .core_note_type
= NT_PPC_TM_CVSX
, .n
= ELF_NVSX
,
2134 .size
= sizeof(double), .align
= sizeof(double),
2135 .active
= tm_cvsx_active
, .get
= tm_cvsx_get
, .set
= tm_cvsx_set
2138 .core_note_type
= NT_PPC_TM_SPR
, .n
= ELF_NTMSPRREG
,
2139 .size
= sizeof(u64
), .align
= sizeof(u64
),
2140 .active
= tm_spr_active
, .get
= tm_spr_get
, .set
= tm_spr_set
2142 [REGSET_TM_CTAR
] = {
2143 .core_note_type
= NT_PPC_TM_CTAR
, .n
= 1,
2144 .size
= sizeof(u64
), .align
= sizeof(u64
),
2145 .active
= tm_tar_active
, .get
= tm_tar_get
, .set
= tm_tar_set
2147 [REGSET_TM_CPPR
] = {
2148 .core_note_type
= NT_PPC_TM_CPPR
, .n
= 1,
2149 .size
= sizeof(u64
), .align
= sizeof(u64
),
2150 .active
= tm_ppr_active
, .get
= tm_ppr_get
, .set
= tm_ppr_set
2152 [REGSET_TM_CDSCR
] = {
2153 .core_note_type
= NT_PPC_TM_CDSCR
, .n
= 1,
2154 .size
= sizeof(u64
), .align
= sizeof(u64
),
2155 .active
= tm_dscr_active
, .get
= tm_dscr_get
, .set
= tm_dscr_set
2160 .core_note_type
= NT_PPC_PPR
, .n
= 1,
2161 .size
= sizeof(u64
), .align
= sizeof(u64
),
2162 .get
= ppr_get
, .set
= ppr_set
2165 .core_note_type
= NT_PPC_DSCR
, .n
= 1,
2166 .size
= sizeof(u64
), .align
= sizeof(u64
),
2167 .get
= dscr_get
, .set
= dscr_set
2170 #ifdef CONFIG_PPC_BOOK3S_64
2172 .core_note_type
= NT_PPC_TAR
, .n
= 1,
2173 .size
= sizeof(u64
), .align
= sizeof(u64
),
2174 .get
= tar_get
, .set
= tar_set
2179 static const struct user_regset_view user_ppc_compat_view
= {
2180 .name
= "ppc", .e_machine
= EM_PPC
, .ei_osabi
= ELF_OSABI
,
2181 .regsets
= compat_regsets
, .n
= ARRAY_SIZE(compat_regsets
)
2183 #endif /* CONFIG_PPC64 */
2185 const struct user_regset_view
*task_user_regset_view(struct task_struct
*task
)
2188 if (test_tsk_thread_flag(task
, TIF_32BIT
))
2189 return &user_ppc_compat_view
;
2191 return &user_ppc_native_view
;
2195 void user_enable_single_step(struct task_struct
*task
)
2197 struct pt_regs
*regs
= task
->thread
.regs
;
2200 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2201 task
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
2202 task
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
2203 regs
->msr
|= MSR_DE
;
2205 regs
->msr
&= ~MSR_BE
;
2206 regs
->msr
|= MSR_SE
;
2209 set_tsk_thread_flag(task
, TIF_SINGLESTEP
);
2212 void user_enable_block_step(struct task_struct
*task
)
2214 struct pt_regs
*regs
= task
->thread
.regs
;
2217 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2218 task
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
2219 task
->thread
.debug
.dbcr0
= DBCR0_IDM
| DBCR0_BT
;
2220 regs
->msr
|= MSR_DE
;
2222 regs
->msr
&= ~MSR_SE
;
2223 regs
->msr
|= MSR_BE
;
2226 set_tsk_thread_flag(task
, TIF_SINGLESTEP
);
2229 void user_disable_single_step(struct task_struct
*task
)
2231 struct pt_regs
*regs
= task
->thread
.regs
;
2234 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2236 * The logic to disable single stepping should be as
2237 * simple as turning off the Instruction Complete flag.
2238 * And, after doing so, if all debug flags are off, turn
2239 * off DBCR0(IDM) and MSR(DE) .... Torez
2241 task
->thread
.debug
.dbcr0
&= ~(DBCR0_IC
|DBCR0_BT
);
2243 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
2245 if (!DBCR_ACTIVE_EVENTS(task
->thread
.debug
.dbcr0
,
2246 task
->thread
.debug
.dbcr1
)) {
2248 * All debug events were off.....
2250 task
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
2251 regs
->msr
&= ~MSR_DE
;
2254 regs
->msr
&= ~(MSR_SE
| MSR_BE
);
2257 clear_tsk_thread_flag(task
, TIF_SINGLESTEP
);
2260 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2261 void ptrace_triggered(struct perf_event
*bp
,
2262 struct perf_sample_data
*data
, struct pt_regs
*regs
)
2264 struct perf_event_attr attr
;
2267 * Disable the breakpoint request here since ptrace has defined a
2268 * one-shot behaviour for breakpoint exceptions in PPC64.
2269 * The SIGTRAP signal is generated automatically for us in do_dabr().
2270 * We don't have to do anything about that here
2273 attr
.disabled
= true;
2274 modify_user_hw_breakpoint(bp
, &attr
);
2276 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2278 static int ptrace_set_debugreg(struct task_struct
*task
, unsigned long addr
,
2281 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2283 struct thread_struct
*thread
= &(task
->thread
);
2284 struct perf_event
*bp
;
2285 struct perf_event_attr attr
;
2286 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2287 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2288 struct arch_hw_breakpoint hw_brk
;
2291 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
2292 * For embedded processors we support one DAC and no IAC's at the
2298 /* The bottom 3 bits in dabr are flags */
2299 if ((data
& ~0x7UL
) >= TASK_SIZE
)
2302 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2303 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
2304 * It was assumed, on previous implementations, that 3 bits were
2305 * passed together with the data address, fitting the design of the
2306 * DABR register, as follows:
2310 * bit 2: Breakpoint translation
2312 * Thus, we use them here as so.
2315 /* Ensure breakpoint translation bit is set */
2316 if (data
&& !(data
& HW_BRK_TYPE_TRANSLATE
))
2318 hw_brk
.address
= data
& (~HW_BRK_TYPE_DABR
);
2319 hw_brk
.type
= (data
& HW_BRK_TYPE_DABR
) | HW_BRK_TYPE_PRIV_ALL
;
2321 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2322 bp
= thread
->ptrace_bps
[0];
2323 if ((!data
) || !(hw_brk
.type
& HW_BRK_TYPE_RDWR
)) {
2325 unregister_hw_breakpoint(bp
);
2326 thread
->ptrace_bps
[0] = NULL
;
2332 attr
.bp_addr
= hw_brk
.address
;
2333 arch_bp_generic_fields(hw_brk
.type
, &attr
.bp_type
);
2335 /* Enable breakpoint */
2336 attr
.disabled
= false;
2338 ret
= modify_user_hw_breakpoint(bp
, &attr
);
2342 thread
->ptrace_bps
[0] = bp
;
2343 thread
->hw_brk
= hw_brk
;
2347 /* Create a new breakpoint request if one doesn't exist already */
2348 hw_breakpoint_init(&attr
);
2349 attr
.bp_addr
= hw_brk
.address
;
2350 arch_bp_generic_fields(hw_brk
.type
,
2353 thread
->ptrace_bps
[0] = bp
= register_user_hw_breakpoint(&attr
,
2354 ptrace_triggered
, NULL
, task
);
2356 thread
->ptrace_bps
[0] = NULL
;
2360 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2361 task
->thread
.hw_brk
= hw_brk
;
2362 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
2363 /* As described above, it was assumed 3 bits were passed with the data
2364 * address, but we will assume only the mode bits will be passed
2365 * as to not cause alignment restrictions for DAC-based processors.
2368 /* DAC's hold the whole address without any mode flags */
2369 task
->thread
.debug
.dac1
= data
& ~0x3UL
;
2371 if (task
->thread
.debug
.dac1
== 0) {
2372 dbcr_dac(task
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
2373 if (!DBCR_ACTIVE_EVENTS(task
->thread
.debug
.dbcr0
,
2374 task
->thread
.debug
.dbcr1
)) {
2375 task
->thread
.regs
->msr
&= ~MSR_DE
;
2376 task
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
2381 /* Read or Write bits must be set */
2383 if (!(data
& 0x3UL
))
2386 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
2388 task
->thread
.debug
.dbcr0
|= DBCR0_IDM
;
2390 /* Check for write and read flags and set DBCR0
2392 dbcr_dac(task
) &= ~(DBCR_DAC1R
|DBCR_DAC1W
);
2394 dbcr_dac(task
) |= DBCR_DAC1R
;
2396 dbcr_dac(task
) |= DBCR_DAC1W
;
2397 task
->thread
.regs
->msr
|= MSR_DE
;
2398 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2403 * Called by kernel/ptrace.c when detaching..
2405 * Make sure single step bits etc are not set.
2407 void ptrace_disable(struct task_struct
*child
)
2409 /* make sure the single step bit is not set. */
2410 user_disable_single_step(child
);
2413 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2414 static long set_instruction_bp(struct task_struct
*child
,
2415 struct ppc_hw_breakpoint
*bp_info
)
2418 int slot1_in_use
= ((child
->thread
.debug
.dbcr0
& DBCR0_IAC1
) != 0);
2419 int slot2_in_use
= ((child
->thread
.debug
.dbcr0
& DBCR0_IAC2
) != 0);
2420 int slot3_in_use
= ((child
->thread
.debug
.dbcr0
& DBCR0_IAC3
) != 0);
2421 int slot4_in_use
= ((child
->thread
.debug
.dbcr0
& DBCR0_IAC4
) != 0);
2423 if (dbcr_iac_range(child
) & DBCR_IAC12MODE
)
2425 if (dbcr_iac_range(child
) & DBCR_IAC34MODE
)
2428 if (bp_info
->addr
>= TASK_SIZE
)
2431 if (bp_info
->addr_mode
!= PPC_BREAKPOINT_MODE_EXACT
) {
2433 /* Make sure range is valid. */
2434 if (bp_info
->addr2
>= TASK_SIZE
)
2437 /* We need a pair of IAC regsisters */
2438 if ((!slot1_in_use
) && (!slot2_in_use
)) {
2440 child
->thread
.debug
.iac1
= bp_info
->addr
;
2441 child
->thread
.debug
.iac2
= bp_info
->addr2
;
2442 child
->thread
.debug
.dbcr0
|= DBCR0_IAC1
;
2443 if (bp_info
->addr_mode
==
2444 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE
)
2445 dbcr_iac_range(child
) |= DBCR_IAC12X
;
2447 dbcr_iac_range(child
) |= DBCR_IAC12I
;
2448 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2449 } else if ((!slot3_in_use
) && (!slot4_in_use
)) {
2451 child
->thread
.debug
.iac3
= bp_info
->addr
;
2452 child
->thread
.debug
.iac4
= bp_info
->addr2
;
2453 child
->thread
.debug
.dbcr0
|= DBCR0_IAC3
;
2454 if (bp_info
->addr_mode
==
2455 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE
)
2456 dbcr_iac_range(child
) |= DBCR_IAC34X
;
2458 dbcr_iac_range(child
) |= DBCR_IAC34I
;
2463 /* We only need one. If possible leave a pair free in
2464 * case a range is needed later
2466 if (!slot1_in_use
) {
2468 * Don't use iac1 if iac1-iac2 are free and either
2469 * iac3 or iac4 (but not both) are free
2471 if (slot2_in_use
|| (slot3_in_use
== slot4_in_use
)) {
2473 child
->thread
.debug
.iac1
= bp_info
->addr
;
2474 child
->thread
.debug
.dbcr0
|= DBCR0_IAC1
;
2478 if (!slot2_in_use
) {
2480 child
->thread
.debug
.iac2
= bp_info
->addr
;
2481 child
->thread
.debug
.dbcr0
|= DBCR0_IAC2
;
2482 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2483 } else if (!slot3_in_use
) {
2485 child
->thread
.debug
.iac3
= bp_info
->addr
;
2486 child
->thread
.debug
.dbcr0
|= DBCR0_IAC3
;
2487 } else if (!slot4_in_use
) {
2489 child
->thread
.debug
.iac4
= bp_info
->addr
;
2490 child
->thread
.debug
.dbcr0
|= DBCR0_IAC4
;
2496 child
->thread
.debug
.dbcr0
|= DBCR0_IDM
;
2497 child
->thread
.regs
->msr
|= MSR_DE
;
2502 static int del_instruction_bp(struct task_struct
*child
, int slot
)
2506 if ((child
->thread
.debug
.dbcr0
& DBCR0_IAC1
) == 0)
2509 if (dbcr_iac_range(child
) & DBCR_IAC12MODE
) {
2510 /* address range - clear slots 1 & 2 */
2511 child
->thread
.debug
.iac2
= 0;
2512 dbcr_iac_range(child
) &= ~DBCR_IAC12MODE
;
2514 child
->thread
.debug
.iac1
= 0;
2515 child
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
2518 if ((child
->thread
.debug
.dbcr0
& DBCR0_IAC2
) == 0)
2521 if (dbcr_iac_range(child
) & DBCR_IAC12MODE
)
2522 /* used in a range */
2524 child
->thread
.debug
.iac2
= 0;
2525 child
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
2527 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2529 if ((child
->thread
.debug
.dbcr0
& DBCR0_IAC3
) == 0)
2532 if (dbcr_iac_range(child
) & DBCR_IAC34MODE
) {
2533 /* address range - clear slots 3 & 4 */
2534 child
->thread
.debug
.iac4
= 0;
2535 dbcr_iac_range(child
) &= ~DBCR_IAC34MODE
;
2537 child
->thread
.debug
.iac3
= 0;
2538 child
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
2541 if ((child
->thread
.debug
.dbcr0
& DBCR0_IAC4
) == 0)
2544 if (dbcr_iac_range(child
) & DBCR_IAC34MODE
)
2545 /* Used in a range */
2547 child
->thread
.debug
.iac4
= 0;
2548 child
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
2557 static int set_dac(struct task_struct
*child
, struct ppc_hw_breakpoint
*bp_info
)
2560 (bp_info
->condition_mode
>> PPC_BREAKPOINT_CONDITION_BE_SHIFT
)
2562 int condition_mode
=
2563 bp_info
->condition_mode
& PPC_BREAKPOINT_CONDITION_MODE
;
2566 if (byte_enable
&& (condition_mode
== 0))
2569 if (bp_info
->addr
>= TASK_SIZE
)
2572 if ((dbcr_dac(child
) & (DBCR_DAC1R
| DBCR_DAC1W
)) == 0) {
2574 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_READ
)
2575 dbcr_dac(child
) |= DBCR_DAC1R
;
2576 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_WRITE
)
2577 dbcr_dac(child
) |= DBCR_DAC1W
;
2578 child
->thread
.debug
.dac1
= (unsigned long)bp_info
->addr
;
2579 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2581 child
->thread
.debug
.dvc1
=
2582 (unsigned long)bp_info
->condition_value
;
2583 child
->thread
.debug
.dbcr2
|=
2584 ((byte_enable
<< DBCR2_DVC1BE_SHIFT
) |
2585 (condition_mode
<< DBCR2_DVC1M_SHIFT
));
2588 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2589 } else if (child
->thread
.debug
.dbcr2
& DBCR2_DAC12MODE
) {
2590 /* Both dac1 and dac2 are part of a range */
2593 } else if ((dbcr_dac(child
) & (DBCR_DAC2R
| DBCR_DAC2W
)) == 0) {
2595 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_READ
)
2596 dbcr_dac(child
) |= DBCR_DAC2R
;
2597 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_WRITE
)
2598 dbcr_dac(child
) |= DBCR_DAC2W
;
2599 child
->thread
.debug
.dac2
= (unsigned long)bp_info
->addr
;
2600 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2602 child
->thread
.debug
.dvc2
=
2603 (unsigned long)bp_info
->condition_value
;
2604 child
->thread
.debug
.dbcr2
|=
2605 ((byte_enable
<< DBCR2_DVC2BE_SHIFT
) |
2606 (condition_mode
<< DBCR2_DVC2M_SHIFT
));
2611 child
->thread
.debug
.dbcr0
|= DBCR0_IDM
;
2612 child
->thread
.regs
->msr
|= MSR_DE
;
2617 static int del_dac(struct task_struct
*child
, int slot
)
2620 if ((dbcr_dac(child
) & (DBCR_DAC1R
| DBCR_DAC1W
)) == 0)
2623 child
->thread
.debug
.dac1
= 0;
2624 dbcr_dac(child
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
2625 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2626 if (child
->thread
.debug
.dbcr2
& DBCR2_DAC12MODE
) {
2627 child
->thread
.debug
.dac2
= 0;
2628 child
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
2630 child
->thread
.debug
.dbcr2
&= ~(DBCR2_DVC1M
| DBCR2_DVC1BE
);
2632 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2633 child
->thread
.debug
.dvc1
= 0;
2635 } else if (slot
== 2) {
2636 if ((dbcr_dac(child
) & (DBCR_DAC2R
| DBCR_DAC2W
)) == 0)
2639 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2640 if (child
->thread
.debug
.dbcr2
& DBCR2_DAC12MODE
)
2641 /* Part of a range */
2643 child
->thread
.debug
.dbcr2
&= ~(DBCR2_DVC2M
| DBCR2_DVC2BE
);
2645 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2646 child
->thread
.debug
.dvc2
= 0;
2648 child
->thread
.debug
.dac2
= 0;
2649 dbcr_dac(child
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
2655 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2657 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2658 static int set_dac_range(struct task_struct
*child
,
2659 struct ppc_hw_breakpoint
*bp_info
)
2661 int mode
= bp_info
->addr_mode
& PPC_BREAKPOINT_MODE_MASK
;
2663 /* We don't allow range watchpoints to be used with DVC */
2664 if (bp_info
->condition_mode
)
2668 * Best effort to verify the address range. The user/supervisor bits
2669 * prevent trapping in kernel space, but let's fail on an obvious bad
2670 * range. The simple test on the mask is not fool-proof, and any
2671 * exclusive range will spill over into kernel space.
2673 if (bp_info
->addr
>= TASK_SIZE
)
2675 if (mode
== PPC_BREAKPOINT_MODE_MASK
) {
2677 * dac2 is a bitmask. Don't allow a mask that makes a
2678 * kernel space address from a valid dac1 value
2680 if (~((unsigned long)bp_info
->addr2
) >= TASK_SIZE
)
2684 * For range breakpoints, addr2 must also be a valid address
2686 if (bp_info
->addr2
>= TASK_SIZE
)
2690 if (child
->thread
.debug
.dbcr0
&
2691 (DBCR0_DAC1R
| DBCR0_DAC1W
| DBCR0_DAC2R
| DBCR0_DAC2W
))
2694 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_READ
)
2695 child
->thread
.debug
.dbcr0
|= (DBCR0_DAC1R
| DBCR0_IDM
);
2696 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_WRITE
)
2697 child
->thread
.debug
.dbcr0
|= (DBCR0_DAC1W
| DBCR0_IDM
);
2698 child
->thread
.debug
.dac1
= bp_info
->addr
;
2699 child
->thread
.debug
.dac2
= bp_info
->addr2
;
2700 if (mode
== PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
)
2701 child
->thread
.debug
.dbcr2
|= DBCR2_DAC12M
;
2702 else if (mode
== PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE
)
2703 child
->thread
.debug
.dbcr2
|= DBCR2_DAC12MX
;
2704 else /* PPC_BREAKPOINT_MODE_MASK */
2705 child
->thread
.debug
.dbcr2
|= DBCR2_DAC12MM
;
2706 child
->thread
.regs
->msr
|= MSR_DE
;
2710 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
2712 static long ppc_set_hwdebug(struct task_struct
*child
,
2713 struct ppc_hw_breakpoint
*bp_info
)
2715 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2717 struct thread_struct
*thread
= &(child
->thread
);
2718 struct perf_event
*bp
;
2719 struct perf_event_attr attr
;
2720 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2721 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2722 struct arch_hw_breakpoint brk
;
2725 if (bp_info
->version
!= 1)
2727 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2729 * Check for invalid flags and combinations
2731 if ((bp_info
->trigger_type
== 0) ||
2732 (bp_info
->trigger_type
& ~(PPC_BREAKPOINT_TRIGGER_EXECUTE
|
2733 PPC_BREAKPOINT_TRIGGER_RW
)) ||
2734 (bp_info
->addr_mode
& ~PPC_BREAKPOINT_MODE_MASK
) ||
2735 (bp_info
->condition_mode
&
2736 ~(PPC_BREAKPOINT_CONDITION_MODE
|
2737 PPC_BREAKPOINT_CONDITION_BE_ALL
)))
2739 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
2740 if (bp_info
->condition_mode
!= PPC_BREAKPOINT_CONDITION_NONE
)
2744 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_EXECUTE
) {
2745 if ((bp_info
->trigger_type
!= PPC_BREAKPOINT_TRIGGER_EXECUTE
) ||
2746 (bp_info
->condition_mode
!= PPC_BREAKPOINT_CONDITION_NONE
))
2748 return set_instruction_bp(child
, bp_info
);
2750 if (bp_info
->addr_mode
== PPC_BREAKPOINT_MODE_EXACT
)
2751 return set_dac(child
, bp_info
);
2753 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2754 return set_dac_range(child
, bp_info
);
2758 #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2760 * We only support one data breakpoint
2762 if ((bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_RW
) == 0 ||
2763 (bp_info
->trigger_type
& ~PPC_BREAKPOINT_TRIGGER_RW
) != 0 ||
2764 bp_info
->condition_mode
!= PPC_BREAKPOINT_CONDITION_NONE
)
2767 if ((unsigned long)bp_info
->addr
>= TASK_SIZE
)
2770 brk
.address
= bp_info
->addr
& ~7UL;
2771 brk
.type
= HW_BRK_TYPE_TRANSLATE
;
2773 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_READ
)
2774 brk
.type
|= HW_BRK_TYPE_READ
;
2775 if (bp_info
->trigger_type
& PPC_BREAKPOINT_TRIGGER_WRITE
)
2776 brk
.type
|= HW_BRK_TYPE_WRITE
;
2777 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2779 * Check if the request is for 'range' breakpoints. We can
2780 * support it if range < 8 bytes.
2782 if (bp_info
->addr_mode
== PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
)
2783 len
= bp_info
->addr2
- bp_info
->addr
;
2784 else if (bp_info
->addr_mode
== PPC_BREAKPOINT_MODE_EXACT
)
2788 bp
= thread
->ptrace_bps
[0];
2792 /* Create a new breakpoint request if one doesn't exist already */
2793 hw_breakpoint_init(&attr
);
2794 attr
.bp_addr
= (unsigned long)bp_info
->addr
& ~HW_BREAKPOINT_ALIGN
;
2796 arch_bp_generic_fields(brk
.type
, &attr
.bp_type
);
2798 thread
->ptrace_bps
[0] = bp
= register_user_hw_breakpoint(&attr
,
2799 ptrace_triggered
, NULL
, child
);
2801 thread
->ptrace_bps
[0] = NULL
;
2806 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2808 if (bp_info
->addr_mode
!= PPC_BREAKPOINT_MODE_EXACT
)
2811 if (child
->thread
.hw_brk
.address
)
2814 child
->thread
.hw_brk
= brk
;
2817 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2820 static long ppc_del_hwdebug(struct task_struct
*child
, long data
)
2822 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2824 struct thread_struct
*thread
= &(child
->thread
);
2825 struct perf_event
*bp
;
2826 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2827 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2831 rc
= del_instruction_bp(child
, (int)data
);
2833 rc
= del_dac(child
, (int)data
- 4);
2836 if (!DBCR_ACTIVE_EVENTS(child
->thread
.debug
.dbcr0
,
2837 child
->thread
.debug
.dbcr1
)) {
2838 child
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
2839 child
->thread
.regs
->msr
&= ~MSR_DE
;
2847 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2848 bp
= thread
->ptrace_bps
[0];
2850 unregister_hw_breakpoint(bp
);
2851 thread
->ptrace_bps
[0] = NULL
;
2855 #else /* CONFIG_HAVE_HW_BREAKPOINT */
2856 if (child
->thread
.hw_brk
.address
== 0)
2859 child
->thread
.hw_brk
.address
= 0;
2860 child
->thread
.hw_brk
.type
= 0;
2861 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2867 long arch_ptrace(struct task_struct
*child
, long request
,
2868 unsigned long addr
, unsigned long data
)
2871 void __user
*datavp
= (void __user
*) data
;
2872 unsigned long __user
*datalp
= datavp
;
2875 /* read the word at location addr in the USER area. */
2876 case PTRACE_PEEKUSR
: {
2877 unsigned long index
, tmp
;
2880 /* convert to index and check */
2883 if ((addr
& 3) || (index
> PT_FPSCR
)
2884 || (child
->thread
.regs
== NULL
))
2887 if ((addr
& 7) || (index
> PT_FPSCR
))
2891 CHECK_FULL_REGS(child
->thread
.regs
);
2892 if (index
< PT_FPR0
) {
2893 ret
= ptrace_get_reg(child
, (int) index
, &tmp
);
2897 unsigned int fpidx
= index
- PT_FPR0
;
2899 flush_fp_to_thread(child
);
2900 if (fpidx
< (PT_FPSCR
- PT_FPR0
))
2901 memcpy(&tmp
, &child
->thread
.TS_FPR(fpidx
),
2904 tmp
= child
->thread
.fp_state
.fpscr
;
2906 ret
= put_user(tmp
, datalp
);
2910 /* write the word at location addr in the USER area */
2911 case PTRACE_POKEUSR
: {
2912 unsigned long index
;
2915 /* convert to index and check */
2918 if ((addr
& 3) || (index
> PT_FPSCR
)
2919 || (child
->thread
.regs
== NULL
))
2922 if ((addr
& 7) || (index
> PT_FPSCR
))
2926 CHECK_FULL_REGS(child
->thread
.regs
);
2927 if (index
< PT_FPR0
) {
2928 ret
= ptrace_put_reg(child
, index
, data
);
2930 unsigned int fpidx
= index
- PT_FPR0
;
2932 flush_fp_to_thread(child
);
2933 if (fpidx
< (PT_FPSCR
- PT_FPR0
))
2934 memcpy(&child
->thread
.TS_FPR(fpidx
), &data
,
2937 child
->thread
.fp_state
.fpscr
= data
;
2943 case PPC_PTRACE_GETHWDBGINFO
: {
2944 struct ppc_debug_info dbginfo
;
2946 dbginfo
.version
= 1;
2947 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2948 dbginfo
.num_instruction_bps
= CONFIG_PPC_ADV_DEBUG_IACS
;
2949 dbginfo
.num_data_bps
= CONFIG_PPC_ADV_DEBUG_DACS
;
2950 dbginfo
.num_condition_regs
= CONFIG_PPC_ADV_DEBUG_DVCS
;
2951 dbginfo
.data_bp_alignment
= 4;
2952 dbginfo
.sizeof_condition
= 4;
2953 dbginfo
.features
= PPC_DEBUG_FEATURE_INSN_BP_RANGE
|
2954 PPC_DEBUG_FEATURE_INSN_BP_MASK
;
2955 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2957 PPC_DEBUG_FEATURE_DATA_BP_RANGE
|
2958 PPC_DEBUG_FEATURE_DATA_BP_MASK
;
2960 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
2961 dbginfo
.num_instruction_bps
= 0;
2962 dbginfo
.num_data_bps
= 1;
2963 dbginfo
.num_condition_regs
= 0;
2965 dbginfo
.data_bp_alignment
= 8;
2967 dbginfo
.data_bp_alignment
= 4;
2969 dbginfo
.sizeof_condition
= 0;
2970 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2971 dbginfo
.features
= PPC_DEBUG_FEATURE_DATA_BP_RANGE
;
2972 if (cpu_has_feature(CPU_FTR_DAWR
))
2973 dbginfo
.features
|= PPC_DEBUG_FEATURE_DATA_BP_DAWR
;
2975 dbginfo
.features
= 0;
2976 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2977 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2979 if (!access_ok(VERIFY_WRITE
, datavp
,
2980 sizeof(struct ppc_debug_info
)))
2982 ret
= __copy_to_user(datavp
, &dbginfo
,
2983 sizeof(struct ppc_debug_info
)) ?
2988 case PPC_PTRACE_SETHWDEBUG
: {
2989 struct ppc_hw_breakpoint bp_info
;
2991 if (!access_ok(VERIFY_READ
, datavp
,
2992 sizeof(struct ppc_hw_breakpoint
)))
2994 ret
= __copy_from_user(&bp_info
, datavp
,
2995 sizeof(struct ppc_hw_breakpoint
)) ?
2998 ret
= ppc_set_hwdebug(child
, &bp_info
);
3002 case PPC_PTRACE_DELHWDEBUG
: {
3003 ret
= ppc_del_hwdebug(child
, data
);
3007 case PTRACE_GET_DEBUGREG
: {
3008 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
3009 unsigned long dabr_fake
;
3012 /* We only support one DABR and no IABRS at the moment */
3015 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
3016 ret
= put_user(child
->thread
.debug
.dac1
, datalp
);
3018 dabr_fake
= ((child
->thread
.hw_brk
.address
& (~HW_BRK_TYPE_DABR
)) |
3019 (child
->thread
.hw_brk
.type
& HW_BRK_TYPE_DABR
));
3020 ret
= put_user(dabr_fake
, datalp
);
3025 case PTRACE_SET_DEBUGREG
:
3026 ret
= ptrace_set_debugreg(child
, addr
, data
);
3030 case PTRACE_GETREGS64
:
3032 case PTRACE_GETREGS
: /* Get all pt_regs from the child. */
3033 return copy_regset_to_user(child
, &user_ppc_native_view
,
3035 0, sizeof(struct pt_regs
),
3039 case PTRACE_SETREGS64
:
3041 case PTRACE_SETREGS
: /* Set all gp regs in the child. */
3042 return copy_regset_from_user(child
, &user_ppc_native_view
,
3044 0, sizeof(struct pt_regs
),
3047 case PTRACE_GETFPREGS
: /* Get the child FPU state (FPR0...31 + FPSCR) */
3048 return copy_regset_to_user(child
, &user_ppc_native_view
,
3050 0, sizeof(elf_fpregset_t
),
3053 case PTRACE_SETFPREGS
: /* Set the child FPU state (FPR0...31 + FPSCR) */
3054 return copy_regset_from_user(child
, &user_ppc_native_view
,
3056 0, sizeof(elf_fpregset_t
),
3059 #ifdef CONFIG_ALTIVEC
3060 case PTRACE_GETVRREGS
:
3061 return copy_regset_to_user(child
, &user_ppc_native_view
,
3063 0, (33 * sizeof(vector128
) +
3067 case PTRACE_SETVRREGS
:
3068 return copy_regset_from_user(child
, &user_ppc_native_view
,
3070 0, (33 * sizeof(vector128
) +
3075 case PTRACE_GETVSRREGS
:
3076 return copy_regset_to_user(child
, &user_ppc_native_view
,
3078 0, 32 * sizeof(double),
3081 case PTRACE_SETVSRREGS
:
3082 return copy_regset_from_user(child
, &user_ppc_native_view
,
3084 0, 32 * sizeof(double),
3088 case PTRACE_GETEVRREGS
:
3089 /* Get the child spe register state. */
3090 return copy_regset_to_user(child
, &user_ppc_native_view
,
3091 REGSET_SPE
, 0, 35 * sizeof(u32
),
3094 case PTRACE_SETEVRREGS
:
3095 /* Set the child spe register state. */
3096 return copy_regset_from_user(child
, &user_ppc_native_view
,
3097 REGSET_SPE
, 0, 35 * sizeof(u32
),
3102 ret
= ptrace_request(child
, request
, addr
, data
);
3108 #ifdef CONFIG_SECCOMP
3109 static int do_seccomp(struct pt_regs
*regs
)
3111 if (!test_thread_flag(TIF_SECCOMP
))
3115 * The ABI we present to seccomp tracers is that r3 contains
3116 * the syscall return value and orig_gpr3 contains the first
3117 * syscall parameter. This is different to the ptrace ABI where
3118 * both r3 and orig_gpr3 contain the first syscall parameter.
3120 regs
->gpr
[3] = -ENOSYS
;
3123 * We use the __ version here because we have already checked
3124 * TIF_SECCOMP. If this fails, there is nothing left to do, we
3125 * have already loaded -ENOSYS into r3, or seccomp has put
3126 * something else in r3 (via SECCOMP_RET_ERRNO/TRACE).
3128 if (__secure_computing(NULL
))
3132 * The syscall was allowed by seccomp, restore the register
3133 * state to what audit expects.
3134 * Note that we use orig_gpr3, which means a seccomp tracer can
3135 * modify the first syscall parameter (in orig_gpr3) and also
3136 * allow the syscall to proceed.
3138 regs
->gpr
[3] = regs
->orig_gpr3
;
3143 static inline int do_seccomp(struct pt_regs
*regs
) { return 0; }
3144 #endif /* CONFIG_SECCOMP */
3147 * do_syscall_trace_enter() - Do syscall tracing on kernel entry.
3148 * @regs: the pt_regs of the task to trace (current)
3150 * Performs various types of tracing on syscall entry. This includes seccomp,
3151 * ptrace, syscall tracepoints and audit.
3153 * The pt_regs are potentially visible to userspace via ptrace, so their
3156 * One or more of the tracers may modify the contents of pt_regs, in particular
3157 * to modify arguments or even the syscall number itself.
3159 * It's also possible that a tracer can choose to reject the system call. In
3160 * that case this function will return an illegal syscall number, and will put
3161 * an appropriate return value in regs->r3.
3163 * Return: the (possibly changed) syscall number.
3165 long do_syscall_trace_enter(struct pt_regs
*regs
)
3170 * The tracer may decide to abort the syscall, if so tracehook
3171 * will return !0. Note that the tracer may also just change
3172 * regs->gpr[0] to an invalid syscall number, that is handled
3173 * below on the exit path.
3175 if (test_thread_flag(TIF_SYSCALL_TRACE
) &&
3176 tracehook_report_syscall_entry(regs
))
3179 /* Run seccomp after ptrace; allow it to set gpr[3]. */
3180 if (do_seccomp(regs
))
3183 /* Avoid trace and audit when syscall is invalid. */
3184 if (regs
->gpr
[0] >= NR_syscalls
)
3187 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT
)))
3188 trace_sys_enter(regs
, regs
->gpr
[0]);
3191 if (!is_32bit_task())
3192 audit_syscall_entry(regs
->gpr
[0], regs
->gpr
[3], regs
->gpr
[4],
3193 regs
->gpr
[5], regs
->gpr
[6]);
3196 audit_syscall_entry(regs
->gpr
[0],
3197 regs
->gpr
[3] & 0xffffffff,
3198 regs
->gpr
[4] & 0xffffffff,
3199 regs
->gpr
[5] & 0xffffffff,
3200 regs
->gpr
[6] & 0xffffffff);
3202 /* Return the possibly modified but valid syscall number */
3203 return regs
->gpr
[0];
3207 * If we are aborting explicitly, or if the syscall number is
3208 * now invalid, set the return value to -ENOSYS.
3210 regs
->gpr
[3] = -ENOSYS
;
3214 void do_syscall_trace_leave(struct pt_regs
*regs
)
3218 audit_syscall_exit(regs
);
3220 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT
)))
3221 trace_sys_exit(regs
, regs
->result
);
3223 step
= test_thread_flag(TIF_SINGLESTEP
);
3224 if (step
|| test_thread_flag(TIF_SYSCALL_TRACE
))
3225 tracehook_report_syscall_exit(regs
, step
);