arch/powerpc/kernel/tm.S

   1 /*
   2  * Transactional memory support routines to reclaim and recheckpoint
   3  * transactional process state.
   4  *
   5  * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
   6  */
   7
   8 #include <asm/asm-offsets.h>
   9 #include <asm/ppc_asm.h>
  10 #include <asm/ppc-opcode.h>
  11 #include <asm/ptrace.h>
  12 #include <asm/reg.h>
  13
  14 #ifdef CONFIG_VSX
  15 /* See fpu.S, this is very similar but to save/restore checkpointed FPRs/VSRs */
  16 #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base)   \
  17 BEGIN_FTR_SECTION                               \
  18         b       2f;                             \
  19 END_FTR_SECTION_IFSET(CPU_FTR_VSX);             \
  20         SAVE_32FPRS_TRANSACT(n,base);           \
  21         b       3f;                             \
  22 2:      SAVE_32VSRS_TRANSACT(n,c,base);         \
  23 3:
  24 /* ...and this is just plain borrowed from there. */
  25 #define __REST_32FPRS_VSRS(n,c,base)            \
  26 BEGIN_FTR_SECTION                               \
  27         b       2f;                             \
  28 END_FTR_SECTION_IFSET(CPU_FTR_VSX);             \
  29         REST_32FPRS(n,base);                    \
  30         b       3f;                             \
  31 2:      REST_32VSRS(n,c,base);                  \
  32 3:
  33 #else
  34 #define __SAVE_32FPRS_VSRS_TRANSACT(n,c,base) SAVE_32FPRS_TRANSACT(n, base)
  35 #define __REST_32FPRS_VSRS(n,c,base)          REST_32FPRS(n, base)
  36 #endif
  37 #define SAVE_32FPRS_VSRS_TRANSACT(n,c,base) \
  38         __SAVE_32FPRS_VSRS_TRANSACT(n,__REG_##c,__REG_##base)
  39 #define REST_32FPRS_VSRS(n,c,base) \
  40         __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
  41
  42 /* Stack frame offsets for local variables. */
  43 #define TM_FRAME_L0     TM_FRAME_SIZE-16
  44 #define TM_FRAME_L1     TM_FRAME_SIZE-8
  45 #define STACK_PARAM(x)  (48+((x)*8))
  46
  47
  48 /* In order to access the TM SPRs, TM must be enabled.  So, do so: */
  49 _GLOBAL(tm_enable)
  50         mfmsr   r4
  51         li      r3, MSR_TM >> 32
  52         sldi    r3, r3, 32
  53         and.    r0, r4, r3
  54         bne     1f
  55         or      r4, r4, r3
  56         mtmsrd  r4
  57 1:      blr
  58
  59 _GLOBAL(tm_save_sprs)
  60         mfspr   r0, SPRN_TFHAR
  61         std     r0, THREAD_TM_TFHAR(r3)
  62         mfspr   r0, SPRN_TEXASR
  63         std     r0, THREAD_TM_TEXASR(r3)
  64         mfspr   r0, SPRN_TFIAR
  65         std     r0, THREAD_TM_TFIAR(r3)
  66         blr
  67
  68 _GLOBAL(tm_restore_sprs)
  69         ld      r0, THREAD_TM_TFHAR(r3)
  70         mtspr   SPRN_TFHAR, r0
  71         ld      r0, THREAD_TM_TEXASR(r3)
  72         mtspr   SPRN_TEXASR, r0
  73         ld      r0, THREAD_TM_TFIAR(r3)
  74         mtspr   SPRN_TFIAR, r0
  75         blr
  76
  77         /* Passed an 8-bit failure cause as first argument. */
  78 _GLOBAL(tm_abort)
  79         TABORT(R3)
  80         blr
  81
  82
  83 /* void tm_reclaim(struct thread_struct *thread,
  84  *                 unsigned long orig_msr,
  85  *                 uint8_t cause)
  86  *
  87  *      - Performs a full reclaim.  This destroys outstanding
  88  *        transactions and updates thread->regs.tm_ckpt_* with the
  89  *        original checkpointed state.  Note that thread->regs is
  90  *        unchanged.
  91  *      - FP regs are written back to thread->transact_fpr before
  92  *        reclaiming.  These are the transactional (current) versions.
  93  *
  94  * Purpose is to both abort transactions of, and preserve the state of,
  95  * a transactions at a context switch. We preserve/restore both sets of process
  96  * state to restore them when the thread's scheduled again.  We continue in
  97  * userland as though nothing happened, but when the transaction is resumed
  98  * they will abort back to the checkpointed state we save out here.
  99  *
 100  * Call with IRQs off, stacks get all out of sync for some periods in here!
 101  */
 102 _GLOBAL(tm_reclaim)
 103         mfcr    r6
 104         mflr    r0
 105         std     r6, 8(r1)
 106         std     r0, 16(r1)
 107         std     r2, 40(r1)
 108         stdu    r1, -TM_FRAME_SIZE(r1)
 109
 110         /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
 111
 112         std     r3, STACK_PARAM(0)(r1)
 113         SAVE_NVGPRS(r1)
 114
 115         mfmsr   r14
 116         mr      r15, r14
 117         ori     r15, r15, MSR_FP
 118         oris    r15, r15, MSR_VEC@h
 119 #ifdef CONFIG_VSX
 120         BEGIN_FTR_SECTION
 121         oris    r15,r15, MSR_VSX@h
 122         END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 123 #endif
 124         mtmsrd  r15
 125         std     r14, TM_FRAME_L0(r1)
 126
 127         /* Stash the stack pointer away for use after reclaim */
 128         std     r1, PACAR1(r13)
 129
 130         /* ******************** FPR/VR/VSRs ************
 131          * Before reclaiming, capture the current/transactional FPR/VR
 132         * versions /if used/.
 133          *
 134          * (If VSX used, FP and VMX are implied.  Or, we don't need to look
 135          * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
 136          *
 137          * We're passed the thread's MSR as parameter 2.
 138          *
 139          * We enabled VEC/FP/VSX in the msr above, so we can execute these
 140          * instructions!
 141          */
 142         andis.          r0, r4, MSR_VEC@h
 143         beq     dont_backup_vec
 144
 145         SAVE_32VRS_TRANSACT(0, r6, r3)  /* r6 scratch, r3 thread */
 146         mfvscr  vr0
 147         li      r6, THREAD_TRANSACT_VSCR
 148         stvx    vr0, r3, r6
 149         mfspr   r0, SPRN_VRSAVE
 150         std     r0, THREAD_TRANSACT_VRSAVE(r3)
 151
 152 dont_backup_vec:
 153         andi.   r0, r4, MSR_FP
 154         beq     dont_backup_fp
 155
 156         SAVE_32FPRS_VSRS_TRANSACT(0, R6, R3)    /* r6 scratch, r3 thread */
 157
 158         mffs    fr0
 159         stfd    fr0,THREAD_TRANSACT_FPSCR(r3)
 160
 161 dont_backup_fp:
 162         /* The moment we treclaim, ALL of our GPRs will switch
 163          * to user register state.  (FPRs, CCR etc. also!)
 164          * Use an sprg and a tm_scratch in the PACA to shuffle.
 165          */
 166         TRECLAIM(R5)                            /* Cause in r5 */
 167
 168         /* ******************** GPRs ******************** */
 169         /* Stash the checkpointed r13 away in the scratch SPR and get the real
 170          *  paca
 171          */
 172         SET_SCRATCH0(r13)
 173         GET_PACA(r13)
 174
 175         /* Stash the checkpointed r1 away in paca tm_scratch and get the real
 176          * stack pointer back
 177          */
 178         std     r1, PACATMSCRATCH(r13)
 179         ld      r1, PACAR1(r13)
 180
 181         /* Now get some more GPRS free */
 182         std     r7, GPR7(r1)                    /* Temporary stash */
 183         std     r12, GPR12(r1)                  /* ''   ''    ''   */
 184         ld      r12, STACK_PARAM(0)(r1)         /* Param 0, thread_struct * */
 185
 186         addi    r7, r12, PT_CKPT_REGS           /* Thread's ckpt_regs */
 187
 188         /* Make r7 look like an exception frame so that we
 189          * can use the neat GPRx(n) macros.  r7 is NOT a pt_regs ptr!
 190          */
 191         subi    r7, r7, STACK_FRAME_OVERHEAD
 192
 193         /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
 194         SAVE_GPR(0, r7)                         /* user r0 */
 195         SAVE_GPR(2, r7)                 /* user r2 */
 196         SAVE_4GPRS(3, r7)                       /* user r3-r6 */
 197         SAVE_4GPRS(8, r7)                       /* user r8-r11 */
 198         ld      r3, PACATMSCRATCH(r13)          /* user r1 */
 199         ld      r4, GPR7(r1)                    /* user r7 */
 200         ld      r5, GPR12(r1)                   /* user r12 */
 201         GET_SCRATCH0(6)                         /* user r13 */
 202         std     r3, GPR1(r7)
 203         std     r4, GPR7(r7)
 204         std     r5, GPR12(r7)
 205         std     r6, GPR13(r7)
 206
 207         SAVE_NVGPRS(r7)                         /* user r14-r31 */
 208
 209         /* ******************** NIP ******************** */
 210         mfspr   r3, SPRN_TFHAR
 211         std     r3, _NIP(r7)                    /* Returns to failhandler */
 212         /* The checkpointed NIP is ignored when rescheduling/rechkpting,
 213          * but is used in signal return to 'wind back' to the abort handler.
 214          */
 215
 216         /* ******************** CR,LR,CCR,MSR ********** */
 217         mfctr   r3
 218         mflr    r4
 219         mfcr    r5
 220         mfxer   r6
 221
 222         std     r3, _CTR(r7)
 223         std     r4, _LINK(r7)
 224         std     r5, _CCR(r7)
 225         std     r6, _XER(r7)
 226
 227         /* MSR and flags:  We don't change CRs, and we don't need to alter
 228          * MSR.
 229          */
 230
 231         /* TM regs, incl TEXASR -- these live in thread_struct.  Note they've
 232          * been updated by the treclaim, to explain to userland the failure
 233          * cause (aborted).
 234          */
 235         mfspr   r0, SPRN_TEXASR
 236         mfspr   r3, SPRN_TFHAR
 237         mfspr   r4, SPRN_TFIAR
 238         std     r0, THREAD_TM_TEXASR(r12)
 239         std     r3, THREAD_TM_TFHAR(r12)
 240         std     r4, THREAD_TM_TFIAR(r12)
 241
 242         /* AMR and PPR are checkpointed too, but are unsupported by Linux. */
 243
 244         /* Restore original MSR/IRQ state & clear TM mode */
 245         ld      r14, TM_FRAME_L0(r1)            /* Orig MSR */
 246         li      r15, 0
 247         rldimi  r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
 248         mtmsrd  r14
 249
 250         REST_NVGPRS(r1)
 251
 252         addi    r1, r1, TM_FRAME_SIZE
 253         ld      r4, 8(r1)
 254         ld      r0, 16(r1)
 255         mtcr    r4
 256         mtlr    r0
 257         ld      r2, 40(r1)
 258         blr
 259
 260
 261         /* void tm_recheckpoint(struct thread_struct *thread,
 262          *                      unsigned long orig_msr)
 263          *      - Restore the checkpointed register state saved by tm_reclaim
 264          *        when we switch_to a process.
 265          *
 266          *      Call with IRQs off, stacks get all out of sync for
 267          *      some periods in here!
 268          */
 269 _GLOBAL(tm_recheckpoint)
 270         mfcr    r5
 271         mflr    r0
 272         std     r5, 8(r1)
 273         std     r0, 16(r1)
 274         std     r2, 40(r1)
 275         stdu    r1, -TM_FRAME_SIZE(r1)
 276
 277         /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
 278          * This is used for backing up the NVGPRs:
 279          */
 280         SAVE_NVGPRS(r1)
 281
 282         std     r1, PACAR1(r13)
 283
 284         /* Load complete register state from ts_ckpt* registers */
 285
 286         addi    r7, r3, PT_CKPT_REGS            /* Thread's ckpt_regs */
 287
 288         /* Make r7 look like an exception frame so that we
 289          * can use the neat GPRx(n) macros.  r7 is now NOT a pt_regs ptr!
 290          */
 291         subi    r7, r7, STACK_FRAME_OVERHEAD
 292
 293         SET_SCRATCH0(r1)
 294
 295         mfmsr   r6
 296         /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
 297
 298         /* Enable FP/vec in MSR if necessary! */
 299         lis     r5, MSR_VEC@h
 300         ori     r5, r5, MSR_FP
 301         and.    r5, r4, r5
 302         beq     restore_gprs                    /* if neither, skip both */
 303
 304 #ifdef CONFIG_VSX
 305         BEGIN_FTR_SECTION
 306         oris    r5, r5, MSR_VSX@h
 307         END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 308 #endif
 309         or      r5, r6, r5                      /* Set MSR.FP+.VSX/.VEC */
 310         mtmsr   r5
 311
 312         /* FP and VEC registers:  These are recheckpointed from thread.fpr[]
 313          * and thread.vr[] respectively.  The thread.transact_fpr[] version
 314          * is more modern, and will be loaded subsequently by any FPUnavailable
 315          * trap.
 316          */
 317         andis.  r0, r4, MSR_VEC@h
 318         beq     dont_restore_vec
 319
 320         li      r5, THREAD_VSCR
 321         lvx     vr0, r3, r5
 322         mtvscr  vr0
 323         REST_32VRS(0, r5, r3)                   /* r5 scratch, r3 THREAD ptr */
 324         ld      r5, THREAD_VRSAVE(r3)
 325         mtspr   SPRN_VRSAVE, r5
 326
 327 dont_restore_vec:
 328         andi.   r0, r4, MSR_FP
 329         beq     dont_restore_fp
 330
 331         lfd     fr0, THREAD_FPSCR(r3)
 332         MTFSF_L(fr0)
 333         REST_32FPRS_VSRS(0, R4, R3)
 334
 335 dont_restore_fp:
 336         mtmsr   r6                              /* FP/Vec off again! */
 337
 338 restore_gprs:
 339         /* ******************** CR,LR,CCR,MSR ********** */
 340         ld      r3, _CTR(r7)
 341         ld      r4, _LINK(r7)
 342         ld      r5, _CCR(r7)
 343         ld      r6, _XER(r7)
 344
 345         mtctr   r3
 346         mtlr    r4
 347         mtcr    r5
 348         mtxer   r6
 349
 350         /* MSR and flags:  We don't change CRs, and we don't need to alter
 351          * MSR.
 352          */
 353
 354         REST_4GPRS(0, r7)                       /* GPR0-3 */
 355         REST_GPR(4, r7)                         /* GPR4-6 */
 356         REST_GPR(5, r7)
 357         REST_GPR(6, r7)
 358         REST_4GPRS(8, r7)                       /* GPR8-11 */
 359         REST_2GPRS(12, r7)                      /* GPR12-13 */
 360
 361         REST_NVGPRS(r7)                         /* GPR14-31 */
 362
 363         ld      r7, GPR7(r7)                    /* GPR7 */
 364
 365         /* Commit register state as checkpointed state: */
 366         TRECHKPT
 367
 368         /* Our transactional state has now changed.
 369          *
 370          * Now just get out of here.  Transactional (current) state will be
 371          * updated once restore is called on the return path in the _switch-ed
 372          * -to process.
 373          */
 374
 375         GET_PACA(r13)
 376         GET_SCRATCH0(r1)
 377
 378         REST_NVGPRS(r1)
 379
 380         addi    r1, r1, TM_FRAME_SIZE
 381         ld      r4, 8(r1)
 382         ld      r0, 16(r1)
 383         mtcr    r4
 384         mtlr    r0
 385         ld      r2, 40(r1)
 386         blr
 387
 388         /* ****************************************************************** */