2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38 #include <linux/context_tracking.h>
40 #include <asm/emulated_ops.h>
41 #include <asm/pgtable.h>
42 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
48 #ifdef CONFIG_PMAC_BACKLIGHT
49 #include <asm/backlight.h>
52 #include <asm/firmware.h>
53 #include <asm/processor.h>
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
62 #include <asm/debug.h>
63 #include <asm/asm-prototypes.h>
65 #include <sysdev/fsl_pci.h>
67 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
68 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
69 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
70 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
71 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
72 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
73 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
74 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
76 EXPORT_SYMBOL(__debugger
);
77 EXPORT_SYMBOL(__debugger_ipi
);
78 EXPORT_SYMBOL(__debugger_bpt
);
79 EXPORT_SYMBOL(__debugger_sstep
);
80 EXPORT_SYMBOL(__debugger_iabr_match
);
81 EXPORT_SYMBOL(__debugger_break_match
);
82 EXPORT_SYMBOL(__debugger_fault_handler
);
85 /* Transactional Memory trap debug */
87 #define TM_DEBUG(x...) printk(KERN_INFO x)
89 #define TM_DEBUG(x...) do { } while(0)
93 * Trap & Exception support
96 #ifdef CONFIG_PMAC_BACKLIGHT
97 static void pmac_backlight_unblank(void)
99 mutex_lock(&pmac_backlight_mutex
);
100 if (pmac_backlight
) {
101 struct backlight_properties
*props
;
103 props
= &pmac_backlight
->props
;
104 props
->brightness
= props
->max_brightness
;
105 props
->power
= FB_BLANK_UNBLANK
;
106 backlight_update_status(pmac_backlight
);
108 mutex_unlock(&pmac_backlight_mutex
);
111 static inline void pmac_backlight_unblank(void) { }
114 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
115 static int die_owner
= -1;
116 static unsigned int die_nest_count
;
117 static int die_counter
;
119 static unsigned __kprobes
long oops_begin(struct pt_regs
*regs
)
129 /* racy, but better than risking deadlock. */
130 raw_local_irq_save(flags
);
131 cpu
= smp_processor_id();
132 if (!arch_spin_trylock(&die_lock
)) {
133 if (cpu
== die_owner
)
134 /* nested oops. should stop eventually */;
136 arch_spin_lock(&die_lock
);
142 if (machine_is(powermac
))
143 pmac_backlight_unblank();
147 static void __kprobes
oops_end(unsigned long flags
, struct pt_regs
*regs
,
152 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
157 /* Nest count reaches zero, release the lock. */
158 arch_spin_unlock(&die_lock
);
159 raw_local_irq_restore(flags
);
161 crash_fadump(regs
, "die oops");
164 * A system reset (0x100) is a request to dump, so we always send
165 * it through the crashdump code.
167 if (kexec_should_crash(current
) || (TRAP(regs
) == 0x100)) {
171 * We aren't the primary crash CPU. We need to send it
172 * to a holding pattern to avoid it ending up in the panic
175 crash_kexec_secondary(regs
);
182 * While our oops output is serialised by a spinlock, output
183 * from panic() called below can race and corrupt it. If we
184 * know we are going to panic, delay for 1 second so we have a
185 * chance to get clean backtraces from all CPUs that are oopsing.
187 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
188 is_global_init(current
)) {
189 mdelay(MSEC_PER_SEC
);
193 panic("Fatal exception in interrupt");
195 panic("Fatal exception");
199 static int __kprobes
__die(const char *str
, struct pt_regs
*regs
, long err
)
201 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
202 #ifdef CONFIG_PREEMPT
206 printk("SMP NR_CPUS=%d ", NR_CPUS
);
208 if (debug_pagealloc_enabled())
209 printk("DEBUG_PAGEALLOC ");
213 printk("%s\n", ppc_md
.name
? ppc_md
.name
: "");
215 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
224 void die(const char *str
, struct pt_regs
*regs
, long err
)
226 unsigned long flags
= oops_begin(regs
);
228 if (__die(str
, regs
, err
))
230 oops_end(flags
, regs
, err
);
233 void user_single_step_siginfo(struct task_struct
*tsk
,
234 struct pt_regs
*regs
, siginfo_t
*info
)
236 memset(info
, 0, sizeof(*info
));
237 info
->si_signo
= SIGTRAP
;
238 info
->si_code
= TRAP_TRACE
;
239 info
->si_addr
= (void __user
*)regs
->nip
;
242 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
245 const char fmt32
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
246 "at %08lx nip %08lx lr %08lx code %x\n";
247 const char fmt64
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
248 "at %016lx nip %016lx lr %016lx code %x\n";
250 if (!user_mode(regs
)) {
251 die("Exception in kernel mode", regs
, signr
);
255 if (show_unhandled_signals
&& unhandled_signal(current
, signr
)) {
256 printk_ratelimited(regs
->msr
& MSR_64BIT
? fmt64
: fmt32
,
257 current
->comm
, current
->pid
, signr
,
258 addr
, regs
->nip
, regs
->link
, code
);
261 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
264 current
->thread
.trap_nr
= code
;
265 memset(&info
, 0, sizeof(info
));
266 info
.si_signo
= signr
;
268 info
.si_addr
= (void __user
*) addr
;
269 force_sig_info(signr
, &info
, current
);
273 void system_reset_exception(struct pt_regs
*regs
)
275 /* See if any machine dependent calls */
276 if (ppc_md
.system_reset_exception
) {
277 if (ppc_md
.system_reset_exception(regs
))
281 die("System Reset", regs
, SIGABRT
);
283 /* Must die if the interrupt is not recoverable */
284 if (!(regs
->msr
& MSR_RI
))
285 panic("Unrecoverable System Reset");
287 /* What should we do here? We could issue a shutdown or hard reset. */
291 * This function is called in real mode. Strictly no printk's please.
293 * regs->nip and regs->msr contains srr0 and ssr1.
295 long machine_check_early(struct pt_regs
*regs
)
299 __this_cpu_inc(irq_stat
.mce_exceptions
);
301 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
303 if (cur_cpu_spec
&& cur_cpu_spec
->machine_check_early
)
304 handled
= cur_cpu_spec
->machine_check_early(regs
);
308 long hmi_exception_realmode(struct pt_regs
*regs
)
310 __this_cpu_inc(irq_stat
.hmi_exceptions
);
312 wait_for_subcore_guest_exit();
314 if (ppc_md
.hmi_exception_early
)
315 ppc_md
.hmi_exception_early(regs
);
317 wait_for_tb_resync();
325 * I/O accesses can cause machine checks on powermacs.
326 * Check if the NIP corresponds to the address of a sync
327 * instruction for which there is an entry in the exception
329 * Note that the 601 only takes a machine check on TEA
330 * (transfer error ack) signal assertion, and does not
331 * set any of the top 16 bits of SRR1.
334 static inline int check_io_access(struct pt_regs
*regs
)
337 unsigned long msr
= regs
->msr
;
338 const struct exception_table_entry
*entry
;
339 unsigned int *nip
= (unsigned int *)regs
->nip
;
341 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
342 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
344 * Check that it's a sync instruction, or somewhere
345 * in the twi; isync; nop sequence that inb/inw/inl uses.
346 * As the address is in the exception table
347 * we should be able to read the instr there.
348 * For the debug message, we look at the preceding
351 if (*nip
== 0x60000000) /* nop */
353 else if (*nip
== 0x4c00012c) /* isync */
355 if (*nip
== 0x7c0004ac || (*nip
>> 26) == 3) {
360 rb
= (*nip
>> 11) & 0x1f;
361 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
362 (*nip
& 0x100)? "OUT to": "IN from",
363 regs
->gpr
[rb
] - _IO_BASE
, nip
);
365 regs
->nip
= entry
->fixup
;
369 #endif /* CONFIG_PPC32 */
373 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
374 /* On 4xx, the reason for the machine check or program exception
376 #define get_reason(regs) ((regs)->dsisr)
377 #ifndef CONFIG_FSL_BOOKE
378 #define get_mc_reason(regs) ((regs)->dsisr)
380 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
382 #define REASON_FP ESR_FP
383 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
384 #define REASON_PRIVILEGED ESR_PPR
385 #define REASON_TRAP ESR_PTR
387 /* single-step stuff */
388 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
389 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
392 /* On non-4xx, the reason for the machine check or program
393 exception is in the MSR. */
394 #define get_reason(regs) ((regs)->msr)
395 #define get_mc_reason(regs) ((regs)->msr)
396 #define REASON_TM 0x200000
397 #define REASON_FP 0x100000
398 #define REASON_ILLEGAL 0x80000
399 #define REASON_PRIVILEGED 0x40000
400 #define REASON_TRAP 0x20000
402 #define single_stepping(regs) ((regs)->msr & MSR_SE)
403 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
406 #if defined(CONFIG_4xx)
407 int machine_check_4xx(struct pt_regs
*regs
)
409 unsigned long reason
= get_mc_reason(regs
);
411 if (reason
& ESR_IMCP
) {
412 printk("Instruction");
413 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
416 printk(" machine check in kernel mode.\n");
421 int machine_check_440A(struct pt_regs
*regs
)
423 unsigned long reason
= get_mc_reason(regs
);
425 printk("Machine check in kernel mode.\n");
426 if (reason
& ESR_IMCP
){
427 printk("Instruction Synchronous Machine Check exception\n");
428 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
431 u32 mcsr
= mfspr(SPRN_MCSR
);
433 printk("Instruction Read PLB Error\n");
435 printk("Data Read PLB Error\n");
437 printk("Data Write PLB Error\n");
438 if (mcsr
& MCSR_TLBP
)
439 printk("TLB Parity Error\n");
440 if (mcsr
& MCSR_ICP
){
441 flush_instruction_cache();
442 printk("I-Cache Parity Error\n");
444 if (mcsr
& MCSR_DCSP
)
445 printk("D-Cache Search Parity Error\n");
446 if (mcsr
& MCSR_DCFP
)
447 printk("D-Cache Flush Parity Error\n");
448 if (mcsr
& MCSR_IMPE
)
449 printk("Machine Check exception is imprecise\n");
452 mtspr(SPRN_MCSR
, mcsr
);
457 int machine_check_47x(struct pt_regs
*regs
)
459 unsigned long reason
= get_mc_reason(regs
);
462 printk(KERN_ERR
"Machine check in kernel mode.\n");
463 if (reason
& ESR_IMCP
) {
465 "Instruction Synchronous Machine Check exception\n");
466 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
469 mcsr
= mfspr(SPRN_MCSR
);
471 printk(KERN_ERR
"Instruction Read PLB Error\n");
473 printk(KERN_ERR
"Data Read PLB Error\n");
475 printk(KERN_ERR
"Data Write PLB Error\n");
476 if (mcsr
& MCSR_TLBP
)
477 printk(KERN_ERR
"TLB Parity Error\n");
478 if (mcsr
& MCSR_ICP
) {
479 flush_instruction_cache();
480 printk(KERN_ERR
"I-Cache Parity Error\n");
482 if (mcsr
& MCSR_DCSP
)
483 printk(KERN_ERR
"D-Cache Search Parity Error\n");
484 if (mcsr
& PPC47x_MCSR_GPR
)
485 printk(KERN_ERR
"GPR Parity Error\n");
486 if (mcsr
& PPC47x_MCSR_FPR
)
487 printk(KERN_ERR
"FPR Parity Error\n");
488 if (mcsr
& PPC47x_MCSR_IPR
)
489 printk(KERN_ERR
"Machine Check exception is imprecise\n");
492 mtspr(SPRN_MCSR
, mcsr
);
496 #elif defined(CONFIG_E500)
497 int machine_check_e500mc(struct pt_regs
*regs
)
499 unsigned long mcsr
= mfspr(SPRN_MCSR
);
500 unsigned long reason
= mcsr
;
503 if (reason
& MCSR_LD
) {
504 recoverable
= fsl_rio_mcheck_exception(regs
);
505 if (recoverable
== 1)
509 printk("Machine check in kernel mode.\n");
510 printk("Caused by (from MCSR=%lx): ", reason
);
512 if (reason
& MCSR_MCP
)
513 printk("Machine Check Signal\n");
515 if (reason
& MCSR_ICPERR
) {
516 printk("Instruction Cache Parity Error\n");
519 * This is recoverable by invalidating the i-cache.
521 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
522 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
526 * This will generally be accompanied by an instruction
527 * fetch error report -- only treat MCSR_IF as fatal
528 * if it wasn't due to an L1 parity error.
533 if (reason
& MCSR_DCPERR_MC
) {
534 printk("Data Cache Parity Error\n");
537 * In write shadow mode we auto-recover from the error, but it
538 * may still get logged and cause a machine check. We should
539 * only treat the non-write shadow case as non-recoverable.
541 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
545 if (reason
& MCSR_L2MMU_MHIT
) {
546 printk("Hit on multiple TLB entries\n");
550 if (reason
& MCSR_NMI
)
551 printk("Non-maskable interrupt\n");
553 if (reason
& MCSR_IF
) {
554 printk("Instruction Fetch Error Report\n");
558 if (reason
& MCSR_LD
) {
559 printk("Load Error Report\n");
563 if (reason
& MCSR_ST
) {
564 printk("Store Error Report\n");
568 if (reason
& MCSR_LDG
) {
569 printk("Guarded Load Error Report\n");
573 if (reason
& MCSR_TLBSYNC
)
574 printk("Simultaneous tlbsync operations\n");
576 if (reason
& MCSR_BSL2_ERR
) {
577 printk("Level 2 Cache Error\n");
581 if (reason
& MCSR_MAV
) {
584 addr
= mfspr(SPRN_MCAR
);
585 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
587 printk("Machine Check %s Address: %#llx\n",
588 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
592 mtspr(SPRN_MCSR
, mcsr
);
593 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
596 int machine_check_e500(struct pt_regs
*regs
)
598 unsigned long reason
= get_mc_reason(regs
);
600 if (reason
& MCSR_BUS_RBERR
) {
601 if (fsl_rio_mcheck_exception(regs
))
603 if (fsl_pci_mcheck_exception(regs
))
607 printk("Machine check in kernel mode.\n");
608 printk("Caused by (from MCSR=%lx): ", reason
);
610 if (reason
& MCSR_MCP
)
611 printk("Machine Check Signal\n");
612 if (reason
& MCSR_ICPERR
)
613 printk("Instruction Cache Parity Error\n");
614 if (reason
& MCSR_DCP_PERR
)
615 printk("Data Cache Push Parity Error\n");
616 if (reason
& MCSR_DCPERR
)
617 printk("Data Cache Parity Error\n");
618 if (reason
& MCSR_BUS_IAERR
)
619 printk("Bus - Instruction Address Error\n");
620 if (reason
& MCSR_BUS_RAERR
)
621 printk("Bus - Read Address Error\n");
622 if (reason
& MCSR_BUS_WAERR
)
623 printk("Bus - Write Address Error\n");
624 if (reason
& MCSR_BUS_IBERR
)
625 printk("Bus - Instruction Data Error\n");
626 if (reason
& MCSR_BUS_RBERR
)
627 printk("Bus - Read Data Bus Error\n");
628 if (reason
& MCSR_BUS_WBERR
)
629 printk("Bus - Write Data Bus Error\n");
630 if (reason
& MCSR_BUS_IPERR
)
631 printk("Bus - Instruction Parity Error\n");
632 if (reason
& MCSR_BUS_RPERR
)
633 printk("Bus - Read Parity Error\n");
638 int machine_check_generic(struct pt_regs
*regs
)
642 #elif defined(CONFIG_E200)
643 int machine_check_e200(struct pt_regs
*regs
)
645 unsigned long reason
= get_mc_reason(regs
);
647 printk("Machine check in kernel mode.\n");
648 printk("Caused by (from MCSR=%lx): ", reason
);
650 if (reason
& MCSR_MCP
)
651 printk("Machine Check Signal\n");
652 if (reason
& MCSR_CP_PERR
)
653 printk("Cache Push Parity Error\n");
654 if (reason
& MCSR_CPERR
)
655 printk("Cache Parity Error\n");
656 if (reason
& MCSR_EXCP_ERR
)
657 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
658 if (reason
& MCSR_BUS_IRERR
)
659 printk("Bus - Read Bus Error on instruction fetch\n");
660 if (reason
& MCSR_BUS_DRERR
)
661 printk("Bus - Read Bus Error on data load\n");
662 if (reason
& MCSR_BUS_WRERR
)
663 printk("Bus - Write Bus Error on buffered store or cache line push\n");
668 int machine_check_generic(struct pt_regs
*regs
)
670 unsigned long reason
= get_mc_reason(regs
);
672 printk("Machine check in kernel mode.\n");
673 printk("Caused by (from SRR1=%lx): ", reason
);
674 switch (reason
& 0x601F0000) {
676 printk("Machine check signal\n");
678 case 0: /* for 601 */
680 case 0x140000: /* 7450 MSS error and TEA */
681 printk("Transfer error ack signal\n");
684 printk("Data parity error signal\n");
687 printk("Address parity error signal\n");
690 printk("L1 Data Cache error\n");
693 printk("L1 Instruction Cache error\n");
696 printk("L2 data cache parity error\n");
699 printk("Unknown values in msr\n");
703 #endif /* everything else */
705 void machine_check_exception(struct pt_regs
*regs
)
707 enum ctx_state prev_state
= exception_enter();
710 __this_cpu_inc(irq_stat
.mce_exceptions
);
712 /* See if any machine dependent calls. In theory, we would want
713 * to call the CPU first, and call the ppc_md. one if the CPU
714 * one returns a positive number. However there is existing code
715 * that assumes the board gets a first chance, so let's keep it
716 * that way for now and fix things later. --BenH.
718 if (ppc_md
.machine_check_exception
)
719 recover
= ppc_md
.machine_check_exception(regs
);
720 else if (cur_cpu_spec
->machine_check
)
721 recover
= cur_cpu_spec
->machine_check(regs
);
726 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
727 /* the qspan pci read routines can cause machine checks -- Cort
729 * yuck !!! that totally needs to go away ! There are better ways
730 * to deal with that than having a wart in the mcheck handler.
733 bad_page_fault(regs
, regs
->dar
, SIGBUS
);
737 if (debugger_fault_handler(regs
))
740 if (check_io_access(regs
))
743 die("Machine check", regs
, SIGBUS
);
745 /* Must die if the interrupt is not recoverable */
746 if (!(regs
->msr
& MSR_RI
))
747 panic("Unrecoverable Machine check");
750 exception_exit(prev_state
);
753 void SMIException(struct pt_regs
*regs
)
755 die("System Management Interrupt", regs
, SIGABRT
);
758 void handle_hmi_exception(struct pt_regs
*regs
)
760 struct pt_regs
*old_regs
;
762 old_regs
= set_irq_regs(regs
);
765 if (ppc_md
.handle_hmi_exception
)
766 ppc_md
.handle_hmi_exception(regs
);
769 set_irq_regs(old_regs
);
772 void unknown_exception(struct pt_regs
*regs
)
774 enum ctx_state prev_state
= exception_enter();
776 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
777 regs
->nip
, regs
->msr
, regs
->trap
);
779 _exception(SIGTRAP
, regs
, 0, 0);
781 exception_exit(prev_state
);
784 void instruction_breakpoint_exception(struct pt_regs
*regs
)
786 enum ctx_state prev_state
= exception_enter();
788 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
789 5, SIGTRAP
) == NOTIFY_STOP
)
791 if (debugger_iabr_match(regs
))
793 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
796 exception_exit(prev_state
);
799 void RunModeException(struct pt_regs
*regs
)
801 _exception(SIGTRAP
, regs
, 0, 0);
804 void __kprobes
single_step_exception(struct pt_regs
*regs
)
806 enum ctx_state prev_state
= exception_enter();
808 clear_single_step(regs
);
810 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
811 5, SIGTRAP
) == NOTIFY_STOP
)
813 if (debugger_sstep(regs
))
816 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
819 exception_exit(prev_state
);
823 * After we have successfully emulated an instruction, we have to
824 * check if the instruction was being single-stepped, and if so,
825 * pretend we got a single-step exception. This was pointed out
826 * by Kumar Gala. -- paulus
828 static void emulate_single_step(struct pt_regs
*regs
)
830 if (single_stepping(regs
))
831 single_step_exception(regs
);
834 static inline int __parse_fpscr(unsigned long fpscr
)
838 /* Invalid operation */
839 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
843 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
847 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
851 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
855 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
861 static void parse_fpe(struct pt_regs
*regs
)
865 flush_fp_to_thread(current
);
867 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
869 _exception(SIGFPE
, regs
, code
, regs
->nip
);
873 * Illegal instruction emulation support. Originally written to
874 * provide the PVR to user applications using the mfspr rd, PVR.
875 * Return non-zero if we can't emulate, or -EFAULT if the associated
876 * memory access caused an access fault. Return zero on success.
878 * There are a couple of ways to do this, either "decode" the instruction
879 * or directly match lots of bits. In this case, matching lots of
880 * bits is faster and easier.
883 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
885 u8 rT
= (instword
>> 21) & 0x1f;
886 u8 rA
= (instword
>> 16) & 0x1f;
887 u8 NB_RB
= (instword
>> 11) & 0x1f;
892 /* Early out if we are an invalid form of lswx */
893 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
894 if ((rT
== rA
) || (rT
== NB_RB
))
897 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
899 switch (instword
& PPC_INST_STRING_MASK
) {
903 num_bytes
= regs
->xer
& 0x7f;
907 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
913 while (num_bytes
!= 0)
916 u32 shift
= 8 * (3 - (pos
& 0x3));
918 /* if process is 32-bit, clear upper 32 bits of EA */
919 if ((regs
->msr
& MSR_64BIT
) == 0)
922 switch ((instword
& PPC_INST_STRING_MASK
)) {
925 if (get_user(val
, (u8 __user
*)EA
))
927 /* first time updating this reg,
931 regs
->gpr
[rT
] |= val
<< shift
;
935 val
= regs
->gpr
[rT
] >> shift
;
936 if (put_user(val
, (u8 __user
*)EA
))
940 /* move EA to next address */
944 /* manage our position within the register */
955 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
960 ra
= (instword
>> 16) & 0x1f;
961 rs
= (instword
>> 21) & 0x1f;
964 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
965 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
966 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
972 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
974 u8 rT
= (instword
>> 21) & 0x1f;
975 u8 rA
= (instword
>> 16) & 0x1f;
976 u8 rB
= (instword
>> 11) & 0x1f;
977 u8 BC
= (instword
>> 6) & 0x1f;
981 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
982 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
984 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
989 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
990 static inline bool tm_abort_check(struct pt_regs
*regs
, int cause
)
992 /* If we're emulating a load/store in an active transaction, we cannot
993 * emulate it as the kernel operates in transaction suspended context.
994 * We need to abort the transaction. This creates a persistent TM
995 * abort so tell the user what caused it with a new code.
997 if (MSR_TM_TRANSACTIONAL(regs
->msr
)) {
1005 static inline bool tm_abort_check(struct pt_regs
*regs
, int reason
)
1011 static int emulate_instruction(struct pt_regs
*regs
)
1016 if (!user_mode(regs
))
1018 CHECK_FULL_REGS(regs
);
1020 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
1023 /* Emulate the mfspr rD, PVR. */
1024 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
1025 PPC_WARN_EMULATED(mfpvr
, regs
);
1026 rd
= (instword
>> 21) & 0x1f;
1027 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
1031 /* Emulating the dcba insn is just a no-op. */
1032 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
1033 PPC_WARN_EMULATED(dcba
, regs
);
1037 /* Emulate the mcrxr insn. */
1038 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
1039 int shift
= (instword
>> 21) & 0x1c;
1040 unsigned long msk
= 0xf0000000UL
>> shift
;
1042 PPC_WARN_EMULATED(mcrxr
, regs
);
1043 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
1044 regs
->xer
&= ~0xf0000000UL
;
1048 /* Emulate load/store string insn. */
1049 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
1050 if (tm_abort_check(regs
,
1051 TM_CAUSE_EMULATE
| TM_CAUSE_PERSISTENT
))
1053 PPC_WARN_EMULATED(string
, regs
);
1054 return emulate_string_inst(regs
, instword
);
1057 /* Emulate the popcntb (Population Count Bytes) instruction. */
1058 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
1059 PPC_WARN_EMULATED(popcntb
, regs
);
1060 return emulate_popcntb_inst(regs
, instword
);
1063 /* Emulate isel (Integer Select) instruction */
1064 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
1065 PPC_WARN_EMULATED(isel
, regs
);
1066 return emulate_isel(regs
, instword
);
1069 /* Emulate sync instruction variants */
1070 if ((instword
& PPC_INST_SYNC_MASK
) == PPC_INST_SYNC
) {
1071 PPC_WARN_EMULATED(sync
, regs
);
1072 asm volatile("sync");
1077 /* Emulate the mfspr rD, DSCR. */
1078 if ((((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
) ==
1079 PPC_INST_MFSPR_DSCR_USER
) ||
1080 ((instword
& PPC_INST_MFSPR_DSCR_MASK
) ==
1081 PPC_INST_MFSPR_DSCR
)) &&
1082 cpu_has_feature(CPU_FTR_DSCR
)) {
1083 PPC_WARN_EMULATED(mfdscr
, regs
);
1084 rd
= (instword
>> 21) & 0x1f;
1085 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
1088 /* Emulate the mtspr DSCR, rD. */
1089 if ((((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
) ==
1090 PPC_INST_MTSPR_DSCR_USER
) ||
1091 ((instword
& PPC_INST_MTSPR_DSCR_MASK
) ==
1092 PPC_INST_MTSPR_DSCR
)) &&
1093 cpu_has_feature(CPU_FTR_DSCR
)) {
1094 PPC_WARN_EMULATED(mtdscr
, regs
);
1095 rd
= (instword
>> 21) & 0x1f;
1096 current
->thread
.dscr
= regs
->gpr
[rd
];
1097 current
->thread
.dscr_inherit
= 1;
1098 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
1106 int is_valid_bugaddr(unsigned long addr
)
1108 return is_kernel_addr(addr
);
1111 #ifdef CONFIG_MATH_EMULATION
1112 static int emulate_math(struct pt_regs
*regs
)
1115 extern int do_mathemu(struct pt_regs
*regs
);
1117 ret
= do_mathemu(regs
);
1119 PPC_WARN_EMULATED(math
, regs
);
1123 emulate_single_step(regs
);
1127 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1128 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1132 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1139 static inline int emulate_math(struct pt_regs
*regs
) { return -1; }
1142 void __kprobes
program_check_exception(struct pt_regs
*regs
)
1144 enum ctx_state prev_state
= exception_enter();
1145 unsigned int reason
= get_reason(regs
);
1147 /* We can now get here via a FP Unavailable exception if the core
1148 * has no FPU, in that case the reason flags will be 0 */
1150 if (reason
& REASON_FP
) {
1151 /* IEEE FP exception */
1155 if (reason
& REASON_TRAP
) {
1156 unsigned long bugaddr
;
1157 /* Debugger is first in line to stop recursive faults in
1158 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1159 if (debugger_bpt(regs
))
1162 /* trap exception */
1163 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1167 bugaddr
= regs
->nip
;
1169 * Fixup bugaddr for BUG_ON() in real mode
1171 if (!is_kernel_addr(bugaddr
) && !(regs
->msr
& MSR_IR
))
1172 bugaddr
+= PAGE_OFFSET
;
1174 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1175 report_bug(bugaddr
, regs
) == BUG_TRAP_TYPE_WARN
) {
1179 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1182 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1183 if (reason
& REASON_TM
) {
1184 /* This is a TM "Bad Thing Exception" program check.
1186 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1187 * transition in TM states.
1188 * - A trechkpt is attempted when transactional.
1189 * - A treclaim is attempted when non transactional.
1190 * - A tend is illegally attempted.
1191 * - writing a TM SPR when transactional.
1193 if (!user_mode(regs
) &&
1194 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1198 /* If usermode caused this, it's done something illegal and
1199 * gets a SIGILL slap on the wrist. We call it an illegal
1200 * operand to distinguish from the instruction just being bad
1201 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1202 * illegal /placement/ of a valid instruction.
1204 if (user_mode(regs
)) {
1205 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1208 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1209 "at %lx (msr 0x%x)\n", regs
->nip
, reason
);
1210 die("Unrecoverable exception", regs
, SIGABRT
);
1216 * If we took the program check in the kernel skip down to sending a
1217 * SIGILL. The subsequent cases all relate to emulating instructions
1218 * which we should only do for userspace. We also do not want to enable
1219 * interrupts for kernel faults because that might lead to further
1220 * faults, and loose the context of the original exception.
1222 if (!user_mode(regs
))
1225 /* We restore the interrupt state now */
1226 if (!arch_irq_disabled_regs(regs
))
1229 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1230 * but there seems to be a hardware bug on the 405GP (RevD)
1231 * that means ESR is sometimes set incorrectly - either to
1232 * ESR_DST (!?) or 0. In the process of chasing this with the
1233 * hardware people - not sure if it can happen on any illegal
1234 * instruction or only on FP instructions, whether there is a
1235 * pattern to occurrences etc. -dgibson 31/Mar/2003
1237 if (!emulate_math(regs
))
1240 /* Try to emulate it if we should. */
1241 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1242 switch (emulate_instruction(regs
)) {
1245 emulate_single_step(regs
);
1248 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1254 if (reason
& REASON_PRIVILEGED
)
1255 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1257 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1260 exception_exit(prev_state
);
1264 * This occurs when running in hypervisor mode on POWER6 or later
1265 * and an illegal instruction is encountered.
1267 void __kprobes
emulation_assist_interrupt(struct pt_regs
*regs
)
1269 regs
->msr
|= REASON_ILLEGAL
;
1270 program_check_exception(regs
);
1273 void alignment_exception(struct pt_regs
*regs
)
1275 enum ctx_state prev_state
= exception_enter();
1276 int sig
, code
, fixed
= 0;
1278 /* We restore the interrupt state now */
1279 if (!arch_irq_disabled_regs(regs
))
1282 if (tm_abort_check(regs
, TM_CAUSE_ALIGNMENT
| TM_CAUSE_PERSISTENT
))
1285 /* we don't implement logging of alignment exceptions */
1286 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1287 fixed
= fix_alignment(regs
);
1290 regs
->nip
+= 4; /* skip over emulated instruction */
1291 emulate_single_step(regs
);
1295 /* Operand address was bad */
1296 if (fixed
== -EFAULT
) {
1303 if (user_mode(regs
))
1304 _exception(sig
, regs
, code
, regs
->dar
);
1306 bad_page_fault(regs
, regs
->dar
, sig
);
1309 exception_exit(prev_state
);
1312 void StackOverflow(struct pt_regs
*regs
)
1314 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
1315 current
, regs
->gpr
[1]);
1318 panic("kernel stack overflow");
1321 void nonrecoverable_exception(struct pt_regs
*regs
)
1323 printk(KERN_ERR
"Non-recoverable exception at PC=%lx MSR=%lx\n",
1324 regs
->nip
, regs
->msr
);
1326 die("nonrecoverable exception", regs
, SIGKILL
);
1329 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1331 enum ctx_state prev_state
= exception_enter();
1333 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1334 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1335 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1337 exception_exit(prev_state
);
1340 void altivec_unavailable_exception(struct pt_regs
*regs
)
1342 enum ctx_state prev_state
= exception_enter();
1344 if (user_mode(regs
)) {
1345 /* A user program has executed an altivec instruction,
1346 but this kernel doesn't support altivec. */
1347 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1351 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1352 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1353 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1356 exception_exit(prev_state
);
1359 void vsx_unavailable_exception(struct pt_regs
*regs
)
1361 if (user_mode(regs
)) {
1362 /* A user program has executed an vsx instruction,
1363 but this kernel doesn't support vsx. */
1364 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1368 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1369 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1370 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1374 void facility_unavailable_exception(struct pt_regs
*regs
)
1376 static char *facility_strings
[] = {
1377 [FSCR_FP_LG
] = "FPU",
1378 [FSCR_VECVSX_LG
] = "VMX/VSX",
1379 [FSCR_DSCR_LG
] = "DSCR",
1380 [FSCR_PM_LG
] = "PMU SPRs",
1381 [FSCR_BHRB_LG
] = "BHRB",
1382 [FSCR_TM_LG
] = "TM",
1383 [FSCR_EBB_LG
] = "EBB",
1384 [FSCR_TAR_LG
] = "TAR",
1385 [FSCR_LM_LG
] = "LM",
1387 char *facility
= "unknown";
1393 hv
= (regs
->trap
== 0xf80);
1395 value
= mfspr(SPRN_HFSCR
);
1397 value
= mfspr(SPRN_FSCR
);
1399 status
= value
>> 56;
1400 if (status
== FSCR_DSCR_LG
) {
1402 * User is accessing the DSCR register using the problem
1403 * state only SPR number (0x03) either through a mfspr or
1404 * a mtspr instruction. If it is a write attempt through
1405 * a mtspr, then we set the inherit bit. This also allows
1406 * the user to write or read the register directly in the
1407 * future by setting via the FSCR DSCR bit. But in case it
1408 * is a read DSCR attempt through a mfspr instruction, we
1409 * just emulate the instruction instead. This code path will
1410 * always emulate all the mfspr instructions till the user
1411 * has attempted at least one mtspr instruction. This way it
1412 * preserves the same behaviour when the user is accessing
1413 * the DSCR through privilege level only SPR number (0x11)
1414 * which is emulated through illegal instruction exception.
1415 * We always leave HFSCR DSCR set.
1417 if (get_user(instword
, (u32 __user
*)(regs
->nip
))) {
1418 pr_err("Failed to fetch the user instruction\n");
1422 /* Write into DSCR (mtspr 0x03, RS) */
1423 if ((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
)
1424 == PPC_INST_MTSPR_DSCR_USER
) {
1425 rd
= (instword
>> 21) & 0x1f;
1426 current
->thread
.dscr
= regs
->gpr
[rd
];
1427 current
->thread
.dscr_inherit
= 1;
1428 current
->thread
.fscr
|= FSCR_DSCR
;
1429 mtspr(SPRN_FSCR
, current
->thread
.fscr
);
1432 /* Read from DSCR (mfspr RT, 0x03) */
1433 if ((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
)
1434 == PPC_INST_MFSPR_DSCR_USER
) {
1435 if (emulate_instruction(regs
)) {
1436 pr_err("DSCR based mfspr emulation failed\n");
1440 emulate_single_step(regs
);
1443 } else if ((status
== FSCR_LM_LG
) && cpu_has_feature(CPU_FTR_ARCH_300
)) {
1445 * This process has touched LM, so turn it on forever
1448 current
->thread
.fscr
|= FSCR_LM
;
1449 mtspr(SPRN_FSCR
, current
->thread
.fscr
);
1453 if ((status
< ARRAY_SIZE(facility_strings
)) &&
1454 facility_strings
[status
])
1455 facility
= facility_strings
[status
];
1457 /* We restore the interrupt state now */
1458 if (!arch_irq_disabled_regs(regs
))
1462 "%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
1463 hv
? "Hypervisor " : "", facility
, regs
->nip
, regs
->msr
);
1465 if (user_mode(regs
)) {
1466 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1470 die("Unexpected facility unavailable exception", regs
, SIGABRT
);
1474 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1476 void fp_unavailable_tm(struct pt_regs
*regs
)
1478 /* Note: This does not handle any kind of FP laziness. */
1480 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1481 regs
->nip
, regs
->msr
);
1483 /* We can only have got here if the task started using FP after
1484 * beginning the transaction. So, the transactional regs are just a
1485 * copy of the checkpointed ones. But, we still need to recheckpoint
1486 * as we're enabling FP for the process; it will return, abort the
1487 * transaction, and probably retry but now with FP enabled. So the
1488 * checkpointed FP registers need to be loaded.
1490 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1491 /* Reclaim didn't save out any FPRs to transact_fprs. */
1493 /* Enable FP for the task: */
1494 regs
->msr
|= (MSR_FP
| current
->thread
.fpexc_mode
);
1496 /* This loads and recheckpoints the FP registers from
1497 * thread.fpr[]. They will remain in registers after the
1498 * checkpoint so we don't need to reload them after.
1499 * If VMX is in use, the VRs now hold checkpointed values,
1500 * so we don't want to load the VRs from the thread_struct.
1502 tm_recheckpoint(¤t
->thread
, MSR_FP
);
1504 /* If VMX is in use, get the transactional values back */
1505 if (regs
->msr
& MSR_VEC
) {
1506 do_load_up_transact_altivec(¤t
->thread
);
1507 /* At this point all the VSX state is loaded, so enable it */
1508 regs
->msr
|= MSR_VSX
;
1512 void altivec_unavailable_tm(struct pt_regs
*regs
)
1514 /* See the comments in fp_unavailable_tm(). This function operates
1518 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1520 regs
->nip
, regs
->msr
);
1521 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1522 regs
->msr
|= MSR_VEC
;
1523 tm_recheckpoint(¤t
->thread
, MSR_VEC
);
1524 current
->thread
.used_vr
= 1;
1526 if (regs
->msr
& MSR_FP
) {
1527 do_load_up_transact_fpu(¤t
->thread
);
1528 regs
->msr
|= MSR_VSX
;
1532 void vsx_unavailable_tm(struct pt_regs
*regs
)
1534 unsigned long orig_msr
= regs
->msr
;
1536 /* See the comments in fp_unavailable_tm(). This works similarly,
1537 * though we're loading both FP and VEC registers in here.
1539 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1540 * regs. Either way, set MSR_VSX.
1543 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1545 regs
->nip
, regs
->msr
);
1547 current
->thread
.used_vsr
= 1;
1549 /* If FP and VMX are already loaded, we have all the state we need */
1550 if ((orig_msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
)) {
1551 regs
->msr
|= MSR_VSX
;
1555 /* This reclaims FP and/or VR regs if they're already enabled */
1556 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1558 regs
->msr
|= MSR_VEC
| MSR_FP
| current
->thread
.fpexc_mode
|
1561 /* This loads & recheckpoints FP and VRs; but we have
1562 * to be sure not to overwrite previously-valid state.
1564 tm_recheckpoint(¤t
->thread
, regs
->msr
& ~orig_msr
);
1566 if (orig_msr
& MSR_FP
)
1567 do_load_up_transact_fpu(¤t
->thread
);
1568 if (orig_msr
& MSR_VEC
)
1569 do_load_up_transact_altivec(¤t
->thread
);
1571 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1573 void performance_monitor_exception(struct pt_regs
*regs
)
1575 __this_cpu_inc(irq_stat
.pmu_irqs
);
1581 void SoftwareEmulation(struct pt_regs
*regs
)
1583 CHECK_FULL_REGS(regs
);
1585 if (!user_mode(regs
)) {
1587 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1591 if (!emulate_math(regs
))
1594 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1596 #endif /* CONFIG_8xx */
1598 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1599 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1603 * Determine the cause of the debug event, clear the
1604 * event flags and send a trap to the handler. Torez
1606 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1607 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1608 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1609 current
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
1611 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
, TRAP_HWBKPT
,
1614 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1615 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1616 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
, TRAP_HWBKPT
,
1619 } else if (debug_status
& DBSR_IAC1
) {
1620 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
1621 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1622 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
, TRAP_HWBKPT
,
1625 } else if (debug_status
& DBSR_IAC2
) {
1626 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
1627 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
, TRAP_HWBKPT
,
1630 } else if (debug_status
& DBSR_IAC3
) {
1631 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
1632 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1633 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
, TRAP_HWBKPT
,
1636 } else if (debug_status
& DBSR_IAC4
) {
1637 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
1638 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
, TRAP_HWBKPT
,
1643 * At the point this routine was called, the MSR(DE) was turned off.
1644 * Check all other debug flags and see if that bit needs to be turned
1647 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1648 current
->thread
.debug
.dbcr1
))
1649 regs
->msr
|= MSR_DE
;
1651 /* Make sure the IDM flag is off */
1652 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1655 mtspr(SPRN_DBCR0
, current
->thread
.debug
.dbcr0
);
1658 void __kprobes
DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1660 current
->thread
.debug
.dbsr
= debug_status
;
1662 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1663 * on server, it stops on the target of the branch. In order to simulate
1664 * the server behaviour, we thus restart right away with a single step
1665 * instead of stopping here when hitting a BT
1667 if (debug_status
& DBSR_BT
) {
1668 regs
->msr
&= ~MSR_DE
;
1671 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1672 /* Clear the BT event */
1673 mtspr(SPRN_DBSR
, DBSR_BT
);
1675 /* Do the single step trick only when coming from userspace */
1676 if (user_mode(regs
)) {
1677 current
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
1678 current
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1679 regs
->msr
|= MSR_DE
;
1683 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1684 5, SIGTRAP
) == NOTIFY_STOP
) {
1687 if (debugger_sstep(regs
))
1689 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1690 regs
->msr
&= ~MSR_DE
;
1692 /* Disable instruction completion */
1693 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1694 /* Clear the instruction completion event */
1695 mtspr(SPRN_DBSR
, DBSR_IC
);
1697 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1698 5, SIGTRAP
) == NOTIFY_STOP
) {
1702 if (debugger_sstep(regs
))
1705 if (user_mode(regs
)) {
1706 current
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
1707 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1708 current
->thread
.debug
.dbcr1
))
1709 regs
->msr
|= MSR_DE
;
1711 /* Make sure the IDM bit is off */
1712 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1715 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1717 handle_debug(regs
, debug_status
);
1719 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1721 #if !defined(CONFIG_TAU_INT)
1722 void TAUException(struct pt_regs
*regs
)
1724 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1725 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
1727 #endif /* CONFIG_INT_TAU */
1729 #ifdef CONFIG_ALTIVEC
1730 void altivec_assist_exception(struct pt_regs
*regs
)
1734 if (!user_mode(regs
)) {
1735 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
1736 " at %lx\n", regs
->nip
);
1737 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
1740 flush_altivec_to_thread(current
);
1742 PPC_WARN_EMULATED(altivec
, regs
);
1743 err
= emulate_altivec(regs
);
1745 regs
->nip
+= 4; /* skip emulated instruction */
1746 emulate_single_step(regs
);
1750 if (err
== -EFAULT
) {
1751 /* got an error reading the instruction */
1752 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1754 /* didn't recognize the instruction */
1755 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1756 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
1757 "in %s at %lx\n", current
->comm
, regs
->nip
);
1758 current
->thread
.vr_state
.vscr
.u
[3] |= 0x10000;
1761 #endif /* CONFIG_ALTIVEC */
1763 #ifdef CONFIG_FSL_BOOKE
1764 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
1765 unsigned long error_code
)
1767 /* We treat cache locking instructions from the user
1768 * as priv ops, in the future we could try to do
1771 if (error_code
& (ESR_DLK
|ESR_ILK
))
1772 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1775 #endif /* CONFIG_FSL_BOOKE */
1778 void SPEFloatingPointException(struct pt_regs
*regs
)
1780 extern int do_spe_mathemu(struct pt_regs
*regs
);
1781 unsigned long spefscr
;
1786 flush_spe_to_thread(current
);
1788 spefscr
= current
->thread
.spefscr
;
1789 fpexc_mode
= current
->thread
.fpexc_mode
;
1791 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
1794 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
1797 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
1799 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
1802 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
1805 err
= do_spe_mathemu(regs
);
1807 regs
->nip
+= 4; /* skip emulated instruction */
1808 emulate_single_step(regs
);
1812 if (err
== -EFAULT
) {
1813 /* got an error reading the instruction */
1814 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1815 } else if (err
== -EINVAL
) {
1816 /* didn't recognize the instruction */
1817 printk(KERN_ERR
"unrecognized spe instruction "
1818 "in %s at %lx\n", current
->comm
, regs
->nip
);
1820 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1826 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
1828 extern int speround_handler(struct pt_regs
*regs
);
1832 if (regs
->msr
& MSR_SPE
)
1833 giveup_spe(current
);
1837 err
= speround_handler(regs
);
1839 regs
->nip
+= 4; /* skip emulated instruction */
1840 emulate_single_step(regs
);
1844 if (err
== -EFAULT
) {
1845 /* got an error reading the instruction */
1846 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1847 } else if (err
== -EINVAL
) {
1848 /* didn't recognize the instruction */
1849 printk(KERN_ERR
"unrecognized spe instruction "
1850 "in %s at %lx\n", current
->comm
, regs
->nip
);
1852 _exception(SIGFPE
, regs
, 0, regs
->nip
);
1859 * We enter here if we get an unrecoverable exception, that is, one
1860 * that happened at a point where the RI (recoverable interrupt) bit
1861 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1862 * we therefore lost state by taking this exception.
1864 void unrecoverable_exception(struct pt_regs
*regs
)
1866 printk(KERN_EMERG
"Unrecoverable exception %lx at %lx\n",
1867 regs
->trap
, regs
->nip
);
1868 die("Unrecoverable exception", regs
, SIGABRT
);
1871 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1873 * Default handler for a Watchdog exception,
1874 * spins until a reboot occurs
1876 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
1878 /* Generic WatchdogHandler, implement your own */
1879 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
1883 void WatchdogException(struct pt_regs
*regs
)
1885 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
1886 WatchdogHandler(regs
);
1891 * We enter here if we discover during exception entry that we are
1892 * running in supervisor mode with a userspace value in the stack pointer.
1894 void kernel_bad_stack(struct pt_regs
*regs
)
1896 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
1897 regs
->gpr
[1], regs
->nip
);
1898 die("Bad kernel stack pointer", regs
, SIGABRT
);
1901 void __init
trap_init(void)
1906 #ifdef CONFIG_PPC_EMULATED_STATS
1908 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1910 struct ppc_emulated ppc_emulated
= {
1911 #ifdef CONFIG_ALTIVEC
1912 WARN_EMULATED_SETUP(altivec
),
1914 WARN_EMULATED_SETUP(dcba
),
1915 WARN_EMULATED_SETUP(dcbz
),
1916 WARN_EMULATED_SETUP(fp_pair
),
1917 WARN_EMULATED_SETUP(isel
),
1918 WARN_EMULATED_SETUP(mcrxr
),
1919 WARN_EMULATED_SETUP(mfpvr
),
1920 WARN_EMULATED_SETUP(multiple
),
1921 WARN_EMULATED_SETUP(popcntb
),
1922 WARN_EMULATED_SETUP(spe
),
1923 WARN_EMULATED_SETUP(string
),
1924 WARN_EMULATED_SETUP(sync
),
1925 WARN_EMULATED_SETUP(unaligned
),
1926 #ifdef CONFIG_MATH_EMULATION
1927 WARN_EMULATED_SETUP(math
),
1930 WARN_EMULATED_SETUP(vsx
),
1933 WARN_EMULATED_SETUP(mfdscr
),
1934 WARN_EMULATED_SETUP(mtdscr
),
1935 WARN_EMULATED_SETUP(lq_stq
),
1939 u32 ppc_warn_emulated
;
1941 void ppc_warn_emulated_print(const char *type
)
1943 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
1947 static int __init
ppc_warn_emulated_init(void)
1949 struct dentry
*dir
, *d
;
1951 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
1953 if (!powerpc_debugfs_root
)
1956 dir
= debugfs_create_dir("emulated_instructions",
1957 powerpc_debugfs_root
);
1961 d
= debugfs_create_u32("do_warn", S_IRUGO
| S_IWUSR
, dir
,
1962 &ppc_warn_emulated
);
1966 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
1967 d
= debugfs_create_u32(entries
[i
].name
, S_IRUGO
| S_IWUSR
, dir
,
1968 (u32
*)&entries
[i
].val
.counter
);
1976 debugfs_remove_recursive(dir
);
1980 device_initcall(ppc_warn_emulated_init
);
1982 #endif /* CONFIG_PPC_EMULATED_STATS */