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powerpc: Don't force MSR_RI in machine_check_exception
[deliverable/linux.git] / arch / powerpc / kernel / traps.c
1 /*
2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
12 */
13
14 /*
15 * This file handles the architecture-dependent parts of hardware exceptions
16 */
17
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37
38 #include <asm/emulated_ops.h>
39 #include <asm/pgtable.h>
40 #include <asm/uaccess.h>
41 #include <asm/system.h>
42 #include <asm/io.h>
43 #include <asm/machdep.h>
44 #include <asm/rtas.h>
45 #include <asm/pmc.h>
46 #ifdef CONFIG_PPC32
47 #include <asm/reg.h>
48 #endif
49 #ifdef CONFIG_PMAC_BACKLIGHT
50 #include <asm/backlight.h>
51 #endif
52 #ifdef CONFIG_PPC64
53 #include <asm/firmware.h>
54 #include <asm/processor.h>
55 #endif
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
58
59 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
60 int (*__debugger)(struct pt_regs *regs) __read_mostly;
61 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
62 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
63 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
64 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
65 int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly;
66 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
67
68 EXPORT_SYMBOL(__debugger);
69 EXPORT_SYMBOL(__debugger_ipi);
70 EXPORT_SYMBOL(__debugger_bpt);
71 EXPORT_SYMBOL(__debugger_sstep);
72 EXPORT_SYMBOL(__debugger_iabr_match);
73 EXPORT_SYMBOL(__debugger_dabr_match);
74 EXPORT_SYMBOL(__debugger_fault_handler);
75 #endif
76
77 /*
78 * Trap & Exception support
79 */
80
81 #ifdef CONFIG_PMAC_BACKLIGHT
82 static void pmac_backlight_unblank(void)
83 {
84 mutex_lock(&pmac_backlight_mutex);
85 if (pmac_backlight) {
86 struct backlight_properties *props;
87
88 props = &pmac_backlight->props;
89 props->brightness = props->max_brightness;
90 props->power = FB_BLANK_UNBLANK;
91 backlight_update_status(pmac_backlight);
92 }
93 mutex_unlock(&pmac_backlight_mutex);
94 }
95 #else
96 static inline void pmac_backlight_unblank(void) { }
97 #endif
98
99 int die(const char *str, struct pt_regs *regs, long err)
100 {
101 static struct {
102 raw_spinlock_t lock;
103 u32 lock_owner;
104 int lock_owner_depth;
105 } die = {
106 .lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock),
107 .lock_owner = -1,
108 .lock_owner_depth = 0
109 };
110 static int die_counter;
111 unsigned long flags;
112
113 if (debugger(regs))
114 return 1;
115
116 oops_enter();
117
118 if (die.lock_owner != raw_smp_processor_id()) {
119 console_verbose();
120 raw_spin_lock_irqsave(&die.lock, flags);
121 die.lock_owner = smp_processor_id();
122 die.lock_owner_depth = 0;
123 bust_spinlocks(1);
124 if (machine_is(powermac))
125 pmac_backlight_unblank();
126 } else {
127 local_save_flags(flags);
128 }
129
130 if (++die.lock_owner_depth < 3) {
131 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
132 #ifdef CONFIG_PREEMPT
133 printk("PREEMPT ");
134 #endif
135 #ifdef CONFIG_SMP
136 printk("SMP NR_CPUS=%d ", NR_CPUS);
137 #endif
138 #ifdef CONFIG_DEBUG_PAGEALLOC
139 printk("DEBUG_PAGEALLOC ");
140 #endif
141 #ifdef CONFIG_NUMA
142 printk("NUMA ");
143 #endif
144 printk("%s\n", ppc_md.name ? ppc_md.name : "");
145
146 sysfs_printk_last_file();
147 if (notify_die(DIE_OOPS, str, regs, err, 255,
148 SIGSEGV) == NOTIFY_STOP)
149 return 1;
150
151 print_modules();
152 show_regs(regs);
153 } else {
154 printk("Recursive die() failure, output suppressed\n");
155 }
156
157 bust_spinlocks(0);
158 die.lock_owner = -1;
159 add_taint(TAINT_DIE);
160 raw_spin_unlock_irqrestore(&die.lock, flags);
161
162 if (kexec_should_crash(current) ||
163 kexec_sr_activated(smp_processor_id()))
164 crash_kexec(regs);
165 crash_kexec_secondary(regs);
166
167 if (in_interrupt())
168 panic("Fatal exception in interrupt");
169
170 if (panic_on_oops)
171 panic("Fatal exception");
172
173 oops_exit();
174 do_exit(err);
175
176 return 0;
177 }
178
179 void user_single_step_siginfo(struct task_struct *tsk,
180 struct pt_regs *regs, siginfo_t *info)
181 {
182 memset(info, 0, sizeof(*info));
183 info->si_signo = SIGTRAP;
184 info->si_code = TRAP_TRACE;
185 info->si_addr = (void __user *)regs->nip;
186 }
187
188 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
189 {
190 siginfo_t info;
191 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
192 "at %08lx nip %08lx lr %08lx code %x\n";
193 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
194 "at %016lx nip %016lx lr %016lx code %x\n";
195
196 if (!user_mode(regs)) {
197 if (die("Exception in kernel mode", regs, signr))
198 return;
199 } else if (show_unhandled_signals &&
200 unhandled_signal(current, signr) &&
201 printk_ratelimit()) {
202 printk(regs->msr & MSR_SF ? fmt64 : fmt32,
203 current->comm, current->pid, signr,
204 addr, regs->nip, regs->link, code);
205 }
206
207 memset(&info, 0, sizeof(info));
208 info.si_signo = signr;
209 info.si_code = code;
210 info.si_addr = (void __user *) addr;
211 force_sig_info(signr, &info, current);
212 }
213
214 #ifdef CONFIG_PPC64
215 void system_reset_exception(struct pt_regs *regs)
216 {
217 /* See if any machine dependent calls */
218 if (ppc_md.system_reset_exception) {
219 if (ppc_md.system_reset_exception(regs))
220 return;
221 }
222
223 #ifdef CONFIG_KEXEC
224 cpu_set(smp_processor_id(), cpus_in_sr);
225 #endif
226
227 die("System Reset", regs, SIGABRT);
228
229 /*
230 * Some CPUs when released from the debugger will execute this path.
231 * These CPUs entered the debugger via a soft-reset. If the CPU was
232 * hung before entering the debugger it will return to the hung
233 * state when exiting this function. This causes a problem in
234 * kdump since the hung CPU(s) will not respond to the IPI sent
235 * from kdump. To prevent the problem we call crash_kexec_secondary()
236 * here. If a kdump had not been initiated or we exit the debugger
237 * with the "exit and recover" command (x) crash_kexec_secondary()
238 * will return after 5ms and the CPU returns to its previous state.
239 */
240 crash_kexec_secondary(regs);
241
242 /* Must die if the interrupt is not recoverable */
243 if (!(regs->msr & MSR_RI))
244 panic("Unrecoverable System Reset");
245
246 /* What should we do here? We could issue a shutdown or hard reset. */
247 }
248 #endif
249
250 /*
251 * I/O accesses can cause machine checks on powermacs.
252 * Check if the NIP corresponds to the address of a sync
253 * instruction for which there is an entry in the exception
254 * table.
255 * Note that the 601 only takes a machine check on TEA
256 * (transfer error ack) signal assertion, and does not
257 * set any of the top 16 bits of SRR1.
258 * -- paulus.
259 */
260 static inline int check_io_access(struct pt_regs *regs)
261 {
262 #ifdef CONFIG_PPC32
263 unsigned long msr = regs->msr;
264 const struct exception_table_entry *entry;
265 unsigned int *nip = (unsigned int *)regs->nip;
266
267 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
268 && (entry = search_exception_tables(regs->nip)) != NULL) {
269 /*
270 * Check that it's a sync instruction, or somewhere
271 * in the twi; isync; nop sequence that inb/inw/inl uses.
272 * As the address is in the exception table
273 * we should be able to read the instr there.
274 * For the debug message, we look at the preceding
275 * load or store.
276 */
277 if (*nip == 0x60000000) /* nop */
278 nip -= 2;
279 else if (*nip == 0x4c00012c) /* isync */
280 --nip;
281 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
282 /* sync or twi */
283 unsigned int rb;
284
285 --nip;
286 rb = (*nip >> 11) & 0x1f;
287 printk(KERN_DEBUG "%s bad port %lx at %p\n",
288 (*nip & 0x100)? "OUT to": "IN from",
289 regs->gpr[rb] - _IO_BASE, nip);
290 regs->msr |= MSR_RI;
291 regs->nip = entry->fixup;
292 return 1;
293 }
294 }
295 #endif /* CONFIG_PPC32 */
296 return 0;
297 }
298
299 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
300 /* On 4xx, the reason for the machine check or program exception
301 is in the ESR. */
302 #define get_reason(regs) ((regs)->dsisr)
303 #ifndef CONFIG_FSL_BOOKE
304 #define get_mc_reason(regs) ((regs)->dsisr)
305 #else
306 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
307 #endif
308 #define REASON_FP ESR_FP
309 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
310 #define REASON_PRIVILEGED ESR_PPR
311 #define REASON_TRAP ESR_PTR
312
313 /* single-step stuff */
314 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
315 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
316
317 #else
318 /* On non-4xx, the reason for the machine check or program
319 exception is in the MSR. */
320 #define get_reason(regs) ((regs)->msr)
321 #define get_mc_reason(regs) ((regs)->msr)
322 #define REASON_FP 0x100000
323 #define REASON_ILLEGAL 0x80000
324 #define REASON_PRIVILEGED 0x40000
325 #define REASON_TRAP 0x20000
326
327 #define single_stepping(regs) ((regs)->msr & MSR_SE)
328 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
329 #endif
330
331 #if defined(CONFIG_4xx)
332 int machine_check_4xx(struct pt_regs *regs)
333 {
334 unsigned long reason = get_mc_reason(regs);
335
336 if (reason & ESR_IMCP) {
337 printk("Instruction");
338 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
339 } else
340 printk("Data");
341 printk(" machine check in kernel mode.\n");
342
343 return 0;
344 }
345
346 int machine_check_440A(struct pt_regs *regs)
347 {
348 unsigned long reason = get_mc_reason(regs);
349
350 printk("Machine check in kernel mode.\n");
351 if (reason & ESR_IMCP){
352 printk("Instruction Synchronous Machine Check exception\n");
353 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
354 }
355 else {
356 u32 mcsr = mfspr(SPRN_MCSR);
357 if (mcsr & MCSR_IB)
358 printk("Instruction Read PLB Error\n");
359 if (mcsr & MCSR_DRB)
360 printk("Data Read PLB Error\n");
361 if (mcsr & MCSR_DWB)
362 printk("Data Write PLB Error\n");
363 if (mcsr & MCSR_TLBP)
364 printk("TLB Parity Error\n");
365 if (mcsr & MCSR_ICP){
366 flush_instruction_cache();
367 printk("I-Cache Parity Error\n");
368 }
369 if (mcsr & MCSR_DCSP)
370 printk("D-Cache Search Parity Error\n");
371 if (mcsr & MCSR_DCFP)
372 printk("D-Cache Flush Parity Error\n");
373 if (mcsr & MCSR_IMPE)
374 printk("Machine Check exception is imprecise\n");
375
376 /* Clear MCSR */
377 mtspr(SPRN_MCSR, mcsr);
378 }
379 return 0;
380 }
381
382 int machine_check_47x(struct pt_regs *regs)
383 {
384 unsigned long reason = get_mc_reason(regs);
385 u32 mcsr;
386
387 printk(KERN_ERR "Machine check in kernel mode.\n");
388 if (reason & ESR_IMCP) {
389 printk(KERN_ERR
390 "Instruction Synchronous Machine Check exception\n");
391 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
392 return 0;
393 }
394 mcsr = mfspr(SPRN_MCSR);
395 if (mcsr & MCSR_IB)
396 printk(KERN_ERR "Instruction Read PLB Error\n");
397 if (mcsr & MCSR_DRB)
398 printk(KERN_ERR "Data Read PLB Error\n");
399 if (mcsr & MCSR_DWB)
400 printk(KERN_ERR "Data Write PLB Error\n");
401 if (mcsr & MCSR_TLBP)
402 printk(KERN_ERR "TLB Parity Error\n");
403 if (mcsr & MCSR_ICP) {
404 flush_instruction_cache();
405 printk(KERN_ERR "I-Cache Parity Error\n");
406 }
407 if (mcsr & MCSR_DCSP)
408 printk(KERN_ERR "D-Cache Search Parity Error\n");
409 if (mcsr & PPC47x_MCSR_GPR)
410 printk(KERN_ERR "GPR Parity Error\n");
411 if (mcsr & PPC47x_MCSR_FPR)
412 printk(KERN_ERR "FPR Parity Error\n");
413 if (mcsr & PPC47x_MCSR_IPR)
414 printk(KERN_ERR "Machine Check exception is imprecise\n");
415
416 /* Clear MCSR */
417 mtspr(SPRN_MCSR, mcsr);
418
419 return 0;
420 }
421 #elif defined(CONFIG_E500)
422 int machine_check_e500mc(struct pt_regs *regs)
423 {
424 unsigned long mcsr = mfspr(SPRN_MCSR);
425 unsigned long reason = mcsr;
426 int recoverable = 1;
427
428 printk("Machine check in kernel mode.\n");
429 printk("Caused by (from MCSR=%lx): ", reason);
430
431 if (reason & MCSR_MCP)
432 printk("Machine Check Signal\n");
433
434 if (reason & MCSR_ICPERR) {
435 printk("Instruction Cache Parity Error\n");
436
437 /*
438 * This is recoverable by invalidating the i-cache.
439 */
440 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
441 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
442 ;
443
444 /*
445 * This will generally be accompanied by an instruction
446 * fetch error report -- only treat MCSR_IF as fatal
447 * if it wasn't due to an L1 parity error.
448 */
449 reason &= ~MCSR_IF;
450 }
451
452 if (reason & MCSR_DCPERR_MC) {
453 printk("Data Cache Parity Error\n");
454 recoverable = 0;
455 }
456
457 if (reason & MCSR_L2MMU_MHIT) {
458 printk("Hit on multiple TLB entries\n");
459 recoverable = 0;
460 }
461
462 if (reason & MCSR_NMI)
463 printk("Non-maskable interrupt\n");
464
465 if (reason & MCSR_IF) {
466 printk("Instruction Fetch Error Report\n");
467 recoverable = 0;
468 }
469
470 if (reason & MCSR_LD) {
471 printk("Load Error Report\n");
472 recoverable = 0;
473 }
474
475 if (reason & MCSR_ST) {
476 printk("Store Error Report\n");
477 recoverable = 0;
478 }
479
480 if (reason & MCSR_LDG) {
481 printk("Guarded Load Error Report\n");
482 recoverable = 0;
483 }
484
485 if (reason & MCSR_TLBSYNC)
486 printk("Simultaneous tlbsync operations\n");
487
488 if (reason & MCSR_BSL2_ERR) {
489 printk("Level 2 Cache Error\n");
490 recoverable = 0;
491 }
492
493 if (reason & MCSR_MAV) {
494 u64 addr;
495
496 addr = mfspr(SPRN_MCAR);
497 addr |= (u64)mfspr(SPRN_MCARU) << 32;
498
499 printk("Machine Check %s Address: %#llx\n",
500 reason & MCSR_MEA ? "Effective" : "Physical", addr);
501 }
502
503 mtspr(SPRN_MCSR, mcsr);
504 return mfspr(SPRN_MCSR) == 0 && recoverable;
505 }
506
507 int machine_check_e500(struct pt_regs *regs)
508 {
509 unsigned long reason = get_mc_reason(regs);
510
511 printk("Machine check in kernel mode.\n");
512 printk("Caused by (from MCSR=%lx): ", reason);
513
514 if (reason & MCSR_MCP)
515 printk("Machine Check Signal\n");
516 if (reason & MCSR_ICPERR)
517 printk("Instruction Cache Parity Error\n");
518 if (reason & MCSR_DCP_PERR)
519 printk("Data Cache Push Parity Error\n");
520 if (reason & MCSR_DCPERR)
521 printk("Data Cache Parity Error\n");
522 if (reason & MCSR_BUS_IAERR)
523 printk("Bus - Instruction Address Error\n");
524 if (reason & MCSR_BUS_RAERR)
525 printk("Bus - Read Address Error\n");
526 if (reason & MCSR_BUS_WAERR)
527 printk("Bus - Write Address Error\n");
528 if (reason & MCSR_BUS_IBERR)
529 printk("Bus - Instruction Data Error\n");
530 if (reason & MCSR_BUS_RBERR)
531 printk("Bus - Read Data Bus Error\n");
532 if (reason & MCSR_BUS_WBERR)
533 printk("Bus - Read Data Bus Error\n");
534 if (reason & MCSR_BUS_IPERR)
535 printk("Bus - Instruction Parity Error\n");
536 if (reason & MCSR_BUS_RPERR)
537 printk("Bus - Read Parity Error\n");
538
539 return 0;
540 }
541
542 int machine_check_generic(struct pt_regs *regs)
543 {
544 return 0;
545 }
546 #elif defined(CONFIG_E200)
547 int machine_check_e200(struct pt_regs *regs)
548 {
549 unsigned long reason = get_mc_reason(regs);
550
551 printk("Machine check in kernel mode.\n");
552 printk("Caused by (from MCSR=%lx): ", reason);
553
554 if (reason & MCSR_MCP)
555 printk("Machine Check Signal\n");
556 if (reason & MCSR_CP_PERR)
557 printk("Cache Push Parity Error\n");
558 if (reason & MCSR_CPERR)
559 printk("Cache Parity Error\n");
560 if (reason & MCSR_EXCP_ERR)
561 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
562 if (reason & MCSR_BUS_IRERR)
563 printk("Bus - Read Bus Error on instruction fetch\n");
564 if (reason & MCSR_BUS_DRERR)
565 printk("Bus - Read Bus Error on data load\n");
566 if (reason & MCSR_BUS_WRERR)
567 printk("Bus - Write Bus Error on buffered store or cache line push\n");
568
569 return 0;
570 }
571 #else
572 int machine_check_generic(struct pt_regs *regs)
573 {
574 unsigned long reason = get_mc_reason(regs);
575
576 printk("Machine check in kernel mode.\n");
577 printk("Caused by (from SRR1=%lx): ", reason);
578 switch (reason & 0x601F0000) {
579 case 0x80000:
580 printk("Machine check signal\n");
581 break;
582 case 0: /* for 601 */
583 case 0x40000:
584 case 0x140000: /* 7450 MSS error and TEA */
585 printk("Transfer error ack signal\n");
586 break;
587 case 0x20000:
588 printk("Data parity error signal\n");
589 break;
590 case 0x10000:
591 printk("Address parity error signal\n");
592 break;
593 case 0x20000000:
594 printk("L1 Data Cache error\n");
595 break;
596 case 0x40000000:
597 printk("L1 Instruction Cache error\n");
598 break;
599 case 0x00100000:
600 printk("L2 data cache parity error\n");
601 break;
602 default:
603 printk("Unknown values in msr\n");
604 }
605 return 0;
606 }
607 #endif /* everything else */
608
609 void machine_check_exception(struct pt_regs *regs)
610 {
611 int recover = 0;
612
613 __get_cpu_var(irq_stat).mce_exceptions++;
614
615 /* See if any machine dependent calls. In theory, we would want
616 * to call the CPU first, and call the ppc_md. one if the CPU
617 * one returns a positive number. However there is existing code
618 * that assumes the board gets a first chance, so let's keep it
619 * that way for now and fix things later. --BenH.
620 */
621 if (ppc_md.machine_check_exception)
622 recover = ppc_md.machine_check_exception(regs);
623 else if (cur_cpu_spec->machine_check)
624 recover = cur_cpu_spec->machine_check(regs);
625
626 if (recover > 0)
627 return;
628
629 if (user_mode(regs)) {
630 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
631 return;
632 }
633
634 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
635 /* the qspan pci read routines can cause machine checks -- Cort
636 *
637 * yuck !!! that totally needs to go away ! There are better ways
638 * to deal with that than having a wart in the mcheck handler.
639 * -- BenH
640 */
641 bad_page_fault(regs, regs->dar, SIGBUS);
642 return;
643 #endif
644
645 if (debugger_fault_handler(regs))
646 return;
647
648 if (check_io_access(regs))
649 return;
650
651 if (debugger_fault_handler(regs))
652 return;
653 die("Machine check", regs, SIGBUS);
654
655 /* Must die if the interrupt is not recoverable */
656 if (!(regs->msr & MSR_RI))
657 panic("Unrecoverable Machine check");
658 }
659
660 void SMIException(struct pt_regs *regs)
661 {
662 die("System Management Interrupt", regs, SIGABRT);
663 }
664
665 void unknown_exception(struct pt_regs *regs)
666 {
667 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
668 regs->nip, regs->msr, regs->trap);
669
670 _exception(SIGTRAP, regs, 0, 0);
671 }
672
673 void instruction_breakpoint_exception(struct pt_regs *regs)
674 {
675 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
676 5, SIGTRAP) == NOTIFY_STOP)
677 return;
678 if (debugger_iabr_match(regs))
679 return;
680 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
681 }
682
683 void RunModeException(struct pt_regs *regs)
684 {
685 _exception(SIGTRAP, regs, 0, 0);
686 }
687
688 void __kprobes single_step_exception(struct pt_regs *regs)
689 {
690 clear_single_step(regs);
691
692 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
693 5, SIGTRAP) == NOTIFY_STOP)
694 return;
695 if (debugger_sstep(regs))
696 return;
697
698 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
699 }
700
701 /*
702 * After we have successfully emulated an instruction, we have to
703 * check if the instruction was being single-stepped, and if so,
704 * pretend we got a single-step exception. This was pointed out
705 * by Kumar Gala. -- paulus
706 */
707 static void emulate_single_step(struct pt_regs *regs)
708 {
709 if (single_stepping(regs))
710 single_step_exception(regs);
711 }
712
713 static inline int __parse_fpscr(unsigned long fpscr)
714 {
715 int ret = 0;
716
717 /* Invalid operation */
718 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
719 ret = FPE_FLTINV;
720
721 /* Overflow */
722 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
723 ret = FPE_FLTOVF;
724
725 /* Underflow */
726 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
727 ret = FPE_FLTUND;
728
729 /* Divide by zero */
730 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
731 ret = FPE_FLTDIV;
732
733 /* Inexact result */
734 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
735 ret = FPE_FLTRES;
736
737 return ret;
738 }
739
740 static void parse_fpe(struct pt_regs *regs)
741 {
742 int code = 0;
743
744 flush_fp_to_thread(current);
745
746 code = __parse_fpscr(current->thread.fpscr.val);
747
748 _exception(SIGFPE, regs, code, regs->nip);
749 }
750
751 /*
752 * Illegal instruction emulation support. Originally written to
753 * provide the PVR to user applications using the mfspr rd, PVR.
754 * Return non-zero if we can't emulate, or -EFAULT if the associated
755 * memory access caused an access fault. Return zero on success.
756 *
757 * There are a couple of ways to do this, either "decode" the instruction
758 * or directly match lots of bits. In this case, matching lots of
759 * bits is faster and easier.
760 *
761 */
762 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
763 {
764 u8 rT = (instword >> 21) & 0x1f;
765 u8 rA = (instword >> 16) & 0x1f;
766 u8 NB_RB = (instword >> 11) & 0x1f;
767 u32 num_bytes;
768 unsigned long EA;
769 int pos = 0;
770
771 /* Early out if we are an invalid form of lswx */
772 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
773 if ((rT == rA) || (rT == NB_RB))
774 return -EINVAL;
775
776 EA = (rA == 0) ? 0 : regs->gpr[rA];
777
778 switch (instword & PPC_INST_STRING_MASK) {
779 case PPC_INST_LSWX:
780 case PPC_INST_STSWX:
781 EA += NB_RB;
782 num_bytes = regs->xer & 0x7f;
783 break;
784 case PPC_INST_LSWI:
785 case PPC_INST_STSWI:
786 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
787 break;
788 default:
789 return -EINVAL;
790 }
791
792 while (num_bytes != 0)
793 {
794 u8 val;
795 u32 shift = 8 * (3 - (pos & 0x3));
796
797 switch ((instword & PPC_INST_STRING_MASK)) {
798 case PPC_INST_LSWX:
799 case PPC_INST_LSWI:
800 if (get_user(val, (u8 __user *)EA))
801 return -EFAULT;
802 /* first time updating this reg,
803 * zero it out */
804 if (pos == 0)
805 regs->gpr[rT] = 0;
806 regs->gpr[rT] |= val << shift;
807 break;
808 case PPC_INST_STSWI:
809 case PPC_INST_STSWX:
810 val = regs->gpr[rT] >> shift;
811 if (put_user(val, (u8 __user *)EA))
812 return -EFAULT;
813 break;
814 }
815 /* move EA to next address */
816 EA += 1;
817 num_bytes--;
818
819 /* manage our position within the register */
820 if (++pos == 4) {
821 pos = 0;
822 if (++rT == 32)
823 rT = 0;
824 }
825 }
826
827 return 0;
828 }
829
830 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
831 {
832 u32 ra,rs;
833 unsigned long tmp;
834
835 ra = (instword >> 16) & 0x1f;
836 rs = (instword >> 21) & 0x1f;
837
838 tmp = regs->gpr[rs];
839 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
840 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
841 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
842 regs->gpr[ra] = tmp;
843
844 return 0;
845 }
846
847 static int emulate_isel(struct pt_regs *regs, u32 instword)
848 {
849 u8 rT = (instword >> 21) & 0x1f;
850 u8 rA = (instword >> 16) & 0x1f;
851 u8 rB = (instword >> 11) & 0x1f;
852 u8 BC = (instword >> 6) & 0x1f;
853 u8 bit;
854 unsigned long tmp;
855
856 tmp = (rA == 0) ? 0 : regs->gpr[rA];
857 bit = (regs->ccr >> (31 - BC)) & 0x1;
858
859 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
860
861 return 0;
862 }
863
864 static int emulate_instruction(struct pt_regs *regs)
865 {
866 u32 instword;
867 u32 rd;
868
869 if (!user_mode(regs) || (regs->msr & MSR_LE))
870 return -EINVAL;
871 CHECK_FULL_REGS(regs);
872
873 if (get_user(instword, (u32 __user *)(regs->nip)))
874 return -EFAULT;
875
876 /* Emulate the mfspr rD, PVR. */
877 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
878 PPC_WARN_EMULATED(mfpvr, regs);
879 rd = (instword >> 21) & 0x1f;
880 regs->gpr[rd] = mfspr(SPRN_PVR);
881 return 0;
882 }
883
884 /* Emulating the dcba insn is just a no-op. */
885 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
886 PPC_WARN_EMULATED(dcba, regs);
887 return 0;
888 }
889
890 /* Emulate the mcrxr insn. */
891 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
892 int shift = (instword >> 21) & 0x1c;
893 unsigned long msk = 0xf0000000UL >> shift;
894
895 PPC_WARN_EMULATED(mcrxr, regs);
896 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
897 regs->xer &= ~0xf0000000UL;
898 return 0;
899 }
900
901 /* Emulate load/store string insn. */
902 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
903 PPC_WARN_EMULATED(string, regs);
904 return emulate_string_inst(regs, instword);
905 }
906
907 /* Emulate the popcntb (Population Count Bytes) instruction. */
908 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
909 PPC_WARN_EMULATED(popcntb, regs);
910 return emulate_popcntb_inst(regs, instword);
911 }
912
913 /* Emulate isel (Integer Select) instruction */
914 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
915 PPC_WARN_EMULATED(isel, regs);
916 return emulate_isel(regs, instword);
917 }
918
919 return -EINVAL;
920 }
921
922 int is_valid_bugaddr(unsigned long addr)
923 {
924 return is_kernel_addr(addr);
925 }
926
927 void __kprobes program_check_exception(struct pt_regs *regs)
928 {
929 unsigned int reason = get_reason(regs);
930 extern int do_mathemu(struct pt_regs *regs);
931
932 /* We can now get here via a FP Unavailable exception if the core
933 * has no FPU, in that case the reason flags will be 0 */
934
935 if (reason & REASON_FP) {
936 /* IEEE FP exception */
937 parse_fpe(regs);
938 return;
939 }
940 if (reason & REASON_TRAP) {
941 /* Debugger is first in line to stop recursive faults in
942 * rcu_lock, notify_die, or atomic_notifier_call_chain */
943 if (debugger_bpt(regs))
944 return;
945
946 /* trap exception */
947 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
948 == NOTIFY_STOP)
949 return;
950
951 if (!(regs->msr & MSR_PR) && /* not user-mode */
952 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
953 regs->nip += 4;
954 return;
955 }
956 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
957 return;
958 }
959
960 local_irq_enable();
961
962 #ifdef CONFIG_MATH_EMULATION
963 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
964 * but there seems to be a hardware bug on the 405GP (RevD)
965 * that means ESR is sometimes set incorrectly - either to
966 * ESR_DST (!?) or 0. In the process of chasing this with the
967 * hardware people - not sure if it can happen on any illegal
968 * instruction or only on FP instructions, whether there is a
969 * pattern to occurences etc. -dgibson 31/Mar/2003 */
970 switch (do_mathemu(regs)) {
971 case 0:
972 emulate_single_step(regs);
973 return;
974 case 1: {
975 int code = 0;
976 code = __parse_fpscr(current->thread.fpscr.val);
977 _exception(SIGFPE, regs, code, regs->nip);
978 return;
979 }
980 case -EFAULT:
981 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
982 return;
983 }
984 /* fall through on any other errors */
985 #endif /* CONFIG_MATH_EMULATION */
986
987 /* Try to emulate it if we should. */
988 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
989 switch (emulate_instruction(regs)) {
990 case 0:
991 regs->nip += 4;
992 emulate_single_step(regs);
993 return;
994 case -EFAULT:
995 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
996 return;
997 }
998 }
999
1000 if (reason & REASON_PRIVILEGED)
1001 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1002 else
1003 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1004 }
1005
1006 void alignment_exception(struct pt_regs *regs)
1007 {
1008 int sig, code, fixed = 0;
1009
1010 /* we don't implement logging of alignment exceptions */
1011 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1012 fixed = fix_alignment(regs);
1013
1014 if (fixed == 1) {
1015 regs->nip += 4; /* skip over emulated instruction */
1016 emulate_single_step(regs);
1017 return;
1018 }
1019
1020 /* Operand address was bad */
1021 if (fixed == -EFAULT) {
1022 sig = SIGSEGV;
1023 code = SEGV_ACCERR;
1024 } else {
1025 sig = SIGBUS;
1026 code = BUS_ADRALN;
1027 }
1028 if (user_mode(regs))
1029 _exception(sig, regs, code, regs->dar);
1030 else
1031 bad_page_fault(regs, regs->dar, sig);
1032 }
1033
1034 void StackOverflow(struct pt_regs *regs)
1035 {
1036 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1037 current, regs->gpr[1]);
1038 debugger(regs);
1039 show_regs(regs);
1040 panic("kernel stack overflow");
1041 }
1042
1043 void nonrecoverable_exception(struct pt_regs *regs)
1044 {
1045 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1046 regs->nip, regs->msr);
1047 debugger(regs);
1048 die("nonrecoverable exception", regs, SIGKILL);
1049 }
1050
1051 void trace_syscall(struct pt_regs *regs)
1052 {
1053 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1054 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1055 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1056 }
1057
1058 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1059 {
1060 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1061 "%lx at %lx\n", regs->trap, regs->nip);
1062 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1063 }
1064
1065 void altivec_unavailable_exception(struct pt_regs *regs)
1066 {
1067 if (user_mode(regs)) {
1068 /* A user program has executed an altivec instruction,
1069 but this kernel doesn't support altivec. */
1070 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1071 return;
1072 }
1073
1074 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1075 "%lx at %lx\n", regs->trap, regs->nip);
1076 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1077 }
1078
1079 void vsx_unavailable_exception(struct pt_regs *regs)
1080 {
1081 if (user_mode(regs)) {
1082 /* A user program has executed an vsx instruction,
1083 but this kernel doesn't support vsx. */
1084 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1085 return;
1086 }
1087
1088 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1089 "%lx at %lx\n", regs->trap, regs->nip);
1090 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1091 }
1092
1093 void performance_monitor_exception(struct pt_regs *regs)
1094 {
1095 __get_cpu_var(irq_stat).pmu_irqs++;
1096
1097 perf_irq(regs);
1098 }
1099
1100 #ifdef CONFIG_8xx
1101 void SoftwareEmulation(struct pt_regs *regs)
1102 {
1103 extern int do_mathemu(struct pt_regs *);
1104 extern int Soft_emulate_8xx(struct pt_regs *);
1105 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
1106 int errcode;
1107 #endif
1108
1109 CHECK_FULL_REGS(regs);
1110
1111 if (!user_mode(regs)) {
1112 debugger(regs);
1113 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1114 }
1115
1116 #ifdef CONFIG_MATH_EMULATION
1117 errcode = do_mathemu(regs);
1118 if (errcode >= 0)
1119 PPC_WARN_EMULATED(math, regs);
1120
1121 switch (errcode) {
1122 case 0:
1123 emulate_single_step(regs);
1124 return;
1125 case 1: {
1126 int code = 0;
1127 code = __parse_fpscr(current->thread.fpscr.val);
1128 _exception(SIGFPE, regs, code, regs->nip);
1129 return;
1130 }
1131 case -EFAULT:
1132 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1133 return;
1134 default:
1135 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1136 return;
1137 }
1138
1139 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1140 errcode = Soft_emulate_8xx(regs);
1141 if (errcode >= 0)
1142 PPC_WARN_EMULATED(8xx, regs);
1143
1144 switch (errcode) {
1145 case 0:
1146 emulate_single_step(regs);
1147 return;
1148 case 1:
1149 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1150 return;
1151 case -EFAULT:
1152 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1153 return;
1154 }
1155 #else
1156 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1157 #endif
1158 }
1159 #endif /* CONFIG_8xx */
1160
1161 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1162 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1163 {
1164 int changed = 0;
1165 /*
1166 * Determine the cause of the debug event, clear the
1167 * event flags and send a trap to the handler. Torez
1168 */
1169 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1170 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1171 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1172 current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1173 #endif
1174 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1175 5);
1176 changed |= 0x01;
1177 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1178 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1179 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1180 6);
1181 changed |= 0x01;
1182 } else if (debug_status & DBSR_IAC1) {
1183 current->thread.dbcr0 &= ~DBCR0_IAC1;
1184 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1185 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1186 1);
1187 changed |= 0x01;
1188 } else if (debug_status & DBSR_IAC2) {
1189 current->thread.dbcr0 &= ~DBCR0_IAC2;
1190 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1191 2);
1192 changed |= 0x01;
1193 } else if (debug_status & DBSR_IAC3) {
1194 current->thread.dbcr0 &= ~DBCR0_IAC3;
1195 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1196 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1197 3);
1198 changed |= 0x01;
1199 } else if (debug_status & DBSR_IAC4) {
1200 current->thread.dbcr0 &= ~DBCR0_IAC4;
1201 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1202 4);
1203 changed |= 0x01;
1204 }
1205 /*
1206 * At the point this routine was called, the MSR(DE) was turned off.
1207 * Check all other debug flags and see if that bit needs to be turned
1208 * back on or not.
1209 */
1210 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1211 regs->msr |= MSR_DE;
1212 else
1213 /* Make sure the IDM flag is off */
1214 current->thread.dbcr0 &= ~DBCR0_IDM;
1215
1216 if (changed & 0x01)
1217 mtspr(SPRN_DBCR0, current->thread.dbcr0);
1218 }
1219
1220 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1221 {
1222 current->thread.dbsr = debug_status;
1223
1224 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1225 * on server, it stops on the target of the branch. In order to simulate
1226 * the server behaviour, we thus restart right away with a single step
1227 * instead of stopping here when hitting a BT
1228 */
1229 if (debug_status & DBSR_BT) {
1230 regs->msr &= ~MSR_DE;
1231
1232 /* Disable BT */
1233 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1234 /* Clear the BT event */
1235 mtspr(SPRN_DBSR, DBSR_BT);
1236
1237 /* Do the single step trick only when coming from userspace */
1238 if (user_mode(regs)) {
1239 current->thread.dbcr0 &= ~DBCR0_BT;
1240 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1241 regs->msr |= MSR_DE;
1242 return;
1243 }
1244
1245 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1246 5, SIGTRAP) == NOTIFY_STOP) {
1247 return;
1248 }
1249 if (debugger_sstep(regs))
1250 return;
1251 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1252 regs->msr &= ~MSR_DE;
1253
1254 /* Disable instruction completion */
1255 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1256 /* Clear the instruction completion event */
1257 mtspr(SPRN_DBSR, DBSR_IC);
1258
1259 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1260 5, SIGTRAP) == NOTIFY_STOP) {
1261 return;
1262 }
1263
1264 if (debugger_sstep(regs))
1265 return;
1266
1267 if (user_mode(regs)) {
1268 current->thread.dbcr0 &= ~DBCR0_IC;
1269 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1270 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1271 current->thread.dbcr1))
1272 regs->msr |= MSR_DE;
1273 else
1274 /* Make sure the IDM bit is off */
1275 current->thread.dbcr0 &= ~DBCR0_IDM;
1276 #endif
1277 }
1278
1279 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1280 } else
1281 handle_debug(regs, debug_status);
1282 }
1283 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1284
1285 #if !defined(CONFIG_TAU_INT)
1286 void TAUException(struct pt_regs *regs)
1287 {
1288 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1289 regs->nip, regs->msr, regs->trap, print_tainted());
1290 }
1291 #endif /* CONFIG_INT_TAU */
1292
1293 #ifdef CONFIG_ALTIVEC
1294 void altivec_assist_exception(struct pt_regs *regs)
1295 {
1296 int err;
1297
1298 if (!user_mode(regs)) {
1299 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1300 " at %lx\n", regs->nip);
1301 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1302 }
1303
1304 flush_altivec_to_thread(current);
1305
1306 PPC_WARN_EMULATED(altivec, regs);
1307 err = emulate_altivec(regs);
1308 if (err == 0) {
1309 regs->nip += 4; /* skip emulated instruction */
1310 emulate_single_step(regs);
1311 return;
1312 }
1313
1314 if (err == -EFAULT) {
1315 /* got an error reading the instruction */
1316 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1317 } else {
1318 /* didn't recognize the instruction */
1319 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1320 if (printk_ratelimit())
1321 printk(KERN_ERR "Unrecognized altivec instruction "
1322 "in %s at %lx\n", current->comm, regs->nip);
1323 current->thread.vscr.u[3] |= 0x10000;
1324 }
1325 }
1326 #endif /* CONFIG_ALTIVEC */
1327
1328 #ifdef CONFIG_VSX
1329 void vsx_assist_exception(struct pt_regs *regs)
1330 {
1331 if (!user_mode(regs)) {
1332 printk(KERN_EMERG "VSX assist exception in kernel mode"
1333 " at %lx\n", regs->nip);
1334 die("Kernel VSX assist exception", regs, SIGILL);
1335 }
1336
1337 flush_vsx_to_thread(current);
1338 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1339 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1340 }
1341 #endif /* CONFIG_VSX */
1342
1343 #ifdef CONFIG_FSL_BOOKE
1344 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1345 unsigned long error_code)
1346 {
1347 /* We treat cache locking instructions from the user
1348 * as priv ops, in the future we could try to do
1349 * something smarter
1350 */
1351 if (error_code & (ESR_DLK|ESR_ILK))
1352 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1353 return;
1354 }
1355 #endif /* CONFIG_FSL_BOOKE */
1356
1357 #ifdef CONFIG_SPE
1358 void SPEFloatingPointException(struct pt_regs *regs)
1359 {
1360 extern int do_spe_mathemu(struct pt_regs *regs);
1361 unsigned long spefscr;
1362 int fpexc_mode;
1363 int code = 0;
1364 int err;
1365
1366 preempt_disable();
1367 if (regs->msr & MSR_SPE)
1368 giveup_spe(current);
1369 preempt_enable();
1370
1371 spefscr = current->thread.spefscr;
1372 fpexc_mode = current->thread.fpexc_mode;
1373
1374 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1375 code = FPE_FLTOVF;
1376 }
1377 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1378 code = FPE_FLTUND;
1379 }
1380 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1381 code = FPE_FLTDIV;
1382 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1383 code = FPE_FLTINV;
1384 }
1385 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1386 code = FPE_FLTRES;
1387
1388 err = do_spe_mathemu(regs);
1389 if (err == 0) {
1390 regs->nip += 4; /* skip emulated instruction */
1391 emulate_single_step(regs);
1392 return;
1393 }
1394
1395 if (err == -EFAULT) {
1396 /* got an error reading the instruction */
1397 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1398 } else if (err == -EINVAL) {
1399 /* didn't recognize the instruction */
1400 printk(KERN_ERR "unrecognized spe instruction "
1401 "in %s at %lx\n", current->comm, regs->nip);
1402 } else {
1403 _exception(SIGFPE, regs, code, regs->nip);
1404 }
1405
1406 return;
1407 }
1408
1409 void SPEFloatingPointRoundException(struct pt_regs *regs)
1410 {
1411 extern int speround_handler(struct pt_regs *regs);
1412 int err;
1413
1414 preempt_disable();
1415 if (regs->msr & MSR_SPE)
1416 giveup_spe(current);
1417 preempt_enable();
1418
1419 regs->nip -= 4;
1420 err = speround_handler(regs);
1421 if (err == 0) {
1422 regs->nip += 4; /* skip emulated instruction */
1423 emulate_single_step(regs);
1424 return;
1425 }
1426
1427 if (err == -EFAULT) {
1428 /* got an error reading the instruction */
1429 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1430 } else if (err == -EINVAL) {
1431 /* didn't recognize the instruction */
1432 printk(KERN_ERR "unrecognized spe instruction "
1433 "in %s at %lx\n", current->comm, regs->nip);
1434 } else {
1435 _exception(SIGFPE, regs, 0, regs->nip);
1436 return;
1437 }
1438 }
1439 #endif
1440
1441 /*
1442 * We enter here if we get an unrecoverable exception, that is, one
1443 * that happened at a point where the RI (recoverable interrupt) bit
1444 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1445 * we therefore lost state by taking this exception.
1446 */
1447 void unrecoverable_exception(struct pt_regs *regs)
1448 {
1449 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1450 regs->trap, regs->nip);
1451 die("Unrecoverable exception", regs, SIGABRT);
1452 }
1453
1454 #ifdef CONFIG_BOOKE_WDT
1455 /*
1456 * Default handler for a Watchdog exception,
1457 * spins until a reboot occurs
1458 */
1459 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1460 {
1461 /* Generic WatchdogHandler, implement your own */
1462 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1463 return;
1464 }
1465
1466 void WatchdogException(struct pt_regs *regs)
1467 {
1468 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1469 WatchdogHandler(regs);
1470 }
1471 #endif
1472
1473 /*
1474 * We enter here if we discover during exception entry that we are
1475 * running in supervisor mode with a userspace value in the stack pointer.
1476 */
1477 void kernel_bad_stack(struct pt_regs *regs)
1478 {
1479 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1480 regs->gpr[1], regs->nip);
1481 die("Bad kernel stack pointer", regs, SIGABRT);
1482 }
1483
1484 void __init trap_init(void)
1485 {
1486 }
1487
1488
1489 #ifdef CONFIG_PPC_EMULATED_STATS
1490
1491 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1492
1493 struct ppc_emulated ppc_emulated = {
1494 #ifdef CONFIG_ALTIVEC
1495 WARN_EMULATED_SETUP(altivec),
1496 #endif
1497 WARN_EMULATED_SETUP(dcba),
1498 WARN_EMULATED_SETUP(dcbz),
1499 WARN_EMULATED_SETUP(fp_pair),
1500 WARN_EMULATED_SETUP(isel),
1501 WARN_EMULATED_SETUP(mcrxr),
1502 WARN_EMULATED_SETUP(mfpvr),
1503 WARN_EMULATED_SETUP(multiple),
1504 WARN_EMULATED_SETUP(popcntb),
1505 WARN_EMULATED_SETUP(spe),
1506 WARN_EMULATED_SETUP(string),
1507 WARN_EMULATED_SETUP(unaligned),
1508 #ifdef CONFIG_MATH_EMULATION
1509 WARN_EMULATED_SETUP(math),
1510 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1511 WARN_EMULATED_SETUP(8xx),
1512 #endif
1513 #ifdef CONFIG_VSX
1514 WARN_EMULATED_SETUP(vsx),
1515 #endif
1516 };
1517
1518 u32 ppc_warn_emulated;
1519
1520 void ppc_warn_emulated_print(const char *type)
1521 {
1522 if (printk_ratelimit())
1523 pr_warning("%s used emulated %s instruction\n", current->comm,
1524 type);
1525 }
1526
1527 static int __init ppc_warn_emulated_init(void)
1528 {
1529 struct dentry *dir, *d;
1530 unsigned int i;
1531 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1532
1533 if (!powerpc_debugfs_root)
1534 return -ENODEV;
1535
1536 dir = debugfs_create_dir("emulated_instructions",
1537 powerpc_debugfs_root);
1538 if (!dir)
1539 return -ENOMEM;
1540
1541 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1542 &ppc_warn_emulated);
1543 if (!d)
1544 goto fail;
1545
1546 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1547 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1548 (u32 *)&entries[i].val.counter);
1549 if (!d)
1550 goto fail;
1551 }
1552
1553 return 0;
1554
1555 fail:
1556 debugfs_remove_recursive(dir);
1557 return -ENOMEM;
1558 }
1559
1560 device_initcall(ppc_warn_emulated_init);
1561
1562 #endif /* CONFIG_PPC_EMULATED_STATS */
Linux kernel - Deliverables
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