arch/powerpc/kvm/book3s_hv_interrupts.S

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, write to the Free Software
  13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  14  *
  15  * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  16  *
  17  * Derived from book3s_interrupts.S, which is:
  18  * Copyright SUSE Linux Products GmbH 2009
  19  *
  20  * Authors: Alexander Graf <agraf@suse.de>
  21  */
  22
  23 #include <asm/ppc_asm.h>
  24 #include <asm/kvm_asm.h>
  25 #include <asm/reg.h>
  26 #include <asm/page.h>
  27 #include <asm/asm-offsets.h>
  28 #include <asm/exception-64s.h>
  29 #include <asm/ppc-opcode.h>
  30
  31 /*****************************************************************************
  32  *                                                                           *
  33  *     Guest entry / exit code that is in kernel module memory (vmalloc)     *
  34  *                                                                           *
  35  ****************************************************************************/
  36
  37 /* Registers:
  38  *  none
  39  */
  40 _GLOBAL(__kvmppc_vcore_entry)
  41
  42         /* Write correct stack frame */
  43         mflr    r0
  44         std     r0,PPC_LR_STKOFF(r1)
  45
  46         /* Save host state to the stack */
  47         stdu    r1, -SWITCH_FRAME_SIZE(r1)
  48
  49         /* Save non-volatile registers (r14 - r31) and CR */
  50         SAVE_NVGPRS(r1)
  51         mfcr    r3
  52         std     r3, _CCR(r1)
  53
  54         /* Save host DSCR */
  55 BEGIN_FTR_SECTION
  56         mfspr   r3, SPRN_DSCR
  57         std     r3, HSTATE_DSCR(r13)
  58 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
  59
  60 BEGIN_FTR_SECTION
  61         /* Save host DABR */
  62         mfspr   r3, SPRN_DABR
  63         std     r3, HSTATE_DABR(r13)
  64 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
  65
  66         /* Hard-disable interrupts */
  67         mfmsr   r10
  68         std     r10, HSTATE_HOST_MSR(r13)
  69         rldicl  r10,r10,48,1
  70         rotldi  r10,r10,16
  71         mtmsrd  r10,1
  72
  73         /* Save host PMU registers */
  74 BEGIN_FTR_SECTION
  75         /* Work around P8 PMAE bug */
  76         li      r3, -1
  77         clrrdi  r3, r3, 10
  78         mfspr   r8, SPRN_MMCR2
  79         mtspr   SPRN_MMCR2, r3          /* freeze all counters using MMCR2 */
  80         isync
  81 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
  82         li      r3, 1
  83         sldi    r3, r3, 31              /* MMCR0_FC (freeze counters) bit */
  84         mfspr   r7, SPRN_MMCR0          /* save MMCR0 */
  85         mtspr   SPRN_MMCR0, r3          /* freeze all counters, disable interrupts */
  86         mfspr   r6, SPRN_MMCRA
  87 BEGIN_FTR_SECTION
  88         /* On P7, clear MMCRA in order to disable SDAR updates */
  89         li      r5, 0
  90         mtspr   SPRN_MMCRA, r5
  91 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
  92         isync
  93         ld      r3, PACALPPACAPTR(r13)  /* is the host using the PMU? */
  94         lbz     r5, LPPACA_PMCINUSE(r3)
  95         cmpwi   r5, 0
  96         beq     31f                     /* skip if not */
  97         mfspr   r5, SPRN_MMCR1
  98         mfspr   r9, SPRN_SIAR
  99         mfspr   r10, SPRN_SDAR
 100         std     r7, HSTATE_MMCR(r13)
 101         std     r5, HSTATE_MMCR + 8(r13)
 102         std     r6, HSTATE_MMCR + 16(r13)
 103         std     r9, HSTATE_MMCR + 24(r13)
 104         std     r10, HSTATE_MMCR + 32(r13)
 105 BEGIN_FTR_SECTION
 106         mfspr   r9, SPRN_SIER
 107         std     r8, HSTATE_MMCR + 40(r13)
 108         std     r9, HSTATE_MMCR + 48(r13)
 109 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 110         mfspr   r3, SPRN_PMC1
 111         mfspr   r5, SPRN_PMC2
 112         mfspr   r6, SPRN_PMC3
 113         mfspr   r7, SPRN_PMC4
 114         mfspr   r8, SPRN_PMC5
 115         mfspr   r9, SPRN_PMC6
 116 BEGIN_FTR_SECTION
 117         mfspr   r10, SPRN_PMC7
 118         mfspr   r11, SPRN_PMC8
 119 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 120         stw     r3, HSTATE_PMC(r13)
 121         stw     r5, HSTATE_PMC + 4(r13)
 122         stw     r6, HSTATE_PMC + 8(r13)
 123         stw     r7, HSTATE_PMC + 12(r13)
 124         stw     r8, HSTATE_PMC + 16(r13)
 125         stw     r9, HSTATE_PMC + 20(r13)
 126 BEGIN_FTR_SECTION
 127         stw     r10, HSTATE_PMC + 24(r13)
 128         stw     r11, HSTATE_PMC + 28(r13)
 129 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 130 31:
 131
 132         /*
 133          * Put whatever is in the decrementer into the
 134          * hypervisor decrementer.
 135          */
 136         mfspr   r8,SPRN_DEC
 137         mftb    r7
 138         mtspr   SPRN_HDEC,r8
 139         extsw   r8,r8
 140         add     r8,r8,r7
 141         std     r8,HSTATE_DECEXP(r13)
 142
 143 #ifdef CONFIG_SMP
 144         /*
 145          * On PPC970, if the guest vcpu has an external interrupt pending,
 146          * send ourselves an IPI so as to interrupt the guest once it
 147          * enables interrupts.  (It must have interrupts disabled,
 148          * otherwise we would already have delivered the interrupt.)
 149          *
 150          * XXX If this is a UP build, smp_send_reschedule is not available,
 151          * so the interrupt will be delayed until the next time the vcpu
 152          * enters the guest with interrupts enabled.
 153          */
 154 BEGIN_FTR_SECTION
 155         ld      r4, HSTATE_KVM_VCPU(r13)
 156         ld      r0, VCPU_PENDING_EXC(r4)
 157         li      r7, (1 << BOOK3S_IRQPRIO_EXTERNAL)
 158         oris    r7, r7, (1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
 159         and.    r0, r0, r7
 160         beq     32f
 161         lhz     r3, PACAPACAINDEX(r13)
 162         bl      smp_send_reschedule
 163         nop
 164 32:
 165 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
 166 #endif /* CONFIG_SMP */
 167
 168         /* Jump to partition switch code */
 169         bl      kvmppc_hv_entry_trampoline
 170         nop
 171
 172 /*
 173  * We return here in virtual mode after the guest exits
 174  * with something that we can't handle in real mode.
 175  * Interrupts are enabled again at this point.
 176  */
 177
 178         /*
 179          * Register usage at this point:
 180          *
 181          * R1       = host R1
 182          * R2       = host R2
 183          * R12      = exit handler id
 184          * R13      = PACA
 185          */
 186
 187         /* Restore non-volatile host registers (r14 - r31) and CR */
 188         REST_NVGPRS(r1)
 189         ld      r4, _CCR(r1)
 190         mtcr    r4
 191
 192         addi    r1, r1, SWITCH_FRAME_SIZE
 193         ld      r0, PPC_LR_STKOFF(r1)
 194         mtlr    r0
 195         blr