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KVM: PPC: Book3S HV: Pull out interrupt-reading code into a subroutine
[deliverable/linux.git] / arch / powerpc / kvm / book3s_hv_rmhandlers.S
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
12 *
13 * Derived from book3s_rmhandlers.S and other files, which are:
14 *
15 * Copyright SUSE Linux Products GmbH 2009
16 *
17 * Authors: Alexander Graf <agraf@suse.de>
18 */
19
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/reg.h>
23 #include <asm/mmu.h>
24 #include <asm/page.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
31
32 #ifdef __LITTLE_ENDIAN__
33 #error Need to fix lppaca and SLB shadow accesses in little endian mode
34 #endif
35
36 /*****************************************************************************
37 * *
38 * Real Mode handlers that need to be in the linear mapping *
39 * *
40 ****************************************************************************/
41
42 .globl kvmppc_skip_interrupt
43 kvmppc_skip_interrupt:
44 mfspr r13,SPRN_SRR0
45 addi r13,r13,4
46 mtspr SPRN_SRR0,r13
47 GET_SCRATCH0(r13)
48 rfid
49 b .
50
51 .globl kvmppc_skip_Hinterrupt
52 kvmppc_skip_Hinterrupt:
53 mfspr r13,SPRN_HSRR0
54 addi r13,r13,4
55 mtspr SPRN_HSRR0,r13
56 GET_SCRATCH0(r13)
57 hrfid
58 b .
59
60 /*
61 * Call kvmppc_hv_entry in real mode.
62 * Must be called with interrupts hard-disabled.
63 *
64 * Input Registers:
65 *
66 * LR = return address to continue at after eventually re-enabling MMU
67 */
68 _GLOBAL(kvmppc_hv_entry_trampoline)
69 mflr r0
70 std r0, PPC_LR_STKOFF(r1)
71 stdu r1, -112(r1)
72 mfmsr r10
73 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
74 li r0,MSR_RI
75 andc r0,r10,r0
76 li r6,MSR_IR | MSR_DR
77 andc r6,r10,r6
78 mtmsrd r0,1 /* clear RI in MSR */
79 mtsrr0 r5
80 mtsrr1 r6
81 RFI
82
83 kvmppc_call_hv_entry:
84 bl kvmppc_hv_entry
85
86 /* Back from guest - restore host state and return to caller */
87
88 /* Restore host DABR and DABRX */
89 ld r5,HSTATE_DABR(r13)
90 li r6,7
91 mtspr SPRN_DABR,r5
92 mtspr SPRN_DABRX,r6
93
94 /* Restore SPRG3 */
95 ld r3,PACA_SPRG3(r13)
96 mtspr SPRN_SPRG3,r3
97
98 /*
99 * Reload DEC. HDEC interrupts were disabled when
100 * we reloaded the host's LPCR value.
101 */
102 ld r3, HSTATE_DECEXP(r13)
103 mftb r4
104 subf r4, r4, r3
105 mtspr SPRN_DEC, r4
106
107 /* Reload the host's PMU registers */
108 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
109 lbz r4, LPPACA_PMCINUSE(r3)
110 cmpwi r4, 0
111 beq 23f /* skip if not */
112 lwz r3, HSTATE_PMC(r13)
113 lwz r4, HSTATE_PMC + 4(r13)
114 lwz r5, HSTATE_PMC + 8(r13)
115 lwz r6, HSTATE_PMC + 12(r13)
116 lwz r8, HSTATE_PMC + 16(r13)
117 lwz r9, HSTATE_PMC + 20(r13)
118 BEGIN_FTR_SECTION
119 lwz r10, HSTATE_PMC + 24(r13)
120 lwz r11, HSTATE_PMC + 28(r13)
121 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
122 mtspr SPRN_PMC1, r3
123 mtspr SPRN_PMC2, r4
124 mtspr SPRN_PMC3, r5
125 mtspr SPRN_PMC4, r6
126 mtspr SPRN_PMC5, r8
127 mtspr SPRN_PMC6, r9
128 BEGIN_FTR_SECTION
129 mtspr SPRN_PMC7, r10
130 mtspr SPRN_PMC8, r11
131 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
132 ld r3, HSTATE_MMCR(r13)
133 ld r4, HSTATE_MMCR + 8(r13)
134 ld r5, HSTATE_MMCR + 16(r13)
135 mtspr SPRN_MMCR1, r4
136 mtspr SPRN_MMCRA, r5
137 mtspr SPRN_MMCR0, r3
138 isync
139 23:
140
141 /*
142 * For external and machine check interrupts, we need
143 * to call the Linux handler to process the interrupt.
144 * We do that by jumping to absolute address 0x500 for
145 * external interrupts, or the machine_check_fwnmi label
146 * for machine checks (since firmware might have patched
147 * the vector area at 0x200). The [h]rfid at the end of the
148 * handler will return to the book3s_hv_interrupts.S code.
149 * For other interrupts we do the rfid to get back
150 * to the book3s_hv_interrupts.S code here.
151 */
152 ld r8, 112+PPC_LR_STKOFF(r1)
153 addi r1, r1, 112
154 ld r7, HSTATE_HOST_MSR(r13)
155
156 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
157 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
158 BEGIN_FTR_SECTION
159 beq 11f
160 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
161
162 /* RFI into the highmem handler, or branch to interrupt handler */
163 mfmsr r6
164 li r0, MSR_RI
165 andc r6, r6, r0
166 mtmsrd r6, 1 /* Clear RI in MSR */
167 mtsrr0 r8
168 mtsrr1 r7
169 beqa 0x500 /* external interrupt (PPC970) */
170 beq cr1, 13f /* machine check */
171 RFI
172
173 /* On POWER7, we have external interrupts set to use HSRR0/1 */
174 11: mtspr SPRN_HSRR0, r8
175 mtspr SPRN_HSRR1, r7
176 ba 0x500
177
178 13: b machine_check_fwnmi
179
180
181 /*
182 * We come in here when wakened from nap mode on a secondary hw thread.
183 * Relocation is off and most register values are lost.
184 * r13 points to the PACA.
185 */
186 .globl kvm_start_guest
187 kvm_start_guest:
188 ld r1,PACAEMERGSP(r13)
189 subi r1,r1,STACK_FRAME_OVERHEAD
190 ld r2,PACATOC(r13)
191
192 li r0,KVM_HWTHREAD_IN_KVM
193 stb r0,HSTATE_HWTHREAD_STATE(r13)
194
195 /* NV GPR values from power7_idle() will no longer be valid */
196 li r0,1
197 stb r0,PACA_NAPSTATELOST(r13)
198
199 /* were we napping due to cede? */
200 lbz r0,HSTATE_NAPPING(r13)
201 cmpwi r0,0
202 bne kvm_end_cede
203
204 /*
205 * We weren't napping due to cede, so this must be a secondary
206 * thread being woken up to run a guest, or being woken up due
207 * to a stray IPI. (Or due to some machine check or hypervisor
208 * maintenance interrupt while the core is in KVM.)
209 */
210
211 /* Check the wake reason in SRR1 to see why we got here */
212 mfspr r3,SPRN_SRR1
213 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
214 cmpwi r3,4 /* was it an external interrupt? */
215 bne 27f /* if not */
216 ld r5,HSTATE_XICS_PHYS(r13)
217 li r7,XICS_XIRR /* if it was an external interrupt, */
218 lwzcix r8,r5,r7 /* get and ack the interrupt */
219 sync
220 clrldi. r9,r8,40 /* get interrupt source ID. */
221 beq 28f /* none there? */
222 cmpwi r9,XICS_IPI /* was it an IPI? */
223 bne 29f
224 li r0,0xff
225 li r6,XICS_MFRR
226 stbcix r0,r5,r6 /* clear IPI */
227 stwcix r8,r5,r7 /* EOI the interrupt */
228 sync /* order loading of vcpu after that */
229
230 /* get vcpu pointer, NULL if we have no vcpu to run */
231 ld r4,HSTATE_KVM_VCPU(r13)
232 cmpdi r4,0
233 /* if we have no vcpu to run, go back to sleep */
234 beq kvm_no_guest
235 b 30f
236
237 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
238 b kvm_no_guest
239 28: /* SRR1 said external but ICP said nope?? */
240 b kvm_no_guest
241 29: /* External non-IPI interrupt to offline secondary thread? help?? */
242 stw r8,HSTATE_SAVED_XIRR(r13)
243 b kvm_no_guest
244
245 30: bl kvmppc_hv_entry
246
247 /* Back from the guest, go back to nap */
248 /* Clear our vcpu pointer so we don't come back in early */
249 li r0, 0
250 std r0, HSTATE_KVM_VCPU(r13)
251 lwsync
252 /* Clear any pending IPI - we're an offline thread */
253 ld r5, HSTATE_XICS_PHYS(r13)
254 li r7, XICS_XIRR
255 lwzcix r3, r5, r7 /* ack any pending interrupt */
256 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
257 beq 37f
258 sync
259 li r0, 0xff
260 li r6, XICS_MFRR
261 stbcix r0, r5, r6 /* clear the IPI */
262 stwcix r3, r5, r7 /* EOI it */
263 37: sync
264
265 /* increment the nap count and then go to nap mode */
266 ld r4, HSTATE_KVM_VCORE(r13)
267 addi r4, r4, VCORE_NAP_COUNT
268 lwsync /* make previous updates visible */
269 51: lwarx r3, 0, r4
270 addi r3, r3, 1
271 stwcx. r3, 0, r4
272 bne 51b
273
274 kvm_no_guest:
275 li r0, KVM_HWTHREAD_IN_NAP
276 stb r0, HSTATE_HWTHREAD_STATE(r13)
277 li r3, LPCR_PECE0
278 mfspr r4, SPRN_LPCR
279 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
280 mtspr SPRN_LPCR, r4
281 isync
282 std r0, HSTATE_SCRATCH0(r13)
283 ptesync
284 ld r0, HSTATE_SCRATCH0(r13)
285 1: cmpd r0, r0
286 bne 1b
287 nap
288 b .
289
290 /******************************************************************************
291 * *
292 * Entry code *
293 * *
294 *****************************************************************************/
295
296 .global kvmppc_hv_entry
297 kvmppc_hv_entry:
298
299 /* Required state:
300 *
301 * R4 = vcpu pointer
302 * MSR = ~IR|DR
303 * R13 = PACA
304 * R1 = host R1
305 * all other volatile GPRS = free
306 */
307 mflr r0
308 std r0, PPC_LR_STKOFF(r1)
309 stdu r1, -112(r1)
310
311 /* Set partition DABR */
312 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
313 li r5,3
314 ld r6,VCPU_DABR(r4)
315 mtspr SPRN_DABRX,r5
316 mtspr SPRN_DABR,r6
317 BEGIN_FTR_SECTION
318 isync
319 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
320
321 /* Load guest PMU registers */
322 /* R4 is live here (vcpu pointer) */
323 li r3, 1
324 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
325 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
326 isync
327 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
328 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
329 lwz r6, VCPU_PMC + 8(r4)
330 lwz r7, VCPU_PMC + 12(r4)
331 lwz r8, VCPU_PMC + 16(r4)
332 lwz r9, VCPU_PMC + 20(r4)
333 BEGIN_FTR_SECTION
334 lwz r10, VCPU_PMC + 24(r4)
335 lwz r11, VCPU_PMC + 28(r4)
336 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
337 mtspr SPRN_PMC1, r3
338 mtspr SPRN_PMC2, r5
339 mtspr SPRN_PMC3, r6
340 mtspr SPRN_PMC4, r7
341 mtspr SPRN_PMC5, r8
342 mtspr SPRN_PMC6, r9
343 BEGIN_FTR_SECTION
344 mtspr SPRN_PMC7, r10
345 mtspr SPRN_PMC8, r11
346 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
347 ld r3, VCPU_MMCR(r4)
348 ld r5, VCPU_MMCR + 8(r4)
349 ld r6, VCPU_MMCR + 16(r4)
350 ld r7, VCPU_SIAR(r4)
351 ld r8, VCPU_SDAR(r4)
352 mtspr SPRN_MMCR1, r5
353 mtspr SPRN_MMCRA, r6
354 mtspr SPRN_SIAR, r7
355 mtspr SPRN_SDAR, r8
356 mtspr SPRN_MMCR0, r3
357 isync
358
359 /* Load up FP, VMX and VSX registers */
360 bl kvmppc_load_fp
361
362 ld r14, VCPU_GPR(R14)(r4)
363 ld r15, VCPU_GPR(R15)(r4)
364 ld r16, VCPU_GPR(R16)(r4)
365 ld r17, VCPU_GPR(R17)(r4)
366 ld r18, VCPU_GPR(R18)(r4)
367 ld r19, VCPU_GPR(R19)(r4)
368 ld r20, VCPU_GPR(R20)(r4)
369 ld r21, VCPU_GPR(R21)(r4)
370 ld r22, VCPU_GPR(R22)(r4)
371 ld r23, VCPU_GPR(R23)(r4)
372 ld r24, VCPU_GPR(R24)(r4)
373 ld r25, VCPU_GPR(R25)(r4)
374 ld r26, VCPU_GPR(R26)(r4)
375 ld r27, VCPU_GPR(R27)(r4)
376 ld r28, VCPU_GPR(R28)(r4)
377 ld r29, VCPU_GPR(R29)(r4)
378 ld r30, VCPU_GPR(R30)(r4)
379 ld r31, VCPU_GPR(R31)(r4)
380
381 BEGIN_FTR_SECTION
382 /* Switch DSCR to guest value */
383 ld r5, VCPU_DSCR(r4)
384 mtspr SPRN_DSCR, r5
385 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
386
387 /*
388 * Set the decrementer to the guest decrementer.
389 */
390 ld r8,VCPU_DEC_EXPIRES(r4)
391 mftb r7
392 subf r3,r7,r8
393 mtspr SPRN_DEC,r3
394 stw r3,VCPU_DEC(r4)
395
396 ld r5, VCPU_SPRG0(r4)
397 ld r6, VCPU_SPRG1(r4)
398 ld r7, VCPU_SPRG2(r4)
399 ld r8, VCPU_SPRG3(r4)
400 mtspr SPRN_SPRG0, r5
401 mtspr SPRN_SPRG1, r6
402 mtspr SPRN_SPRG2, r7
403 mtspr SPRN_SPRG3, r8
404
405 /* Save R1 in the PACA */
406 std r1, HSTATE_HOST_R1(r13)
407
408 /* Increment yield count if they have a VPA */
409 ld r3, VCPU_VPA(r4)
410 cmpdi r3, 0
411 beq 25f
412 lwz r5, LPPACA_YIELDCOUNT(r3)
413 addi r5, r5, 1
414 stw r5, LPPACA_YIELDCOUNT(r3)
415 li r6, 1
416 stb r6, VCPU_VPA_DIRTY(r4)
417 25:
418 /* Load up DAR and DSISR */
419 ld r5, VCPU_DAR(r4)
420 lwz r6, VCPU_DSISR(r4)
421 mtspr SPRN_DAR, r5
422 mtspr SPRN_DSISR, r6
423
424 BEGIN_FTR_SECTION
425 /* Restore AMR and UAMOR, set AMOR to all 1s */
426 ld r5,VCPU_AMR(r4)
427 ld r6,VCPU_UAMOR(r4)
428 li r7,-1
429 mtspr SPRN_AMR,r5
430 mtspr SPRN_UAMOR,r6
431 mtspr SPRN_AMOR,r7
432 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
433
434 /* Clear out SLB */
435 li r6,0
436 slbmte r6,r6
437 slbia
438 ptesync
439
440 BEGIN_FTR_SECTION
441 b 30f
442 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
443 /*
444 * POWER7 host -> guest partition switch code.
445 * We don't have to lock against concurrent tlbies,
446 * but we do have to coordinate across hardware threads.
447 */
448 /* Increment entry count iff exit count is zero. */
449 ld r5,HSTATE_KVM_VCORE(r13)
450 addi r9,r5,VCORE_ENTRY_EXIT
451 21: lwarx r3,0,r9
452 cmpwi r3,0x100 /* any threads starting to exit? */
453 bge secondary_too_late /* if so we're too late to the party */
454 addi r3,r3,1
455 stwcx. r3,0,r9
456 bne 21b
457
458 /* Primary thread switches to guest partition. */
459 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
460 lwz r6,VCPU_PTID(r4)
461 cmpwi r6,0
462 bne 20f
463 ld r6,KVM_SDR1(r9)
464 lwz r7,KVM_LPID(r9)
465 li r0,LPID_RSVD /* switch to reserved LPID */
466 mtspr SPRN_LPID,r0
467 ptesync
468 mtspr SPRN_SDR1,r6 /* switch to partition page table */
469 mtspr SPRN_LPID,r7
470 isync
471
472 /* See if we need to flush the TLB */
473 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
474 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
475 srdi r6,r6,6 /* doubleword number */
476 sldi r6,r6,3 /* address offset */
477 add r6,r6,r9
478 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
479 li r0,1
480 sld r0,r0,r7
481 ld r7,0(r6)
482 and. r7,r7,r0
483 beq 22f
484 23: ldarx r7,0,r6 /* if set, clear the bit */
485 andc r7,r7,r0
486 stdcx. r7,0,r6
487 bne 23b
488 li r6,128 /* and flush the TLB */
489 mtctr r6
490 li r7,0x800 /* IS field = 0b10 */
491 ptesync
492 28: tlbiel r7
493 addi r7,r7,0x1000
494 bdnz 28b
495 ptesync
496
497 /* Add timebase offset onto timebase */
498 22: ld r8,VCORE_TB_OFFSET(r5)
499 cmpdi r8,0
500 beq 37f
501 mftb r6 /* current host timebase */
502 add r8,r8,r6
503 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
504 mftb r7 /* check if lower 24 bits overflowed */
505 clrldi r6,r6,40
506 clrldi r7,r7,40
507 cmpld r7,r6
508 bge 37f
509 addis r8,r8,0x100 /* if so, increment upper 40 bits */
510 mtspr SPRN_TBU40,r8
511
512 37: li r0,1
513 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
514 b 10f
515
516 /* Secondary threads wait for primary to have done partition switch */
517 20: lbz r0,VCORE_IN_GUEST(r5)
518 cmpwi r0,0
519 beq 20b
520
521 /* Set LPCR and RMOR. */
522 10: ld r8,KVM_LPCR(r9)
523 mtspr SPRN_LPCR,r8
524 ld r8,KVM_RMOR(r9)
525 mtspr SPRN_RMOR,r8
526 isync
527
528 /* Check if HDEC expires soon */
529 mfspr r3,SPRN_HDEC
530 cmpwi r3,10
531 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
532 mr r9,r4
533 blt hdec_soon
534
535 /* Save purr/spurr */
536 mfspr r5,SPRN_PURR
537 mfspr r6,SPRN_SPURR
538 std r5,HSTATE_PURR(r13)
539 std r6,HSTATE_SPURR(r13)
540 ld r7,VCPU_PURR(r4)
541 ld r8,VCPU_SPURR(r4)
542 mtspr SPRN_PURR,r7
543 mtspr SPRN_SPURR,r8
544 b 31f
545
546 /*
547 * PPC970 host -> guest partition switch code.
548 * We have to lock against concurrent tlbies,
549 * using native_tlbie_lock to lock against host tlbies
550 * and kvm->arch.tlbie_lock to lock against guest tlbies.
551 * We also have to invalidate the TLB since its
552 * entries aren't tagged with the LPID.
553 */
554 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
555
556 /* first take native_tlbie_lock */
557 .section ".toc","aw"
558 toc_tlbie_lock:
559 .tc native_tlbie_lock[TC],native_tlbie_lock
560 .previous
561 ld r3,toc_tlbie_lock@toc(2)
562 #ifdef __BIG_ENDIAN__
563 lwz r8,PACA_LOCK_TOKEN(r13)
564 #else
565 lwz r8,PACAPACAINDEX(r13)
566 #endif
567 24: lwarx r0,0,r3
568 cmpwi r0,0
569 bne 24b
570 stwcx. r8,0,r3
571 bne 24b
572 isync
573
574 ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */
575 li r0,0x18f
576 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
577 or r0,r7,r0
578 ptesync
579 sync
580 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
581 isync
582 li r0,0
583 stw r0,0(r3) /* drop native_tlbie_lock */
584
585 /* invalidate the whole TLB */
586 li r0,256
587 mtctr r0
588 li r6,0
589 25: tlbiel r6
590 addi r6,r6,0x1000
591 bdnz 25b
592 ptesync
593
594 /* Take the guest's tlbie_lock */
595 addi r3,r9,KVM_TLBIE_LOCK
596 24: lwarx r0,0,r3
597 cmpwi r0,0
598 bne 24b
599 stwcx. r8,0,r3
600 bne 24b
601 isync
602 ld r6,KVM_SDR1(r9)
603 mtspr SPRN_SDR1,r6 /* switch to partition page table */
604
605 /* Set up HID4 with the guest's LPID etc. */
606 sync
607 mtspr SPRN_HID4,r7
608 isync
609
610 /* drop the guest's tlbie_lock */
611 li r0,0
612 stw r0,0(r3)
613
614 /* Check if HDEC expires soon */
615 mfspr r3,SPRN_HDEC
616 cmpwi r3,10
617 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
618 mr r9,r4
619 blt hdec_soon
620
621 /* Enable HDEC interrupts */
622 mfspr r0,SPRN_HID0
623 li r3,1
624 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
625 sync
626 mtspr SPRN_HID0,r0
627 mfspr r0,SPRN_HID0
628 mfspr r0,SPRN_HID0
629 mfspr r0,SPRN_HID0
630 mfspr r0,SPRN_HID0
631 mfspr r0,SPRN_HID0
632 mfspr r0,SPRN_HID0
633
634 /* Load up guest SLB entries */
635 31: lwz r5,VCPU_SLB_MAX(r4)
636 cmpwi r5,0
637 beq 9f
638 mtctr r5
639 addi r6,r4,VCPU_SLB
640 1: ld r8,VCPU_SLB_E(r6)
641 ld r9,VCPU_SLB_V(r6)
642 slbmte r9,r8
643 addi r6,r6,VCPU_SLB_SIZE
644 bdnz 1b
645 9:
646
647 /* Restore state of CTRL run bit; assume 1 on entry */
648 lwz r5,VCPU_CTRL(r4)
649 andi. r5,r5,1
650 bne 4f
651 mfspr r6,SPRN_CTRLF
652 clrrdi r6,r6,1
653 mtspr SPRN_CTRLT,r6
654 4:
655 ld r6, VCPU_CTR(r4)
656 lwz r7, VCPU_XER(r4)
657
658 mtctr r6
659 mtxer r7
660
661 ld r10, VCPU_PC(r4)
662 ld r11, VCPU_MSR(r4)
663 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
664 ld r6, VCPU_SRR0(r4)
665 ld r7, VCPU_SRR1(r4)
666
667 /* r11 = vcpu->arch.msr & ~MSR_HV */
668 rldicl r11, r11, 63 - MSR_HV_LG, 1
669 rotldi r11, r11, 1 + MSR_HV_LG
670 ori r11, r11, MSR_ME
671
672 /* Check if we can deliver an external or decrementer interrupt now */
673 ld r0,VCPU_PENDING_EXC(r4)
674 lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
675 and r0,r0,r8
676 cmpdi cr1,r0,0
677 andi. r0,r11,MSR_EE
678 beq cr1,11f
679 BEGIN_FTR_SECTION
680 mfspr r8,SPRN_LPCR
681 ori r8,r8,LPCR_MER
682 mtspr SPRN_LPCR,r8
683 isync
684 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
685 beq 5f
686 li r0,BOOK3S_INTERRUPT_EXTERNAL
687 12: mr r6,r10
688 mr r10,r0
689 mr r7,r11
690 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
691 rotldi r11,r11,63
692 b 5f
693 11: beq 5f
694 mfspr r0,SPRN_DEC
695 cmpwi r0,0
696 li r0,BOOK3S_INTERRUPT_DECREMENTER
697 blt 12b
698
699 /* Move SRR0 and SRR1 into the respective regs */
700 5: mtspr SPRN_SRR0, r6
701 mtspr SPRN_SRR1, r7
702
703 fast_guest_return:
704 li r0,0
705 stb r0,VCPU_CEDED(r4) /* cancel cede */
706 mtspr SPRN_HSRR0,r10
707 mtspr SPRN_HSRR1,r11
708
709 /* Activate guest mode, so faults get handled by KVM */
710 li r9, KVM_GUEST_MODE_GUEST
711 stb r9, HSTATE_IN_GUEST(r13)
712
713 /* Enter guest */
714
715 BEGIN_FTR_SECTION
716 ld r5, VCPU_CFAR(r4)
717 mtspr SPRN_CFAR, r5
718 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
719
720 ld r5, VCPU_LR(r4)
721 lwz r6, VCPU_CR(r4)
722 mtlr r5
723 mtcr r6
724
725 ld r0, VCPU_GPR(R0)(r4)
726 ld r1, VCPU_GPR(R1)(r4)
727 ld r2, VCPU_GPR(R2)(r4)
728 ld r3, VCPU_GPR(R3)(r4)
729 ld r5, VCPU_GPR(R5)(r4)
730 ld r6, VCPU_GPR(R6)(r4)
731 ld r7, VCPU_GPR(R7)(r4)
732 ld r8, VCPU_GPR(R8)(r4)
733 ld r9, VCPU_GPR(R9)(r4)
734 ld r10, VCPU_GPR(R10)(r4)
735 ld r11, VCPU_GPR(R11)(r4)
736 ld r12, VCPU_GPR(R12)(r4)
737 ld r13, VCPU_GPR(R13)(r4)
738
739 ld r4, VCPU_GPR(R4)(r4)
740
741 hrfid
742 b .
743
744 /******************************************************************************
745 * *
746 * Exit code *
747 * *
748 *****************************************************************************/
749
750 /*
751 * We come here from the first-level interrupt handlers.
752 */
753 .globl kvmppc_interrupt
754 kvmppc_interrupt:
755 /*
756 * Register contents:
757 * R12 = interrupt vector
758 * R13 = PACA
759 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
760 * guest R13 saved in SPRN_SCRATCH0
761 */
762 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
763 std r9, HSTATE_HOST_R2(r13)
764 ld r9, HSTATE_KVM_VCPU(r13)
765
766 /* Save registers */
767
768 std r0, VCPU_GPR(R0)(r9)
769 std r1, VCPU_GPR(R1)(r9)
770 std r2, VCPU_GPR(R2)(r9)
771 std r3, VCPU_GPR(R3)(r9)
772 std r4, VCPU_GPR(R4)(r9)
773 std r5, VCPU_GPR(R5)(r9)
774 std r6, VCPU_GPR(R6)(r9)
775 std r7, VCPU_GPR(R7)(r9)
776 std r8, VCPU_GPR(R8)(r9)
777 ld r0, HSTATE_HOST_R2(r13)
778 std r0, VCPU_GPR(R9)(r9)
779 std r10, VCPU_GPR(R10)(r9)
780 std r11, VCPU_GPR(R11)(r9)
781 ld r3, HSTATE_SCRATCH0(r13)
782 lwz r4, HSTATE_SCRATCH1(r13)
783 std r3, VCPU_GPR(R12)(r9)
784 stw r4, VCPU_CR(r9)
785 BEGIN_FTR_SECTION
786 ld r3, HSTATE_CFAR(r13)
787 std r3, VCPU_CFAR(r9)
788 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
789
790 /* Restore R1/R2 so we can handle faults */
791 ld r1, HSTATE_HOST_R1(r13)
792 ld r2, PACATOC(r13)
793
794 mfspr r10, SPRN_SRR0
795 mfspr r11, SPRN_SRR1
796 std r10, VCPU_SRR0(r9)
797 std r11, VCPU_SRR1(r9)
798 andi. r0, r12, 2 /* need to read HSRR0/1? */
799 beq 1f
800 mfspr r10, SPRN_HSRR0
801 mfspr r11, SPRN_HSRR1
802 clrrdi r12, r12, 2
803 1: std r10, VCPU_PC(r9)
804 std r11, VCPU_MSR(r9)
805
806 GET_SCRATCH0(r3)
807 mflr r4
808 std r3, VCPU_GPR(R13)(r9)
809 std r4, VCPU_LR(r9)
810
811 /* Unset guest mode */
812 li r0, KVM_GUEST_MODE_NONE
813 stb r0, HSTATE_IN_GUEST(r13)
814
815 stw r12,VCPU_TRAP(r9)
816
817 /* Save HEIR (HV emulation assist reg) in last_inst
818 if this is an HEI (HV emulation interrupt, e40) */
819 li r3,KVM_INST_FETCH_FAILED
820 BEGIN_FTR_SECTION
821 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
822 bne 11f
823 mfspr r3,SPRN_HEIR
824 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
825 11: stw r3,VCPU_LAST_INST(r9)
826
827 /* these are volatile across C function calls */
828 mfctr r3
829 mfxer r4
830 std r3, VCPU_CTR(r9)
831 stw r4, VCPU_XER(r9)
832
833 BEGIN_FTR_SECTION
834 /* If this is a page table miss then see if it's theirs or ours */
835 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
836 beq kvmppc_hdsi
837 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
838 beq kvmppc_hisi
839 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
840
841 /* See if this is a leftover HDEC interrupt */
842 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
843 bne 2f
844 mfspr r3,SPRN_HDEC
845 cmpwi r3,0
846 bge ignore_hdec
847 2:
848 /* See if this is an hcall we can handle in real mode */
849 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
850 beq hcall_try_real_mode
851
852 /* Only handle external interrupts here on arch 206 and later */
853 BEGIN_FTR_SECTION
854 b ext_interrupt_to_host
855 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
856
857 /* External interrupt ? */
858 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
859 bne+ ext_interrupt_to_host
860
861 /* External interrupt, first check for host_ipi. If this is
862 * set, we know the host wants us out so let's do it now
863 */
864 do_ext_interrupt:
865 bl kvmppc_read_intr
866 cmpdi r3, 0
867 bgt ext_interrupt_to_host
868
869 /* Allright, looks like an IPI for the guest, we need to set MER */
870 /* Check if any CPU is heading out to the host, if so head out too */
871 ld r5, HSTATE_KVM_VCORE(r13)
872 lwz r0, VCORE_ENTRY_EXIT(r5)
873 cmpwi r0, 0x100
874 bge ext_interrupt_to_host
875
876 /* See if there is a pending interrupt for the guest */
877 mfspr r8, SPRN_LPCR
878 ld r0, VCPU_PENDING_EXC(r9)
879 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
880 rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
881 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
882 beq 2f
883
884 /* And if the guest EE is set, we can deliver immediately, else
885 * we return to the guest with MER set
886 */
887 andi. r0, r11, MSR_EE
888 beq 2f
889 mtspr SPRN_SRR0, r10
890 mtspr SPRN_SRR1, r11
891 li r10, BOOK3S_INTERRUPT_EXTERNAL
892 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
893 rotldi r11, r11, 63
894 2: mr r4, r9
895 mtspr SPRN_LPCR, r8
896 b fast_guest_return
897
898 ext_interrupt_to_host:
899
900 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
901 /* Save more register state */
902 mfdar r6
903 mfdsisr r7
904 std r6, VCPU_DAR(r9)
905 stw r7, VCPU_DSISR(r9)
906 BEGIN_FTR_SECTION
907 /* don't overwrite fault_dar/fault_dsisr if HDSI */
908 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
909 beq 6f
910 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
911 std r6, VCPU_FAULT_DAR(r9)
912 stw r7, VCPU_FAULT_DSISR(r9)
913
914 /* See if it is a machine check */
915 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
916 beq machine_check_realmode
917 mc_cont:
918
919 /* Save guest CTRL register, set runlatch to 1 */
920 6: mfspr r6,SPRN_CTRLF
921 stw r6,VCPU_CTRL(r9)
922 andi. r0,r6,1
923 bne 4f
924 ori r6,r6,1
925 mtspr SPRN_CTRLT,r6
926 4:
927 /* Read the guest SLB and save it away */
928 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
929 mtctr r0
930 li r6,0
931 addi r7,r9,VCPU_SLB
932 li r5,0
933 1: slbmfee r8,r6
934 andis. r0,r8,SLB_ESID_V@h
935 beq 2f
936 add r8,r8,r6 /* put index in */
937 slbmfev r3,r6
938 std r8,VCPU_SLB_E(r7)
939 std r3,VCPU_SLB_V(r7)
940 addi r7,r7,VCPU_SLB_SIZE
941 addi r5,r5,1
942 2: addi r6,r6,1
943 bdnz 1b
944 stw r5,VCPU_SLB_MAX(r9)
945
946 /*
947 * Save the guest PURR/SPURR
948 */
949 BEGIN_FTR_SECTION
950 mfspr r5,SPRN_PURR
951 mfspr r6,SPRN_SPURR
952 ld r7,VCPU_PURR(r9)
953 ld r8,VCPU_SPURR(r9)
954 std r5,VCPU_PURR(r9)
955 std r6,VCPU_SPURR(r9)
956 subf r5,r7,r5
957 subf r6,r8,r6
958
959 /*
960 * Restore host PURR/SPURR and add guest times
961 * so that the time in the guest gets accounted.
962 */
963 ld r3,HSTATE_PURR(r13)
964 ld r4,HSTATE_SPURR(r13)
965 add r3,r3,r5
966 add r4,r4,r6
967 mtspr SPRN_PURR,r3
968 mtspr SPRN_SPURR,r4
969 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
970
971 /* Clear out SLB */
972 li r5,0
973 slbmte r5,r5
974 slbia
975 ptesync
976
977 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
978 BEGIN_FTR_SECTION
979 b 32f
980 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
981 /*
982 * POWER7 guest -> host partition switch code.
983 * We don't have to lock against tlbies but we do
984 * have to coordinate the hardware threads.
985 */
986 /* Increment the threads-exiting-guest count in the 0xff00
987 bits of vcore->entry_exit_count */
988 lwsync
989 ld r5,HSTATE_KVM_VCORE(r13)
990 addi r6,r5,VCORE_ENTRY_EXIT
991 41: lwarx r3,0,r6
992 addi r0,r3,0x100
993 stwcx. r0,0,r6
994 bne 41b
995 lwsync
996
997 /*
998 * At this point we have an interrupt that we have to pass
999 * up to the kernel or qemu; we can't handle it in real mode.
1000 * Thus we have to do a partition switch, so we have to
1001 * collect the other threads, if we are the first thread
1002 * to take an interrupt. To do this, we set the HDEC to 0,
1003 * which causes an HDEC interrupt in all threads within 2ns
1004 * because the HDEC register is shared between all 4 threads.
1005 * However, we don't need to bother if this is an HDEC
1006 * interrupt, since the other threads will already be on their
1007 * way here in that case.
1008 */
1009 cmpwi r3,0x100 /* Are we the first here? */
1010 bge 43f
1011 cmpwi r3,1 /* Are any other threads in the guest? */
1012 ble 43f
1013 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1014 beq 40f
1015 li r0,0
1016 mtspr SPRN_HDEC,r0
1017 40:
1018 /*
1019 * Send an IPI to any napping threads, since an HDEC interrupt
1020 * doesn't wake CPUs up from nap.
1021 */
1022 lwz r3,VCORE_NAPPING_THREADS(r5)
1023 lwz r4,VCPU_PTID(r9)
1024 li r0,1
1025 sld r0,r0,r4
1026 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1027 beq 43f
1028 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1029 subf r6,r4,r13
1030 42: andi. r0,r3,1
1031 beq 44f
1032 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1033 li r0,IPI_PRIORITY
1034 li r7,XICS_MFRR
1035 stbcix r0,r7,r8 /* trigger the IPI */
1036 44: srdi. r3,r3,1
1037 addi r6,r6,PACA_SIZE
1038 bne 42b
1039
1040 /* Secondary threads wait for primary to do partition switch */
1041 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1042 ld r5,HSTATE_KVM_VCORE(r13)
1043 lwz r3,VCPU_PTID(r9)
1044 cmpwi r3,0
1045 beq 15f
1046 HMT_LOW
1047 13: lbz r3,VCORE_IN_GUEST(r5)
1048 cmpwi r3,0
1049 bne 13b
1050 HMT_MEDIUM
1051 b 16f
1052
1053 /* Primary thread waits for all the secondaries to exit guest */
1054 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1055 srwi r0,r3,8
1056 clrldi r3,r3,56
1057 cmpw r3,r0
1058 bne 15b
1059 isync
1060
1061 /* Primary thread switches back to host partition */
1062 ld r6,KVM_HOST_SDR1(r4)
1063 lwz r7,KVM_HOST_LPID(r4)
1064 li r8,LPID_RSVD /* switch to reserved LPID */
1065 mtspr SPRN_LPID,r8
1066 ptesync
1067 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1068 mtspr SPRN_LPID,r7
1069 isync
1070
1071 /* Subtract timebase offset from timebase */
1072 ld r8,VCORE_TB_OFFSET(r5)
1073 cmpdi r8,0
1074 beq 17f
1075 mftb r6 /* current host timebase */
1076 subf r8,r8,r6
1077 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1078 mftb r7 /* check if lower 24 bits overflowed */
1079 clrldi r6,r6,40
1080 clrldi r7,r7,40
1081 cmpld r7,r6
1082 bge 17f
1083 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1084 mtspr SPRN_TBU40,r8
1085
1086 /* Signal secondary CPUs to continue */
1087 17: li r0,0
1088 stb r0,VCORE_IN_GUEST(r5)
1089 lis r8,0x7fff /* MAX_INT@h */
1090 mtspr SPRN_HDEC,r8
1091
1092 16: ld r8,KVM_HOST_LPCR(r4)
1093 mtspr SPRN_LPCR,r8
1094 isync
1095 b 33f
1096
1097 /*
1098 * PPC970 guest -> host partition switch code.
1099 * We have to lock against concurrent tlbies, and
1100 * we have to flush the whole TLB.
1101 */
1102 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
1103
1104 /* Take the guest's tlbie_lock */
1105 #ifdef __BIG_ENDIAN__
1106 lwz r8,PACA_LOCK_TOKEN(r13)
1107 #else
1108 lwz r8,PACAPACAINDEX(r13)
1109 #endif
1110 addi r3,r4,KVM_TLBIE_LOCK
1111 24: lwarx r0,0,r3
1112 cmpwi r0,0
1113 bne 24b
1114 stwcx. r8,0,r3
1115 bne 24b
1116 isync
1117
1118 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1119 li r0,0x18f
1120 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1121 or r0,r7,r0
1122 ptesync
1123 sync
1124 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1125 isync
1126 li r0,0
1127 stw r0,0(r3) /* drop guest tlbie_lock */
1128
1129 /* invalidate the whole TLB */
1130 li r0,256
1131 mtctr r0
1132 li r6,0
1133 25: tlbiel r6
1134 addi r6,r6,0x1000
1135 bdnz 25b
1136 ptesync
1137
1138 /* take native_tlbie_lock */
1139 ld r3,toc_tlbie_lock@toc(2)
1140 24: lwarx r0,0,r3
1141 cmpwi r0,0
1142 bne 24b
1143 stwcx. r8,0,r3
1144 bne 24b
1145 isync
1146
1147 ld r6,KVM_HOST_SDR1(r4)
1148 mtspr SPRN_SDR1,r6 /* switch to host page table */
1149
1150 /* Set up host HID4 value */
1151 sync
1152 mtspr SPRN_HID4,r7
1153 isync
1154 li r0,0
1155 stw r0,0(r3) /* drop native_tlbie_lock */
1156
1157 lis r8,0x7fff /* MAX_INT@h */
1158 mtspr SPRN_HDEC,r8
1159
1160 /* Disable HDEC interrupts */
1161 mfspr r0,SPRN_HID0
1162 li r3,0
1163 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1164 sync
1165 mtspr SPRN_HID0,r0
1166 mfspr r0,SPRN_HID0
1167 mfspr r0,SPRN_HID0
1168 mfspr r0,SPRN_HID0
1169 mfspr r0,SPRN_HID0
1170 mfspr r0,SPRN_HID0
1171 mfspr r0,SPRN_HID0
1172
1173 /* load host SLB entries */
1174 33: ld r8,PACA_SLBSHADOWPTR(r13)
1175
1176 .rept SLB_NUM_BOLTED
1177 ld r5,SLBSHADOW_SAVEAREA(r8)
1178 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1179 andis. r7,r5,SLB_ESID_V@h
1180 beq 1f
1181 slbmte r6,r5
1182 1: addi r8,r8,16
1183 .endr
1184
1185 /* Save DEC */
1186 mfspr r5,SPRN_DEC
1187 mftb r6
1188 extsw r5,r5
1189 add r5,r5,r6
1190 std r5,VCPU_DEC_EXPIRES(r9)
1191
1192 /* Save and reset AMR and UAMOR before turning on the MMU */
1193 BEGIN_FTR_SECTION
1194 mfspr r5,SPRN_AMR
1195 mfspr r6,SPRN_UAMOR
1196 std r5,VCPU_AMR(r9)
1197 std r6,VCPU_UAMOR(r9)
1198 li r6,0
1199 mtspr SPRN_AMR,r6
1200 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1201
1202 /* Switch DSCR back to host value */
1203 BEGIN_FTR_SECTION
1204 mfspr r8, SPRN_DSCR
1205 ld r7, HSTATE_DSCR(r13)
1206 std r8, VCPU_DSCR(r7)
1207 mtspr SPRN_DSCR, r7
1208 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1209
1210 /* Save non-volatile GPRs */
1211 std r14, VCPU_GPR(R14)(r9)
1212 std r15, VCPU_GPR(R15)(r9)
1213 std r16, VCPU_GPR(R16)(r9)
1214 std r17, VCPU_GPR(R17)(r9)
1215 std r18, VCPU_GPR(R18)(r9)
1216 std r19, VCPU_GPR(R19)(r9)
1217 std r20, VCPU_GPR(R20)(r9)
1218 std r21, VCPU_GPR(R21)(r9)
1219 std r22, VCPU_GPR(R22)(r9)
1220 std r23, VCPU_GPR(R23)(r9)
1221 std r24, VCPU_GPR(R24)(r9)
1222 std r25, VCPU_GPR(R25)(r9)
1223 std r26, VCPU_GPR(R26)(r9)
1224 std r27, VCPU_GPR(R27)(r9)
1225 std r28, VCPU_GPR(R28)(r9)
1226 std r29, VCPU_GPR(R29)(r9)
1227 std r30, VCPU_GPR(R30)(r9)
1228 std r31, VCPU_GPR(R31)(r9)
1229
1230 /* Save SPRGs */
1231 mfspr r3, SPRN_SPRG0
1232 mfspr r4, SPRN_SPRG1
1233 mfspr r5, SPRN_SPRG2
1234 mfspr r6, SPRN_SPRG3
1235 std r3, VCPU_SPRG0(r9)
1236 std r4, VCPU_SPRG1(r9)
1237 std r5, VCPU_SPRG2(r9)
1238 std r6, VCPU_SPRG3(r9)
1239
1240 /* save FP state */
1241 mr r3, r9
1242 bl .kvmppc_save_fp
1243
1244 /* Increment yield count if they have a VPA */
1245 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1246 cmpdi r8, 0
1247 beq 25f
1248 lwz r3, LPPACA_YIELDCOUNT(r8)
1249 addi r3, r3, 1
1250 stw r3, LPPACA_YIELDCOUNT(r8)
1251 li r3, 1
1252 stb r3, VCPU_VPA_DIRTY(r9)
1253 25:
1254 /* Save PMU registers if requested */
1255 /* r8 and cr0.eq are live here */
1256 li r3, 1
1257 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1258 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1259 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1260 mfspr r6, SPRN_MMCRA
1261 BEGIN_FTR_SECTION
1262 /* On P7, clear MMCRA in order to disable SDAR updates */
1263 li r7, 0
1264 mtspr SPRN_MMCRA, r7
1265 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1266 isync
1267 beq 21f /* if no VPA, save PMU stuff anyway */
1268 lbz r7, LPPACA_PMCINUSE(r8)
1269 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1270 bne 21f
1271 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1272 b 22f
1273 21: mfspr r5, SPRN_MMCR1
1274 mfspr r7, SPRN_SIAR
1275 mfspr r8, SPRN_SDAR
1276 std r4, VCPU_MMCR(r9)
1277 std r5, VCPU_MMCR + 8(r9)
1278 std r6, VCPU_MMCR + 16(r9)
1279 std r7, VCPU_SIAR(r9)
1280 std r8, VCPU_SDAR(r9)
1281 mfspr r3, SPRN_PMC1
1282 mfspr r4, SPRN_PMC2
1283 mfspr r5, SPRN_PMC3
1284 mfspr r6, SPRN_PMC4
1285 mfspr r7, SPRN_PMC5
1286 mfspr r8, SPRN_PMC6
1287 BEGIN_FTR_SECTION
1288 mfspr r10, SPRN_PMC7
1289 mfspr r11, SPRN_PMC8
1290 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1291 stw r3, VCPU_PMC(r9)
1292 stw r4, VCPU_PMC + 4(r9)
1293 stw r5, VCPU_PMC + 8(r9)
1294 stw r6, VCPU_PMC + 12(r9)
1295 stw r7, VCPU_PMC + 16(r9)
1296 stw r8, VCPU_PMC + 20(r9)
1297 BEGIN_FTR_SECTION
1298 stw r10, VCPU_PMC + 24(r9)
1299 stw r11, VCPU_PMC + 28(r9)
1300 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1301 22:
1302 ld r0, 112+PPC_LR_STKOFF(r1)
1303 addi r1, r1, 112
1304 mtlr r0
1305 blr
1306 secondary_too_late:
1307 ld r5,HSTATE_KVM_VCORE(r13)
1308 HMT_LOW
1309 13: lbz r3,VCORE_IN_GUEST(r5)
1310 cmpwi r3,0
1311 bne 13b
1312 HMT_MEDIUM
1313 li r0, KVM_GUEST_MODE_NONE
1314 stb r0, HSTATE_IN_GUEST(r13)
1315 ld r11,PACA_SLBSHADOWPTR(r13)
1316
1317 .rept SLB_NUM_BOLTED
1318 ld r5,SLBSHADOW_SAVEAREA(r11)
1319 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1320 andis. r7,r5,SLB_ESID_V@h
1321 beq 1f
1322 slbmte r6,r5
1323 1: addi r11,r11,16
1324 .endr
1325 b 22b
1326
1327 /*
1328 * Check whether an HDSI is an HPTE not found fault or something else.
1329 * If it is an HPTE not found fault that is due to the guest accessing
1330 * a page that they have mapped but which we have paged out, then
1331 * we continue on with the guest exit path. In all other cases,
1332 * reflect the HDSI to the guest as a DSI.
1333 */
1334 kvmppc_hdsi:
1335 mfspr r4, SPRN_HDAR
1336 mfspr r6, SPRN_HDSISR
1337 /* HPTE not found fault or protection fault? */
1338 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1339 beq 1f /* if not, send it to the guest */
1340 andi. r0, r11, MSR_DR /* data relocation enabled? */
1341 beq 3f
1342 clrrdi r0, r4, 28
1343 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1344 bne 1f /* if no SLB entry found */
1345 4: std r4, VCPU_FAULT_DAR(r9)
1346 stw r6, VCPU_FAULT_DSISR(r9)
1347
1348 /* Search the hash table. */
1349 mr r3, r9 /* vcpu pointer */
1350 li r7, 1 /* data fault */
1351 bl .kvmppc_hpte_hv_fault
1352 ld r9, HSTATE_KVM_VCPU(r13)
1353 ld r10, VCPU_PC(r9)
1354 ld r11, VCPU_MSR(r9)
1355 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1356 cmpdi r3, 0 /* retry the instruction */
1357 beq 6f
1358 cmpdi r3, -1 /* handle in kernel mode */
1359 beq guest_exit_cont
1360 cmpdi r3, -2 /* MMIO emulation; need instr word */
1361 beq 2f
1362
1363 /* Synthesize a DSI for the guest */
1364 ld r4, VCPU_FAULT_DAR(r9)
1365 mr r6, r3
1366 1: mtspr SPRN_DAR, r4
1367 mtspr SPRN_DSISR, r6
1368 mtspr SPRN_SRR0, r10
1369 mtspr SPRN_SRR1, r11
1370 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1371 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1372 rotldi r11, r11, 63
1373 fast_interrupt_c_return:
1374 6: ld r7, VCPU_CTR(r9)
1375 lwz r8, VCPU_XER(r9)
1376 mtctr r7
1377 mtxer r8
1378 mr r4, r9
1379 b fast_guest_return
1380
1381 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1382 ld r5, KVM_VRMA_SLB_V(r5)
1383 b 4b
1384
1385 /* If this is for emulated MMIO, load the instruction word */
1386 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1387
1388 /* Set guest mode to 'jump over instruction' so if lwz faults
1389 * we'll just continue at the next IP. */
1390 li r0, KVM_GUEST_MODE_SKIP
1391 stb r0, HSTATE_IN_GUEST(r13)
1392
1393 /* Do the access with MSR:DR enabled */
1394 mfmsr r3
1395 ori r4, r3, MSR_DR /* Enable paging for data */
1396 mtmsrd r4
1397 lwz r8, 0(r10)
1398 mtmsrd r3
1399
1400 /* Store the result */
1401 stw r8, VCPU_LAST_INST(r9)
1402
1403 /* Unset guest mode. */
1404 li r0, KVM_GUEST_MODE_NONE
1405 stb r0, HSTATE_IN_GUEST(r13)
1406 b guest_exit_cont
1407
1408 /*
1409 * Similarly for an HISI, reflect it to the guest as an ISI unless
1410 * it is an HPTE not found fault for a page that we have paged out.
1411 */
1412 kvmppc_hisi:
1413 andis. r0, r11, SRR1_ISI_NOPT@h
1414 beq 1f
1415 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1416 beq 3f
1417 clrrdi r0, r10, 28
1418 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1419 bne 1f /* if no SLB entry found */
1420 4:
1421 /* Search the hash table. */
1422 mr r3, r9 /* vcpu pointer */
1423 mr r4, r10
1424 mr r6, r11
1425 li r7, 0 /* instruction fault */
1426 bl .kvmppc_hpte_hv_fault
1427 ld r9, HSTATE_KVM_VCPU(r13)
1428 ld r10, VCPU_PC(r9)
1429 ld r11, VCPU_MSR(r9)
1430 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1431 cmpdi r3, 0 /* retry the instruction */
1432 beq fast_interrupt_c_return
1433 cmpdi r3, -1 /* handle in kernel mode */
1434 beq guest_exit_cont
1435
1436 /* Synthesize an ISI for the guest */
1437 mr r11, r3
1438 1: mtspr SPRN_SRR0, r10
1439 mtspr SPRN_SRR1, r11
1440 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1441 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1442 rotldi r11, r11, 63
1443 b fast_interrupt_c_return
1444
1445 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1446 ld r5, KVM_VRMA_SLB_V(r6)
1447 b 4b
1448
1449 /*
1450 * Try to handle an hcall in real mode.
1451 * Returns to the guest if we handle it, or continues on up to
1452 * the kernel if we can't (i.e. if we don't have a handler for
1453 * it, or if the handler returns H_TOO_HARD).
1454 */
1455 .globl hcall_try_real_mode
1456 hcall_try_real_mode:
1457 ld r3,VCPU_GPR(R3)(r9)
1458 andi. r0,r11,MSR_PR
1459 bne guest_exit_cont
1460 clrrdi r3,r3,2
1461 cmpldi r3,hcall_real_table_end - hcall_real_table
1462 bge guest_exit_cont
1463 LOAD_REG_ADDR(r4, hcall_real_table)
1464 lwax r3,r3,r4
1465 cmpwi r3,0
1466 beq guest_exit_cont
1467 add r3,r3,r4
1468 mtctr r3
1469 mr r3,r9 /* get vcpu pointer */
1470 ld r4,VCPU_GPR(R4)(r9)
1471 bctrl
1472 cmpdi r3,H_TOO_HARD
1473 beq hcall_real_fallback
1474 ld r4,HSTATE_KVM_VCPU(r13)
1475 std r3,VCPU_GPR(R3)(r4)
1476 ld r10,VCPU_PC(r4)
1477 ld r11,VCPU_MSR(r4)
1478 b fast_guest_return
1479
1480 /* We've attempted a real mode hcall, but it's punted it back
1481 * to userspace. We need to restore some clobbered volatiles
1482 * before resuming the pass-it-to-qemu path */
1483 hcall_real_fallback:
1484 li r12,BOOK3S_INTERRUPT_SYSCALL
1485 ld r9, HSTATE_KVM_VCPU(r13)
1486
1487 b guest_exit_cont
1488
1489 .globl hcall_real_table
1490 hcall_real_table:
1491 .long 0 /* 0 - unused */
1492 .long .kvmppc_h_remove - hcall_real_table
1493 .long .kvmppc_h_enter - hcall_real_table
1494 .long .kvmppc_h_read - hcall_real_table
1495 .long 0 /* 0x10 - H_CLEAR_MOD */
1496 .long 0 /* 0x14 - H_CLEAR_REF */
1497 .long .kvmppc_h_protect - hcall_real_table
1498 .long 0 /* 0x1c - H_GET_TCE */
1499 .long .kvmppc_h_put_tce - hcall_real_table
1500 .long 0 /* 0x24 - H_SET_SPRG0 */
1501 .long .kvmppc_h_set_dabr - hcall_real_table
1502 .long 0 /* 0x2c */
1503 .long 0 /* 0x30 */
1504 .long 0 /* 0x34 */
1505 .long 0 /* 0x38 */
1506 .long 0 /* 0x3c */
1507 .long 0 /* 0x40 */
1508 .long 0 /* 0x44 */
1509 .long 0 /* 0x48 */
1510 .long 0 /* 0x4c */
1511 .long 0 /* 0x50 */
1512 .long 0 /* 0x54 */
1513 .long 0 /* 0x58 */
1514 .long 0 /* 0x5c */
1515 .long 0 /* 0x60 */
1516 #ifdef CONFIG_KVM_XICS
1517 .long .kvmppc_rm_h_eoi - hcall_real_table
1518 .long .kvmppc_rm_h_cppr - hcall_real_table
1519 .long .kvmppc_rm_h_ipi - hcall_real_table
1520 .long 0 /* 0x70 - H_IPOLL */
1521 .long .kvmppc_rm_h_xirr - hcall_real_table
1522 #else
1523 .long 0 /* 0x64 - H_EOI */
1524 .long 0 /* 0x68 - H_CPPR */
1525 .long 0 /* 0x6c - H_IPI */
1526 .long 0 /* 0x70 - H_IPOLL */
1527 .long 0 /* 0x74 - H_XIRR */
1528 #endif
1529 .long 0 /* 0x78 */
1530 .long 0 /* 0x7c */
1531 .long 0 /* 0x80 */
1532 .long 0 /* 0x84 */
1533 .long 0 /* 0x88 */
1534 .long 0 /* 0x8c */
1535 .long 0 /* 0x90 */
1536 .long 0 /* 0x94 */
1537 .long 0 /* 0x98 */
1538 .long 0 /* 0x9c */
1539 .long 0 /* 0xa0 */
1540 .long 0 /* 0xa4 */
1541 .long 0 /* 0xa8 */
1542 .long 0 /* 0xac */
1543 .long 0 /* 0xb0 */
1544 .long 0 /* 0xb4 */
1545 .long 0 /* 0xb8 */
1546 .long 0 /* 0xbc */
1547 .long 0 /* 0xc0 */
1548 .long 0 /* 0xc4 */
1549 .long 0 /* 0xc8 */
1550 .long 0 /* 0xcc */
1551 .long 0 /* 0xd0 */
1552 .long 0 /* 0xd4 */
1553 .long 0 /* 0xd8 */
1554 .long 0 /* 0xdc */
1555 .long .kvmppc_h_cede - hcall_real_table
1556 .long 0 /* 0xe4 */
1557 .long 0 /* 0xe8 */
1558 .long 0 /* 0xec */
1559 .long 0 /* 0xf0 */
1560 .long 0 /* 0xf4 */
1561 .long 0 /* 0xf8 */
1562 .long 0 /* 0xfc */
1563 .long 0 /* 0x100 */
1564 .long 0 /* 0x104 */
1565 .long 0 /* 0x108 */
1566 .long 0 /* 0x10c */
1567 .long 0 /* 0x110 */
1568 .long 0 /* 0x114 */
1569 .long 0 /* 0x118 */
1570 .long 0 /* 0x11c */
1571 .long 0 /* 0x120 */
1572 .long .kvmppc_h_bulk_remove - hcall_real_table
1573 hcall_real_table_end:
1574
1575 ignore_hdec:
1576 mr r4,r9
1577 b fast_guest_return
1578
1579 _GLOBAL(kvmppc_h_set_dabr)
1580 std r4,VCPU_DABR(r3)
1581 /* Work around P7 bug where DABR can get corrupted on mtspr */
1582 1: mtspr SPRN_DABR,r4
1583 mfspr r5, SPRN_DABR
1584 cmpd r4, r5
1585 bne 1b
1586 isync
1587 li r3,0
1588 blr
1589
1590 _GLOBAL(kvmppc_h_cede)
1591 ori r11,r11,MSR_EE
1592 std r11,VCPU_MSR(r3)
1593 li r0,1
1594 stb r0,VCPU_CEDED(r3)
1595 sync /* order setting ceded vs. testing prodded */
1596 lbz r5,VCPU_PRODDED(r3)
1597 cmpwi r5,0
1598 bne kvm_cede_prodded
1599 li r0,0 /* set trap to 0 to say hcall is handled */
1600 stw r0,VCPU_TRAP(r3)
1601 li r0,H_SUCCESS
1602 std r0,VCPU_GPR(R3)(r3)
1603 BEGIN_FTR_SECTION
1604 b kvm_cede_exit /* just send it up to host on 970 */
1605 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1606
1607 /*
1608 * Set our bit in the bitmask of napping threads unless all the
1609 * other threads are already napping, in which case we send this
1610 * up to the host.
1611 */
1612 ld r5,HSTATE_KVM_VCORE(r13)
1613 lwz r6,VCPU_PTID(r3)
1614 lwz r8,VCORE_ENTRY_EXIT(r5)
1615 clrldi r8,r8,56
1616 li r0,1
1617 sld r0,r0,r6
1618 addi r6,r5,VCORE_NAPPING_THREADS
1619 31: lwarx r4,0,r6
1620 or r4,r4,r0
1621 PPC_POPCNTW(R7,R4)
1622 cmpw r7,r8
1623 bge kvm_cede_exit
1624 stwcx. r4,0,r6
1625 bne 31b
1626 li r0,1
1627 stb r0,HSTATE_NAPPING(r13)
1628 /* order napping_threads update vs testing entry_exit_count */
1629 lwsync
1630 mr r4,r3
1631 lwz r7,VCORE_ENTRY_EXIT(r5)
1632 cmpwi r7,0x100
1633 bge 33f /* another thread already exiting */
1634
1635 /*
1636 * Although not specifically required by the architecture, POWER7
1637 * preserves the following registers in nap mode, even if an SMT mode
1638 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1639 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1640 */
1641 /* Save non-volatile GPRs */
1642 std r14, VCPU_GPR(R14)(r3)
1643 std r15, VCPU_GPR(R15)(r3)
1644 std r16, VCPU_GPR(R16)(r3)
1645 std r17, VCPU_GPR(R17)(r3)
1646 std r18, VCPU_GPR(R18)(r3)
1647 std r19, VCPU_GPR(R19)(r3)
1648 std r20, VCPU_GPR(R20)(r3)
1649 std r21, VCPU_GPR(R21)(r3)
1650 std r22, VCPU_GPR(R22)(r3)
1651 std r23, VCPU_GPR(R23)(r3)
1652 std r24, VCPU_GPR(R24)(r3)
1653 std r25, VCPU_GPR(R25)(r3)
1654 std r26, VCPU_GPR(R26)(r3)
1655 std r27, VCPU_GPR(R27)(r3)
1656 std r28, VCPU_GPR(R28)(r3)
1657 std r29, VCPU_GPR(R29)(r3)
1658 std r30, VCPU_GPR(R30)(r3)
1659 std r31, VCPU_GPR(R31)(r3)
1660
1661 /* save FP state */
1662 bl .kvmppc_save_fp
1663
1664 /*
1665 * Take a nap until a decrementer or external interrupt occurs,
1666 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1667 */
1668 li r0,1
1669 stb r0,HSTATE_HWTHREAD_REQ(r13)
1670 mfspr r5,SPRN_LPCR
1671 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1672 mtspr SPRN_LPCR,r5
1673 isync
1674 li r0, 0
1675 std r0, HSTATE_SCRATCH0(r13)
1676 ptesync
1677 ld r0, HSTATE_SCRATCH0(r13)
1678 1: cmpd r0, r0
1679 bne 1b
1680 nap
1681 b .
1682
1683 kvm_end_cede:
1684 /* get vcpu pointer */
1685 ld r4, HSTATE_KVM_VCPU(r13)
1686
1687 /* Woken by external or decrementer interrupt */
1688 ld r1, HSTATE_HOST_R1(r13)
1689
1690 /* load up FP state */
1691 bl kvmppc_load_fp
1692
1693 /* Load NV GPRS */
1694 ld r14, VCPU_GPR(R14)(r4)
1695 ld r15, VCPU_GPR(R15)(r4)
1696 ld r16, VCPU_GPR(R16)(r4)
1697 ld r17, VCPU_GPR(R17)(r4)
1698 ld r18, VCPU_GPR(R18)(r4)
1699 ld r19, VCPU_GPR(R19)(r4)
1700 ld r20, VCPU_GPR(R20)(r4)
1701 ld r21, VCPU_GPR(R21)(r4)
1702 ld r22, VCPU_GPR(R22)(r4)
1703 ld r23, VCPU_GPR(R23)(r4)
1704 ld r24, VCPU_GPR(R24)(r4)
1705 ld r25, VCPU_GPR(R25)(r4)
1706 ld r26, VCPU_GPR(R26)(r4)
1707 ld r27, VCPU_GPR(R27)(r4)
1708 ld r28, VCPU_GPR(R28)(r4)
1709 ld r29, VCPU_GPR(R29)(r4)
1710 ld r30, VCPU_GPR(R30)(r4)
1711 ld r31, VCPU_GPR(R31)(r4)
1712
1713 /* clear our bit in vcore->napping_threads */
1714 33: ld r5,HSTATE_KVM_VCORE(r13)
1715 lwz r3,VCPU_PTID(r4)
1716 li r0,1
1717 sld r0,r0,r3
1718 addi r6,r5,VCORE_NAPPING_THREADS
1719 32: lwarx r7,0,r6
1720 andc r7,r7,r0
1721 stwcx. r7,0,r6
1722 bne 32b
1723 li r0,0
1724 stb r0,HSTATE_NAPPING(r13)
1725
1726 /* Check the wake reason in SRR1 to see why we got here */
1727 mfspr r3, SPRN_SRR1
1728 rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */
1729 cmpwi r3, 4 /* was it an external interrupt? */
1730 li r12, BOOK3S_INTERRUPT_EXTERNAL
1731 mr r9, r4
1732 ld r10, VCPU_PC(r9)
1733 ld r11, VCPU_MSR(r9)
1734 beq do_ext_interrupt /* if so */
1735
1736 /* see if any other thread is already exiting */
1737 lwz r0,VCORE_ENTRY_EXIT(r5)
1738 cmpwi r0,0x100
1739 blt kvmppc_cede_reentry /* if not go back to guest */
1740
1741 /* some threads are exiting, so go to the guest exit path */
1742 b hcall_real_fallback
1743
1744 /* cede when already previously prodded case */
1745 kvm_cede_prodded:
1746 li r0,0
1747 stb r0,VCPU_PRODDED(r3)
1748 sync /* order testing prodded vs. clearing ceded */
1749 stb r0,VCPU_CEDED(r3)
1750 li r3,H_SUCCESS
1751 blr
1752
1753 /* we've ceded but we want to give control to the host */
1754 kvm_cede_exit:
1755 b hcall_real_fallback
1756
1757 /* Try to handle a machine check in real mode */
1758 machine_check_realmode:
1759 mr r3, r9 /* get vcpu pointer */
1760 bl .kvmppc_realmode_machine_check
1761 nop
1762 cmpdi r3, 0 /* continue exiting from guest? */
1763 ld r9, HSTATE_KVM_VCPU(r13)
1764 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1765 beq mc_cont
1766 /* If not, deliver a machine check. SRR0/1 are already set */
1767 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
1768 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1769 rotldi r11, r11, 63
1770 b fast_interrupt_c_return
1771
1772 /*
1773 * Determine what sort of external interrupt is pending (if any).
1774 * Returns:
1775 * 0 if no interrupt is pending
1776 * 1 if an interrupt is pending that needs to be handled by the host
1777 * -1 if there was a guest wakeup IPI (which has now been cleared)
1778 */
1779 kvmppc_read_intr:
1780 /* see if a host IPI is pending */
1781 li r3, 1
1782 lbz r0, HSTATE_HOST_IPI(r13)
1783 cmpwi r0, 0
1784 bne 1f
1785
1786 /* Now read the interrupt from the ICP */
1787 ld r6, HSTATE_XICS_PHYS(r13)
1788 li r7, XICS_XIRR
1789 cmpdi r6, 0
1790 beq- 1f
1791 lwzcix r0, r6, r7
1792 rlwinm. r3, r0, 0, 0xffffff
1793 sync
1794 beq 1f /* if nothing pending in the ICP */
1795
1796 /* We found something in the ICP...
1797 *
1798 * If it's not an IPI, stash it in the PACA and return to
1799 * the host, we don't (yet) handle directing real external
1800 * interrupts directly to the guest
1801 */
1802 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
1803 li r3, 1
1804 bne 42f
1805
1806 /* It's an IPI, clear the MFRR and EOI it */
1807 li r3, 0xff
1808 li r8, XICS_MFRR
1809 stbcix r3, r6, r8 /* clear the IPI */
1810 stwcix r0, r6, r7 /* EOI it */
1811 sync
1812
1813 /* We need to re-check host IPI now in case it got set in the
1814 * meantime. If it's clear, we bounce the interrupt to the
1815 * guest
1816 */
1817 lbz r0, HSTATE_HOST_IPI(r13)
1818 cmpwi r0, 0
1819 bne- 43f
1820
1821 /* OK, it's an IPI for us */
1822 li r3, -1
1823 1: blr
1824
1825 42: /* It's not an IPI and it's for the host, stash it in the PACA
1826 * before exit, it will be picked up by the host ICP driver
1827 */
1828 stw r0, HSTATE_SAVED_XIRR(r13)
1829 b 1b
1830
1831 43: /* We raced with the host, we need to resend that IPI, bummer */
1832 li r0, IPI_PRIORITY
1833 stbcix r0, r6, r8 /* set the IPI */
1834 sync
1835 b 1b
1836
1837 /*
1838 * Save away FP, VMX and VSX registers.
1839 * r3 = vcpu pointer
1840 */
1841 _GLOBAL(kvmppc_save_fp)
1842 mfmsr r5
1843 ori r8,r5,MSR_FP
1844 #ifdef CONFIG_ALTIVEC
1845 BEGIN_FTR_SECTION
1846 oris r8,r8,MSR_VEC@h
1847 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1848 #endif
1849 #ifdef CONFIG_VSX
1850 BEGIN_FTR_SECTION
1851 oris r8,r8,MSR_VSX@h
1852 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1853 #endif
1854 mtmsrd r8
1855 isync
1856 #ifdef CONFIG_VSX
1857 BEGIN_FTR_SECTION
1858 reg = 0
1859 .rept 32
1860 li r6,reg*16+VCPU_VSRS
1861 STXVD2X(reg,R6,R3)
1862 reg = reg + 1
1863 .endr
1864 FTR_SECTION_ELSE
1865 #endif
1866 reg = 0
1867 .rept 32
1868 stfd reg,reg*8+VCPU_FPRS(r3)
1869 reg = reg + 1
1870 .endr
1871 #ifdef CONFIG_VSX
1872 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1873 #endif
1874 mffs fr0
1875 stfd fr0,VCPU_FPSCR(r3)
1876
1877 #ifdef CONFIG_ALTIVEC
1878 BEGIN_FTR_SECTION
1879 reg = 0
1880 .rept 32
1881 li r6,reg*16+VCPU_VRS
1882 stvx reg,r6,r3
1883 reg = reg + 1
1884 .endr
1885 mfvscr vr0
1886 li r6,VCPU_VSCR
1887 stvx vr0,r6,r3
1888 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1889 #endif
1890 mfspr r6,SPRN_VRSAVE
1891 stw r6,VCPU_VRSAVE(r3)
1892 mtmsrd r5
1893 isync
1894 blr
1895
1896 /*
1897 * Load up FP, VMX and VSX registers
1898 * r4 = vcpu pointer
1899 */
1900 .globl kvmppc_load_fp
1901 kvmppc_load_fp:
1902 mfmsr r9
1903 ori r8,r9,MSR_FP
1904 #ifdef CONFIG_ALTIVEC
1905 BEGIN_FTR_SECTION
1906 oris r8,r8,MSR_VEC@h
1907 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1908 #endif
1909 #ifdef CONFIG_VSX
1910 BEGIN_FTR_SECTION
1911 oris r8,r8,MSR_VSX@h
1912 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1913 #endif
1914 mtmsrd r8
1915 isync
1916 lfd fr0,VCPU_FPSCR(r4)
1917 MTFSF_L(fr0)
1918 #ifdef CONFIG_VSX
1919 BEGIN_FTR_SECTION
1920 reg = 0
1921 .rept 32
1922 li r7,reg*16+VCPU_VSRS
1923 LXVD2X(reg,R7,R4)
1924 reg = reg + 1
1925 .endr
1926 FTR_SECTION_ELSE
1927 #endif
1928 reg = 0
1929 .rept 32
1930 lfd reg,reg*8+VCPU_FPRS(r4)
1931 reg = reg + 1
1932 .endr
1933 #ifdef CONFIG_VSX
1934 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1935 #endif
1936
1937 #ifdef CONFIG_ALTIVEC
1938 BEGIN_FTR_SECTION
1939 li r7,VCPU_VSCR
1940 lvx vr0,r7,r4
1941 mtvscr vr0
1942 reg = 0
1943 .rept 32
1944 li r7,reg*16+VCPU_VRS
1945 lvx reg,r7,r4
1946 reg = reg + 1
1947 .endr
1948 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1949 #endif
1950 lwz r7,VCPU_VRSAVE(r4)
1951 mtspr SPRN_VRSAVE,r7
1952 blr
Linux kernel - Deliverables
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