arch/powerpc/kvm/bookehv_interrupts.S

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, write to the Free Software
  13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  14  *
  15  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  16  *
  17  * Author: Varun Sethi <varun.sethi@freescale.com>
  18  * Author: Scott Wood <scotwood@freescale.com>
  19  *
  20  * This file is derived from arch/powerpc/kvm/booke_interrupts.S
  21  */
  22
  23 #include <asm/ppc_asm.h>
  24 #include <asm/kvm_asm.h>
  25 #include <asm/reg.h>
  26 #include <asm/mmu-44x.h>
  27 #include <asm/page.h>
  28 #include <asm/asm-compat.h>
  29 #include <asm/asm-offsets.h>
  30 #include <asm/bitsperlong.h>
  31 #include <asm/thread_info.h>
  32
  33 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
  34
  35 #define GET_VCPU(vcpu, thread)  \
  36         PPC_LL  vcpu, THREAD_KVM_VCPU(thread)
  37
  38 #define SET_VCPU(vcpu)          \
  39         PPC_STL vcpu, (THREAD + THREAD_KVM_VCPU)(r2)
  40
  41 #define LONGBYTES               (BITS_PER_LONG / 8)
  42
  43 #define VCPU_GPR(n)             (VCPU_GPRS + (n * LONGBYTES))
  44 #define VCPU_GUEST_SPRG(n)      (VCPU_GUEST_SPRGS + (n * LONGBYTES))
  45
  46 /* The host stack layout: */
  47 #define HOST_R1         (0 * LONGBYTES) /* Implied by stwu. */
  48 #define HOST_CALLEE_LR  (1 * LONGBYTES)
  49 #define HOST_RUN        (2 * LONGBYTES) /* struct kvm_run */
  50 /*
  51  * r2 is special: it holds 'current', and it made nonvolatile in the
  52  * kernel with the -ffixed-r2 gcc option.
  53  */
  54 #define HOST_R2         (3 * LONGBYTES)
  55 #define HOST_NV_GPRS    (4 * LONGBYTES)
  56 #define HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
  57 #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
  58 #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
  59 #define HOST_STACK_LR   (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
  60
  61 #define NEED_EMU                0x00000001 /* emulation -- save nv regs */
  62 #define NEED_DEAR               0x00000002 /* save faulting DEAR */
  63 #define NEED_ESR                0x00000004 /* save faulting ESR */
  64
  65 /*
  66  * On entry:
  67  * r4 = vcpu, r5 = srr0, r6 = srr1
  68  * saved in vcpu: cr, ctr, r3-r13
  69  */
  70 .macro kvm_handler_common intno, srr0, flags
  71         /* Restore host stack pointer */
  72         PPC_STL r1, VCPU_GPR(r1)(r4)
  73         PPC_STL r2, VCPU_GPR(r2)(r4)
  74         PPC_LL  r1, VCPU_HOST_STACK(r4)
  75         PPC_LL  r2, HOST_R2(r1)
  76
  77         mfspr   r10, SPRN_PID
  78         lwz     r8, VCPU_HOST_PID(r4)
  79         PPC_LL  r11, VCPU_SHARED(r4)
  80         PPC_STL r14, VCPU_GPR(r14)(r4) /* We need a non-volatile GPR. */
  81         li      r14, \intno
  82
  83         stw     r10, VCPU_GUEST_PID(r4)
  84         mtspr   SPRN_PID, r8
  85
  86 #ifdef CONFIG_KVM_EXIT_TIMING
  87         /* save exit time */
  88 1:      mfspr   r7, SPRN_TBRU
  89         mfspr   r8, SPRN_TBRL
  90         mfspr   r9, SPRN_TBRU
  91         cmpw    r9, r7
  92         PPC_STL r8, VCPU_TIMING_EXIT_TBL(r4)
  93         bne-    1b
  94         PPC_STL r9, VCPU_TIMING_EXIT_TBU(r4)
  95 #endif
  96
  97         .if     \flags & NEED_EMU
  98         lwz     r9, VCPU_KVM(r4)
  99         .endif
 100
 101         oris    r8, r6, MSR_CE@h
 102 #ifdef CONFIG_64BIT
 103         std     r6, (VCPU_SHARED_MSR)(r11)
 104 #else
 105         stw     r6, (VCPU_SHARED_MSR + 4)(r11)
 106 #endif
 107         ori     r8, r8, MSR_ME | MSR_RI
 108         PPC_STL r5, VCPU_PC(r4)
 109
 110         /*
 111          * Make sure CE/ME/RI are set (if appropriate for exception type)
 112          * whether or not the guest had it set.  Since mfmsr/mtmsr are
 113          * somewhat expensive, skip in the common case where the guest
 114          * had all these bits set (and thus they're still set if
 115          * appropriate for the exception type).
 116          */
 117         cmpw    r6, r8
 118         .if     \flags & NEED_EMU
 119         lwz     r9, KVM_LPID(r9)
 120         .endif
 121         beq     1f
 122         mfmsr   r7
 123         .if     \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
 124         oris    r7, r7, MSR_CE@h
 125         .endif
 126         .if     \srr0 != SPRN_MCSRR0
 127         ori     r7, r7, MSR_ME | MSR_RI
 128         .endif
 129         mtmsr   r7
 130 1:
 131
 132         .if     \flags & NEED_EMU
 133         /*
 134          * This assumes you have external PID support.
 135          * To support a bookehv CPU without external PID, you'll
 136          * need to look up the TLB entry and create a temporary mapping.
 137          *
 138          * FIXME: we don't currently handle if the lwepx faults.  PR-mode
 139          * booke doesn't handle it either.  Since Linux doesn't use
 140          * broadcast tlbivax anymore, the only way this should happen is
 141          * if the guest maps its memory execute-but-not-read, or if we
 142          * somehow take a TLB miss in the middle of this entry code and
 143          * evict the relevant entry.  On e500mc, all kernel lowmem is
 144          * bolted into TLB1 large page mappings, and we don't use
 145          * broadcast invalidates, so we should not take a TLB miss here.
 146          *
 147          * Later we'll need to deal with faults here.  Disallowing guest
 148          * mappings that are execute-but-not-read could be an option on
 149          * e500mc, but not on chips with an LRAT if it is used.
 150          */
 151
 152         mfspr   r3, SPRN_EPLC   /* will already have correct ELPID and EGS */
 153         PPC_STL r15, VCPU_GPR(r15)(r4)
 154         PPC_STL r16, VCPU_GPR(r16)(r4)
 155         PPC_STL r17, VCPU_GPR(r17)(r4)
 156         PPC_STL r18, VCPU_GPR(r18)(r4)
 157         PPC_STL r19, VCPU_GPR(r19)(r4)
 158         mr      r8, r3
 159         PPC_STL r20, VCPU_GPR(r20)(r4)
 160         rlwimi  r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
 161         PPC_STL r21, VCPU_GPR(r21)(r4)
 162         rlwimi  r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
 163         PPC_STL r22, VCPU_GPR(r22)(r4)
 164         rlwimi  r8, r10, EPC_EPID_SHIFT, EPC_EPID
 165         PPC_STL r23, VCPU_GPR(r23)(r4)
 166         PPC_STL r24, VCPU_GPR(r24)(r4)
 167         PPC_STL r25, VCPU_GPR(r25)(r4)
 168         PPC_STL r26, VCPU_GPR(r26)(r4)
 169         PPC_STL r27, VCPU_GPR(r27)(r4)
 170         PPC_STL r28, VCPU_GPR(r28)(r4)
 171         PPC_STL r29, VCPU_GPR(r29)(r4)
 172         PPC_STL r30, VCPU_GPR(r30)(r4)
 173         PPC_STL r31, VCPU_GPR(r31)(r4)
 174         mtspr   SPRN_EPLC, r8
 175
 176         /* disable preemption, so we are sure we hit the fixup handler */
 177 #ifdef CONFIG_PPC64
 178         clrrdi  r8,r1,THREAD_SHIFT
 179 #else
 180         rlwinm  r8,r1,0,0,31-THREAD_SHIFT       /* current thread_info */
 181 #endif
 182         li      r7, 1
 183         stw     r7, TI_PREEMPT(r8)
 184
 185         isync
 186
 187         /*
 188          * In case the read goes wrong, we catch it and write an invalid value
 189          * in LAST_INST instead.
 190          */
 191 1:      lwepx   r9, 0, r5
 192 2:
 193 .section .fixup, "ax"
 194 3:      li      r9, KVM_INST_FETCH_FAILED
 195         b       2b
 196 .previous
 197 .section __ex_table,"a"
 198         PPC_LONG_ALIGN
 199         PPC_LONG 1b,3b
 200 .previous
 201
 202         mtspr   SPRN_EPLC, r3
 203         li      r7, 0
 204         stw     r7, TI_PREEMPT(r8)
 205         stw     r9, VCPU_LAST_INST(r4)
 206         .endif
 207
 208         .if     \flags & NEED_ESR
 209         mfspr   r8, SPRN_ESR
 210         PPC_STL r8, VCPU_FAULT_ESR(r4)
 211         .endif
 212
 213         .if     \flags & NEED_DEAR
 214         mfspr   r9, SPRN_DEAR
 215         PPC_STL r9, VCPU_FAULT_DEAR(r4)
 216         .endif
 217
 218         b       kvmppc_resume_host
 219 .endm
 220
 221 /*
 222  * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
 223  */
 224 .macro kvm_handler intno srr0, srr1, flags
 225 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 226         GET_VCPU(r11, r10)
 227         PPC_STL r3, VCPU_GPR(r3)(r11)
 228         mfspr   r3, SPRN_SPRG_RSCRATCH0
 229         PPC_STL r4, VCPU_GPR(r4)(r11)
 230         PPC_LL  r4, THREAD_NORMSAVE(0)(r10)
 231         PPC_STL r5, VCPU_GPR(r5)(r11)
 232         PPC_STL r13, VCPU_CR(r11)
 233         mfspr   r5, \srr0
 234         PPC_STL r3, VCPU_GPR(r10)(r11)
 235         PPC_LL  r3, THREAD_NORMSAVE(2)(r10)
 236         PPC_STL r6, VCPU_GPR(r6)(r11)
 237         PPC_STL r4, VCPU_GPR(r11)(r11)
 238         mfspr   r6, \srr1
 239         PPC_STL r7, VCPU_GPR(r7)(r11)
 240         PPC_STL r8, VCPU_GPR(r8)(r11)
 241         PPC_STL r9, VCPU_GPR(r9)(r11)
 242         PPC_STL r3, VCPU_GPR(r13)(r11)
 243         mfctr   r7
 244         PPC_STL r12, VCPU_GPR(r12)(r11)
 245         PPC_STL r7, VCPU_CTR(r11)
 246         mr      r4, r11
 247         kvm_handler_common \intno, \srr0, \flags
 248 .endm
 249
 250 .macro kvm_lvl_handler intno scratch srr0, srr1, flags
 251 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 252         mfspr   r10, SPRN_SPRG_THREAD
 253         GET_VCPU(r11, r10)
 254         PPC_STL r3, VCPU_GPR(r3)(r11)
 255         mfspr   r3, \scratch
 256         PPC_STL r4, VCPU_GPR(r4)(r11)
 257         PPC_LL  r4, GPR9(r8)
 258         PPC_STL r5, VCPU_GPR(r5)(r11)
 259         PPC_STL r9, VCPU_CR(r11)
 260         mfspr   r5, \srr0
 261         PPC_STL r3, VCPU_GPR(r8)(r11)
 262         PPC_LL  r3, GPR10(r8)
 263         PPC_STL r6, VCPU_GPR(r6)(r11)
 264         PPC_STL r4, VCPU_GPR(r9)(r11)
 265         mfspr   r6, \srr1
 266         PPC_LL  r4, GPR11(r8)
 267         PPC_STL r7, VCPU_GPR(r7)(r11)
 268         PPC_STL r8, VCPU_GPR(r8)(r11)
 269         PPC_STL r3, VCPU_GPR(r10)(r11)
 270         mfctr   r7
 271         PPC_STL r12, VCPU_GPR(r12)(r11)
 272         PPC_STL r4, VCPU_GPR(r11)(r11)
 273         PPC_STL r7, VCPU_CTR(r11)
 274         mr      r4, r11
 275         kvm_handler_common \intno, \srr0, \flags
 276 .endm
 277
 278 kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
 279         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 280 kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
 281         SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
 282 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
 283         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR)
 284 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
 285 kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
 286 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
 287         SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
 288 kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
 289 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 290 kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
 291 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 292 kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
 293 kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
 294 kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
 295         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 296 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
 297         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 298 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
 299 kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 300 kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
 301 kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
 302 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
 303 kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
 304 kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
 305         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 306 kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
 307 kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
 308 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
 309 kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
 310         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 311 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 312         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 313 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 314         SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
 315
 316
 317 /* Registers:
 318  *  SPRG_SCRATCH0: guest r10
 319  *  r4: vcpu pointer
 320  *  r11: vcpu->arch.shared
 321  *  r14: KVM exit number
 322  */
 323 _GLOBAL(kvmppc_resume_host)
 324         /* Save remaining volatile guest register state to vcpu. */
 325         mfspr   r3, SPRN_VRSAVE
 326         PPC_STL r0, VCPU_GPR(r0)(r4)
 327         mflr    r5
 328         mfspr   r6, SPRN_SPRG4
 329         PPC_STL r5, VCPU_LR(r4)
 330         mfspr   r7, SPRN_SPRG5
 331         PPC_STL r3, VCPU_VRSAVE(r4)
 332         PPC_STL r6, VCPU_SHARED_SPRG4(r11)
 333         mfspr   r8, SPRN_SPRG6
 334         PPC_STL r7, VCPU_SHARED_SPRG5(r11)
 335         mfspr   r9, SPRN_SPRG7
 336         PPC_STL r8, VCPU_SHARED_SPRG6(r11)
 337         mfxer   r3
 338         PPC_STL r9, VCPU_SHARED_SPRG7(r11)
 339
 340         /* save guest MAS registers and restore host mas4 & mas6 */
 341         mfspr   r5, SPRN_MAS0
 342         PPC_STL r3, VCPU_XER(r4)
 343         mfspr   r6, SPRN_MAS1
 344         stw     r5, VCPU_SHARED_MAS0(r11)
 345         mfspr   r7, SPRN_MAS2
 346         stw     r6, VCPU_SHARED_MAS1(r11)
 347 #ifdef CONFIG_64BIT
 348         std     r7, (VCPU_SHARED_MAS2)(r11)
 349 #else
 350         stw     r7, (VCPU_SHARED_MAS2 + 4)(r11)
 351 #endif
 352         mfspr   r5, SPRN_MAS3
 353         mfspr   r6, SPRN_MAS4
 354         stw     r5, VCPU_SHARED_MAS7_3+4(r11)
 355         mfspr   r7, SPRN_MAS6
 356         stw     r6, VCPU_SHARED_MAS4(r11)
 357         mfspr   r5, SPRN_MAS7
 358         lwz     r6, VCPU_HOST_MAS4(r4)
 359         stw     r7, VCPU_SHARED_MAS6(r11)
 360         lwz     r8, VCPU_HOST_MAS6(r4)
 361         mtspr   SPRN_MAS4, r6
 362         stw     r5, VCPU_SHARED_MAS7_3+0(r11)
 363         mtspr   SPRN_MAS6, r8
 364         mfspr   r3, SPRN_EPCR
 365         rlwinm  r3, r3, 0, ~SPRN_EPCR_DMIUH
 366         mtspr   SPRN_EPCR, r3
 367         isync
 368
 369         /* Switch to kernel stack and jump to handler. */
 370         PPC_LL  r3, HOST_RUN(r1)
 371         mr      r5, r14 /* intno */
 372         mr      r14, r4 /* Save vcpu pointer. */
 373         bl      kvmppc_handle_exit
 374
 375         /* Restore vcpu pointer and the nonvolatiles we used. */
 376         mr      r4, r14
 377         PPC_LL  r14, VCPU_GPR(r14)(r4)
 378
 379         andi.   r5, r3, RESUME_FLAG_NV
 380         beq     skip_nv_load
 381         PPC_LL  r15, VCPU_GPR(r15)(r4)
 382         PPC_LL  r16, VCPU_GPR(r16)(r4)
 383         PPC_LL  r17, VCPU_GPR(r17)(r4)
 384         PPC_LL  r18, VCPU_GPR(r18)(r4)
 385         PPC_LL  r19, VCPU_GPR(r19)(r4)
 386         PPC_LL  r20, VCPU_GPR(r20)(r4)
 387         PPC_LL  r21, VCPU_GPR(r21)(r4)
 388         PPC_LL  r22, VCPU_GPR(r22)(r4)
 389         PPC_LL  r23, VCPU_GPR(r23)(r4)
 390         PPC_LL  r24, VCPU_GPR(r24)(r4)
 391         PPC_LL  r25, VCPU_GPR(r25)(r4)
 392         PPC_LL  r26, VCPU_GPR(r26)(r4)
 393         PPC_LL  r27, VCPU_GPR(r27)(r4)
 394         PPC_LL  r28, VCPU_GPR(r28)(r4)
 395         PPC_LL  r29, VCPU_GPR(r29)(r4)
 396         PPC_LL  r30, VCPU_GPR(r30)(r4)
 397         PPC_LL  r31, VCPU_GPR(r31)(r4)
 398 skip_nv_load:
 399         /* Should we return to the guest? */
 400         andi.   r5, r3, RESUME_FLAG_HOST
 401         beq     lightweight_exit
 402
 403         srawi   r3, r3, 2 /* Shift -ERR back down. */
 404
 405 heavyweight_exit:
 406         /* Not returning to guest. */
 407         PPC_LL  r5, HOST_STACK_LR(r1)
 408
 409         /*
 410          * We already saved guest volatile register state; now save the
 411          * non-volatiles.
 412          */
 413
 414         PPC_STL r15, VCPU_GPR(r15)(r4)
 415         PPC_STL r16, VCPU_GPR(r16)(r4)
 416         PPC_STL r17, VCPU_GPR(r17)(r4)
 417         PPC_STL r18, VCPU_GPR(r18)(r4)
 418         PPC_STL r19, VCPU_GPR(r19)(r4)
 419         PPC_STL r20, VCPU_GPR(r20)(r4)
 420         PPC_STL r21, VCPU_GPR(r21)(r4)
 421         PPC_STL r22, VCPU_GPR(r22)(r4)
 422         PPC_STL r23, VCPU_GPR(r23)(r4)
 423         PPC_STL r24, VCPU_GPR(r24)(r4)
 424         PPC_STL r25, VCPU_GPR(r25)(r4)
 425         PPC_STL r26, VCPU_GPR(r26)(r4)
 426         PPC_STL r27, VCPU_GPR(r27)(r4)
 427         PPC_STL r28, VCPU_GPR(r28)(r4)
 428         PPC_STL r29, VCPU_GPR(r29)(r4)
 429         PPC_STL r30, VCPU_GPR(r30)(r4)
 430         PPC_STL r31, VCPU_GPR(r31)(r4)
 431
 432         /* Load host non-volatile register state from host stack. */
 433         PPC_LL  r14, HOST_NV_GPR(r14)(r1)
 434         PPC_LL  r15, HOST_NV_GPR(r15)(r1)
 435         PPC_LL  r16, HOST_NV_GPR(r16)(r1)
 436         PPC_LL  r17, HOST_NV_GPR(r17)(r1)
 437         PPC_LL  r18, HOST_NV_GPR(r18)(r1)
 438         PPC_LL  r19, HOST_NV_GPR(r19)(r1)
 439         PPC_LL  r20, HOST_NV_GPR(r20)(r1)
 440         PPC_LL  r21, HOST_NV_GPR(r21)(r1)
 441         PPC_LL  r22, HOST_NV_GPR(r22)(r1)
 442         PPC_LL  r23, HOST_NV_GPR(r23)(r1)
 443         PPC_LL  r24, HOST_NV_GPR(r24)(r1)
 444         PPC_LL  r25, HOST_NV_GPR(r25)(r1)
 445         PPC_LL  r26, HOST_NV_GPR(r26)(r1)
 446         PPC_LL  r27, HOST_NV_GPR(r27)(r1)
 447         PPC_LL  r28, HOST_NV_GPR(r28)(r1)
 448         PPC_LL  r29, HOST_NV_GPR(r29)(r1)
 449         PPC_LL  r30, HOST_NV_GPR(r30)(r1)
 450         PPC_LL  r31, HOST_NV_GPR(r31)(r1)
 451
 452         /* Return to kvm_vcpu_run(). */
 453         mtlr    r5
 454         addi    r1, r1, HOST_STACK_SIZE
 455         /* r3 still contains the return code from kvmppc_handle_exit(). */
 456         blr
 457
 458 /* Registers:
 459  *  r3: kvm_run pointer
 460  *  r4: vcpu pointer
 461  */
 462 _GLOBAL(__kvmppc_vcpu_run)
 463         stwu    r1, -HOST_STACK_SIZE(r1)
 464         PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
 465
 466         /* Save host state to stack. */
 467         PPC_STL r3, HOST_RUN(r1)
 468         mflr    r3
 469         PPC_STL r3, HOST_STACK_LR(r1)
 470
 471         /* Save host non-volatile register state to stack. */
 472         PPC_STL r14, HOST_NV_GPR(r14)(r1)
 473         PPC_STL r15, HOST_NV_GPR(r15)(r1)
 474         PPC_STL r16, HOST_NV_GPR(r16)(r1)
 475         PPC_STL r17, HOST_NV_GPR(r17)(r1)
 476         PPC_STL r18, HOST_NV_GPR(r18)(r1)
 477         PPC_STL r19, HOST_NV_GPR(r19)(r1)
 478         PPC_STL r20, HOST_NV_GPR(r20)(r1)
 479         PPC_STL r21, HOST_NV_GPR(r21)(r1)
 480         PPC_STL r22, HOST_NV_GPR(r22)(r1)
 481         PPC_STL r23, HOST_NV_GPR(r23)(r1)
 482         PPC_STL r24, HOST_NV_GPR(r24)(r1)
 483         PPC_STL r25, HOST_NV_GPR(r25)(r1)
 484         PPC_STL r26, HOST_NV_GPR(r26)(r1)
 485         PPC_STL r27, HOST_NV_GPR(r27)(r1)
 486         PPC_STL r28, HOST_NV_GPR(r28)(r1)
 487         PPC_STL r29, HOST_NV_GPR(r29)(r1)
 488         PPC_STL r30, HOST_NV_GPR(r30)(r1)
 489         PPC_STL r31, HOST_NV_GPR(r31)(r1)
 490
 491         /* Load guest non-volatiles. */
 492         PPC_LL  r14, VCPU_GPR(r14)(r4)
 493         PPC_LL  r15, VCPU_GPR(r15)(r4)
 494         PPC_LL  r16, VCPU_GPR(r16)(r4)
 495         PPC_LL  r17, VCPU_GPR(r17)(r4)
 496         PPC_LL  r18, VCPU_GPR(r18)(r4)
 497         PPC_LL  r19, VCPU_GPR(r19)(r4)
 498         PPC_LL  r20, VCPU_GPR(r20)(r4)
 499         PPC_LL  r21, VCPU_GPR(r21)(r4)
 500         PPC_LL  r22, VCPU_GPR(r22)(r4)
 501         PPC_LL  r23, VCPU_GPR(r23)(r4)
 502         PPC_LL  r24, VCPU_GPR(r24)(r4)
 503         PPC_LL  r25, VCPU_GPR(r25)(r4)
 504         PPC_LL  r26, VCPU_GPR(r26)(r4)
 505         PPC_LL  r27, VCPU_GPR(r27)(r4)
 506         PPC_LL  r28, VCPU_GPR(r28)(r4)
 507         PPC_LL  r29, VCPU_GPR(r29)(r4)
 508         PPC_LL  r30, VCPU_GPR(r30)(r4)
 509         PPC_LL  r31, VCPU_GPR(r31)(r4)
 510
 511
 512 lightweight_exit:
 513         PPC_STL r2, HOST_R2(r1)
 514
 515         mfspr   r3, SPRN_PID
 516         stw     r3, VCPU_HOST_PID(r4)
 517         lwz     r3, VCPU_GUEST_PID(r4)
 518         mtspr   SPRN_PID, r3
 519
 520         /* Save vcpu pointer for the exception handlers
 521          * must be done before loading guest r2.
 522          */
 523 //      SET_VCPU(r4)
 524
 525         PPC_LL  r11, VCPU_SHARED(r4)
 526         /* Save host mas4 and mas6 and load guest MAS registers */
 527         mfspr   r3, SPRN_MAS4
 528         stw     r3, VCPU_HOST_MAS4(r4)
 529         mfspr   r3, SPRN_MAS6
 530         stw     r3, VCPU_HOST_MAS6(r4)
 531         lwz     r3, VCPU_SHARED_MAS0(r11)
 532         lwz     r5, VCPU_SHARED_MAS1(r11)
 533 #ifdef CONFIG_64BIT
 534         ld      r6, (VCPU_SHARED_MAS2)(r11)
 535 #else
 536         lwz     r6, (VCPU_SHARED_MAS2 + 4)(r11)
 537 #endif
 538         lwz     r7, VCPU_SHARED_MAS7_3+4(r11)
 539         lwz     r8, VCPU_SHARED_MAS4(r11)
 540         mtspr   SPRN_MAS0, r3
 541         mtspr   SPRN_MAS1, r5
 542         mtspr   SPRN_MAS2, r6
 543         mtspr   SPRN_MAS3, r7
 544         mtspr   SPRN_MAS4, r8
 545         lwz     r3, VCPU_SHARED_MAS6(r11)
 546         lwz     r5, VCPU_SHARED_MAS7_3+0(r11)
 547         mtspr   SPRN_MAS6, r3
 548         mtspr   SPRN_MAS7, r5
 549         /* Disable MAS register updates via exception */
 550         mfspr   r3, SPRN_EPCR
 551         oris    r3, r3, SPRN_EPCR_DMIUH@h
 552         mtspr   SPRN_EPCR, r3
 553
 554         /*
 555          * Host interrupt handlers may have clobbered these guest-readable
 556          * SPRGs, so we need to reload them here with the guest's values.
 557          */
 558         lwz     r3, VCPU_VRSAVE(r4)
 559         lwz     r5, VCPU_SHARED_SPRG4(r11)
 560         mtspr   SPRN_VRSAVE, r3
 561         lwz     r6, VCPU_SHARED_SPRG5(r11)
 562         mtspr   SPRN_SPRG4W, r5
 563         lwz     r7, VCPU_SHARED_SPRG6(r11)
 564         mtspr   SPRN_SPRG5W, r6
 565         lwz     r8, VCPU_SHARED_SPRG7(r11)
 566         mtspr   SPRN_SPRG6W, r7
 567         mtspr   SPRN_SPRG7W, r8
 568
 569         /* Load some guest volatiles. */
 570         PPC_LL  r3, VCPU_LR(r4)
 571         PPC_LL  r5, VCPU_XER(r4)
 572         PPC_LL  r6, VCPU_CTR(r4)
 573         PPC_LL  r7, VCPU_CR(r4)
 574         PPC_LL  r8, VCPU_PC(r4)
 575 #ifdef CONFIG_64BIT
 576         ld      r9, (VCPU_SHARED_MSR)(r11)
 577 #else
 578         lwz     r9, (VCPU_SHARED_MSR + 4)(r11)
 579 #endif
 580         PPC_LL  r0, VCPU_GPR(r0)(r4)
 581         PPC_LL  r1, VCPU_GPR(r1)(r4)
 582         PPC_LL  r2, VCPU_GPR(r2)(r4)
 583         PPC_LL  r10, VCPU_GPR(r10)(r4)
 584         PPC_LL  r11, VCPU_GPR(r11)(r4)
 585         PPC_LL  r12, VCPU_GPR(r12)(r4)
 586         PPC_LL  r13, VCPU_GPR(r13)(r4)
 587         mtlr    r3
 588         mtxer   r5
 589         mtctr   r6
 590         mtcr    r7
 591         mtsrr0  r8
 592         mtsrr1  r9
 593
 594 #ifdef CONFIG_KVM_EXIT_TIMING
 595         /* save enter time */
 596 1:
 597         mfspr   r6, SPRN_TBRU
 598         mfspr   r7, SPRN_TBRL
 599         mfspr   r8, SPRN_TBRU
 600         cmpw    r8, r6
 601         PPC_STL r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
 602         bne     1b
 603         PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
 604 #endif
 605
 606         /* Finish loading guest volatiles and jump to guest. */
 607         PPC_LL  r5, VCPU_GPR(r5)(r4)
 608         PPC_LL  r6, VCPU_GPR(r6)(r4)
 609         PPC_LL  r7, VCPU_GPR(r7)(r4)
 610         PPC_LL  r8, VCPU_GPR(r8)(r4)
 611         PPC_LL  r9, VCPU_GPR(r9)(r4)
 612
 613         PPC_LL  r3, VCPU_GPR(r3)(r4)
 614         PPC_LL  r4, VCPU_GPR(r4)(r4)
 615         rfi