arch/powerpc/kvm/bookehv_interrupts.S

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, write to the Free Software
  13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  14  *
  15  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  16  *
  17  * Author: Varun Sethi <varun.sethi@freescale.com>
  18  * Author: Scott Wood <scotwood@freescale.com>
  19  * Author: Mihai Caraman <mihai.caraman@freescale.com>
  20  *
  21  * This file is derived from arch/powerpc/kvm/booke_interrupts.S
  22  */
  23
  24 #include <asm/ppc_asm.h>
  25 #include <asm/kvm_asm.h>
  26 #include <asm/reg.h>
  27 #include <asm/mmu-44x.h>
  28 #include <asm/page.h>
  29 #include <asm/asm-compat.h>
  30 #include <asm/asm-offsets.h>
  31 #include <asm/bitsperlong.h>
  32 #include <asm/thread_info.h>
  33
  34 #ifdef CONFIG_64BIT
  35 #include <asm/exception-64e.h>
  36 #include <asm/hw_irq.h>
  37 #include <asm/irqflags.h>
  38 #else
  39 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
  40 #endif
  41
  42 #define LONGBYTES               (BITS_PER_LONG / 8)
  43
  44 #define VCPU_GUEST_SPRG(n)      (VCPU_GUEST_SPRGS + (n * LONGBYTES))
  45
  46 /* The host stack layout: */
  47 #define HOST_R1         0 /* Implied by stwu. */
  48 #define HOST_CALLEE_LR  PPC_LR_STKOFF
  49 #define HOST_RUN        (HOST_CALLEE_LR + LONGBYTES)
  50 /*
  51  * r2 is special: it holds 'current', and it made nonvolatile in the
  52  * kernel with the -ffixed-r2 gcc option.
  53  */
  54 #define HOST_R2         (HOST_RUN + LONGBYTES)
  55 #define HOST_CR         (HOST_R2 + LONGBYTES)
  56 #define HOST_NV_GPRS    (HOST_CR + LONGBYTES)
  57 #define __HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
  58 #define HOST_NV_GPR(n)  __HOST_NV_GPR(__REG_##n)
  59 #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES)
  60 #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
  61 /* LR in caller stack frame. */
  62 #define HOST_STACK_LR   (HOST_STACK_SIZE + PPC_LR_STKOFF)
  63
  64 #define NEED_EMU                0x00000001 /* emulation -- save nv regs */
  65 #define NEED_DEAR               0x00000002 /* save faulting DEAR */
  66 #define NEED_ESR                0x00000004 /* save faulting ESR */
  67
  68 /*
  69  * On entry:
  70  * r4 = vcpu, r5 = srr0, r6 = srr1
  71  * saved in vcpu: cr, ctr, r3-r13
  72  */
  73 .macro kvm_handler_common intno, srr0, flags
  74         /* Restore host stack pointer */
  75         PPC_STL r1, VCPU_GPR(R1)(r4)
  76         PPC_STL r2, VCPU_GPR(R2)(r4)
  77         PPC_LL  r1, VCPU_HOST_STACK(r4)
  78         PPC_LL  r2, HOST_R2(r1)
  79
  80         mfspr   r10, SPRN_PID
  81         lwz     r8, VCPU_HOST_PID(r4)
  82         PPC_LL  r11, VCPU_SHARED(r4)
  83         PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
  84         li      r14, \intno
  85
  86         stw     r10, VCPU_GUEST_PID(r4)
  87         mtspr   SPRN_PID, r8
  88
  89 #ifdef CONFIG_KVM_EXIT_TIMING
  90         /* save exit time */
  91 1:      mfspr   r7, SPRN_TBRU
  92         mfspr   r8, SPRN_TBRL
  93         mfspr   r9, SPRN_TBRU
  94         cmpw    r9, r7
  95         stw     r8, VCPU_TIMING_EXIT_TBL(r4)
  96         bne-    1b
  97         stw     r9, VCPU_TIMING_EXIT_TBU(r4)
  98 #endif
  99
 100         oris    r8, r6, MSR_CE@h
 101         PPC_STD(r6, VCPU_SHARED_MSR, r11)
 102         ori     r8, r8, MSR_ME | MSR_RI
 103         PPC_STL r5, VCPU_PC(r4)
 104
 105         /*
 106          * Make sure CE/ME/RI are set (if appropriate for exception type)
 107          * whether or not the guest had it set.  Since mfmsr/mtmsr are
 108          * somewhat expensive, skip in the common case where the guest
 109          * had all these bits set (and thus they're still set if
 110          * appropriate for the exception type).
 111          */
 112         cmpw    r6, r8
 113         beq     1f
 114         mfmsr   r7
 115         .if     \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
 116         oris    r7, r7, MSR_CE@h
 117         .endif
 118         .if     \srr0 != SPRN_MCSRR0
 119         ori     r7, r7, MSR_ME | MSR_RI
 120         .endif
 121         mtmsr   r7
 122 1:
 123
 124         .if     \flags & NEED_EMU
 125         /*
 126          * This assumes you have external PID support.
 127          * To support a bookehv CPU without external PID, you'll
 128          * need to look up the TLB entry and create a temporary mapping.
 129          *
 130          * FIXME: we don't currently handle if the lwepx faults.  PR-mode
 131          * booke doesn't handle it either.  Since Linux doesn't use
 132          * broadcast tlbivax anymore, the only way this should happen is
 133          * if the guest maps its memory execute-but-not-read, or if we
 134          * somehow take a TLB miss in the middle of this entry code and
 135          * evict the relevant entry.  On e500mc, all kernel lowmem is
 136          * bolted into TLB1 large page mappings, and we don't use
 137          * broadcast invalidates, so we should not take a TLB miss here.
 138          *
 139          * Later we'll need to deal with faults here.  Disallowing guest
 140          * mappings that are execute-but-not-read could be an option on
 141          * e500mc, but not on chips with an LRAT if it is used.
 142          */
 143
 144         mfspr   r3, SPRN_EPLC   /* will already have correct ELPID and EGS */
 145         PPC_STL r15, VCPU_GPR(R15)(r4)
 146         PPC_STL r16, VCPU_GPR(R16)(r4)
 147         PPC_STL r17, VCPU_GPR(R17)(r4)
 148         PPC_STL r18, VCPU_GPR(R18)(r4)
 149         PPC_STL r19, VCPU_GPR(R19)(r4)
 150         mr      r8, r3
 151         PPC_STL r20, VCPU_GPR(R20)(r4)
 152         rlwimi  r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
 153         PPC_STL r21, VCPU_GPR(R21)(r4)
 154         rlwimi  r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
 155         PPC_STL r22, VCPU_GPR(R22)(r4)
 156         rlwimi  r8, r10, EPC_EPID_SHIFT, EPC_EPID
 157         PPC_STL r23, VCPU_GPR(R23)(r4)
 158         PPC_STL r24, VCPU_GPR(R24)(r4)
 159         PPC_STL r25, VCPU_GPR(R25)(r4)
 160         PPC_STL r26, VCPU_GPR(R26)(r4)
 161         PPC_STL r27, VCPU_GPR(R27)(r4)
 162         PPC_STL r28, VCPU_GPR(R28)(r4)
 163         PPC_STL r29, VCPU_GPR(R29)(r4)
 164         PPC_STL r30, VCPU_GPR(R30)(r4)
 165         PPC_STL r31, VCPU_GPR(R31)(r4)
 166         mtspr   SPRN_EPLC, r8
 167
 168         /* disable preemption, so we are sure we hit the fixup handler */
 169         CURRENT_THREAD_INFO(r8, r1)
 170         li      r7, 1
 171         stw     r7, TI_PREEMPT(r8)
 172
 173         isync
 174
 175         /*
 176          * In case the read goes wrong, we catch it and write an invalid value
 177          * in LAST_INST instead.
 178          */
 179 1:      lwepx   r9, 0, r5
 180 2:
 181 .section .fixup, "ax"
 182 3:      li      r9, KVM_INST_FETCH_FAILED
 183         b       2b
 184 .previous
 185 .section __ex_table,"a"
 186         PPC_LONG_ALIGN
 187         PPC_LONG 1b,3b
 188 .previous
 189
 190         mtspr   SPRN_EPLC, r3
 191         li      r7, 0
 192         stw     r7, TI_PREEMPT(r8)
 193         stw     r9, VCPU_LAST_INST(r4)
 194         .endif
 195
 196         .if     \flags & NEED_ESR
 197         mfspr   r8, SPRN_ESR
 198         PPC_STL r8, VCPU_FAULT_ESR(r4)
 199         .endif
 200
 201         .if     \flags & NEED_DEAR
 202         mfspr   r9, SPRN_DEAR
 203         PPC_STL r9, VCPU_FAULT_DEAR(r4)
 204         .endif
 205
 206         b       kvmppc_resume_host
 207 .endm
 208
 209 #ifdef CONFIG_64BIT
 210 /* Exception types */
 211 #define EX_GEN                  1
 212 #define EX_GDBELL               2
 213 #define EX_DBG                  3
 214 #define EX_MC                   4
 215 #define EX_CRIT                 5
 216 #define EX_TLB                  6
 217
 218 /*
 219  * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
 220  */
 221 .macro kvm_handler intno type scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags
 222  _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 223         mr      r11, r4
 224         /*
 225          * Get vcpu from Paca: paca->__current.thread->kvm_vcpu
 226          */
 227         PPC_LL  r4, PACACURRENT(r13)
 228         PPC_LL  r4, (THREAD + THREAD_KVM_VCPU)(r4)
 229         stw     r10, VCPU_CR(r4)
 230         PPC_STL r11, VCPU_GPR(R4)(r4)
 231         PPC_STL r5, VCPU_GPR(R5)(r4)
 232         .if \type == EX_CRIT
 233         PPC_LL  r5, (\paca_ex + EX_R13)(r13)
 234         .else
 235         mfspr   r5, \scratch
 236         .endif
 237         PPC_STL r6, VCPU_GPR(R6)(r4)
 238         PPC_STL r8, VCPU_GPR(R8)(r4)
 239         PPC_STL r9, VCPU_GPR(R9)(r4)
 240         PPC_STL r5, VCPU_GPR(R13)(r4)
 241         PPC_LL  r6, (\paca_ex + \ex_r10)(r13)
 242         PPC_LL  r8, (\paca_ex + \ex_r11)(r13)
 243         PPC_STL r3, VCPU_GPR(R3)(r4)
 244         PPC_STL r7, VCPU_GPR(R7)(r4)
 245         PPC_STL r12, VCPU_GPR(R12)(r4)
 246         PPC_STL r6, VCPU_GPR(R10)(r4)
 247         PPC_STL r8, VCPU_GPR(R11)(r4)
 248         mfctr   r5
 249         PPC_STL r5, VCPU_CTR(r4)
 250         mfspr   r5, \srr0
 251         mfspr   r6, \srr1
 252         kvm_handler_common \intno, \srr0, \flags
 253 .endm
 254
 255 #define EX_PARAMS(type) \
 256         EX_##type, \
 257         SPRN_SPRG_##type##_SCRATCH, \
 258         PACA_EX##type, \
 259         EX_R10, \
 260         EX_R11
 261
 262 #define EX_PARAMS_TLB \
 263         EX_TLB, \
 264         SPRN_SPRG_GEN_SCRATCH, \
 265         PACA_EXTLB, \
 266         EX_TLB_R10, \
 267         EX_TLB_R11
 268
 269 kvm_handler BOOKE_INTERRUPT_CRITICAL, EX_PARAMS(CRIT), \
 270         SPRN_CSRR0, SPRN_CSRR1, 0
 271 kvm_handler BOOKE_INTERRUPT_MACHINE_CHECK, EX_PARAMS(MC), \
 272         SPRN_MCSRR0, SPRN_MCSRR1, 0
 273 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, EX_PARAMS(GEN), \
 274         SPRN_SRR0, SPRN_SRR1,(NEED_EMU | NEED_DEAR | NEED_ESR)
 275 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, EX_PARAMS(GEN), \
 276         SPRN_SRR0, SPRN_SRR1, NEED_ESR
 277 kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \
 278         SPRN_SRR0, SPRN_SRR1, 0
 279 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \
 280         SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR)
 281 kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \
 282         SPRN_SRR0, SPRN_SRR1,NEED_ESR
 283 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \
 284         SPRN_SRR0, SPRN_SRR1, 0
 285 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \
 286         SPRN_SRR0, SPRN_SRR1, 0
 287 kvm_handler BOOKE_INTERRUPT_DECREMENTER, EX_PARAMS(GEN), \
 288         SPRN_SRR0, SPRN_SRR1, 0
 289 kvm_handler BOOKE_INTERRUPT_FIT, EX_PARAMS(GEN), \
 290         SPRN_SRR0, SPRN_SRR1, 0
 291 kvm_handler BOOKE_INTERRUPT_WATCHDOG, EX_PARAMS(CRIT),\
 292         SPRN_CSRR0, SPRN_CSRR1, 0
 293 /*
 294  * Only bolted TLB miss exception handlers are supported for now
 295  */
 296 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS_TLB, \
 297         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 298 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS_TLB, \
 299         SPRN_SRR0, SPRN_SRR1, 0
 300 kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, EX_PARAMS(GEN), \
 301         SPRN_SRR0, SPRN_SRR1, 0
 302 kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, EX_PARAMS(GEN), \
 303         SPRN_SRR0, SPRN_SRR1, 0
 304 kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, EX_PARAMS(GEN), \
 305         SPRN_SRR0, SPRN_SRR1, 0
 306 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \
 307         SPRN_SRR0, SPRN_SRR1, 0
 308 kvm_handler BOOKE_INTERRUPT_DOORBELL, EX_PARAMS(GEN), \
 309         SPRN_SRR0, SPRN_SRR1, 0
 310 kvm_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, EX_PARAMS(CRIT), \
 311         SPRN_CSRR0, SPRN_CSRR1, 0
 312 kvm_handler BOOKE_INTERRUPT_HV_PRIV, EX_PARAMS(GEN), \
 313         SPRN_SRR0, SPRN_SRR1, NEED_EMU
 314 kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, EX_PARAMS(GEN), \
 315         SPRN_SRR0, SPRN_SRR1, 0
 316 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, EX_PARAMS(GDBELL), \
 317         SPRN_GSRR0, SPRN_GSRR1, 0
 318 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, EX_PARAMS(CRIT), \
 319         SPRN_CSRR0, SPRN_CSRR1, 0
 320 kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
 321         SPRN_DSRR0, SPRN_DSRR1, 0
 322 kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
 323         SPRN_CSRR0, SPRN_CSRR1, 0
 324 #else
 325 /*
 326  * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
 327  */
 328 .macro kvm_handler intno srr0, srr1, flags
 329 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 330         PPC_LL  r11, THREAD_KVM_VCPU(r10)
 331         PPC_STL r3, VCPU_GPR(R3)(r11)
 332         mfspr   r3, SPRN_SPRG_RSCRATCH0
 333         PPC_STL r4, VCPU_GPR(R4)(r11)
 334         PPC_LL  r4, THREAD_NORMSAVE(0)(r10)
 335         PPC_STL r5, VCPU_GPR(R5)(r11)
 336         stw     r13, VCPU_CR(r11)
 337         mfspr   r5, \srr0
 338         PPC_STL r3, VCPU_GPR(R10)(r11)
 339         PPC_LL  r3, THREAD_NORMSAVE(2)(r10)
 340         PPC_STL r6, VCPU_GPR(R6)(r11)
 341         PPC_STL r4, VCPU_GPR(R11)(r11)
 342         mfspr   r6, \srr1
 343         PPC_STL r7, VCPU_GPR(R7)(r11)
 344         PPC_STL r8, VCPU_GPR(R8)(r11)
 345         PPC_STL r9, VCPU_GPR(R9)(r11)
 346         PPC_STL r3, VCPU_GPR(R13)(r11)
 347         mfctr   r7
 348         PPC_STL r12, VCPU_GPR(R12)(r11)
 349         PPC_STL r7, VCPU_CTR(r11)
 350         mr      r4, r11
 351         kvm_handler_common \intno, \srr0, \flags
 352 .endm
 353
 354 .macro kvm_lvl_handler intno scratch srr0, srr1, flags
 355 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 356         mfspr   r10, SPRN_SPRG_THREAD
 357         PPC_LL  r11, THREAD_KVM_VCPU(r10)
 358         PPC_STL r3, VCPU_GPR(R3)(r11)
 359         mfspr   r3, \scratch
 360         PPC_STL r4, VCPU_GPR(R4)(r11)
 361         PPC_LL  r4, GPR9(r8)
 362         PPC_STL r5, VCPU_GPR(R5)(r11)
 363         stw     r9, VCPU_CR(r11)
 364         mfspr   r5, \srr0
 365         PPC_STL r3, VCPU_GPR(R8)(r11)
 366         PPC_LL  r3, GPR10(r8)
 367         PPC_STL r6, VCPU_GPR(R6)(r11)
 368         PPC_STL r4, VCPU_GPR(R9)(r11)
 369         mfspr   r6, \srr1
 370         PPC_LL  r4, GPR11(r8)
 371         PPC_STL r7, VCPU_GPR(R7)(r11)
 372         PPC_STL r3, VCPU_GPR(R10)(r11)
 373         mfctr   r7
 374         PPC_STL r12, VCPU_GPR(R12)(r11)
 375         PPC_STL r13, VCPU_GPR(R13)(r11)
 376         PPC_STL r4, VCPU_GPR(R11)(r11)
 377         PPC_STL r7, VCPU_CTR(r11)
 378         mr      r4, r11
 379         kvm_handler_common \intno, \srr0, \flags
 380 .endm
 381
 382 kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
 383         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 384 kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
 385         SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
 386 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
 387         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 388 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
 389 kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
 390 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
 391         SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
 392 kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
 393 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 394 kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
 395 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 396 kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
 397 kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
 398 kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
 399         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 400 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
 401         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 402 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
 403 kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 404 kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
 405 kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
 406 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
 407 kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
 408 kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
 409         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 410 kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
 411 kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
 412 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
 413 kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
 414         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 415 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 416         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 417 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 418         SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
 419 #endif
 420
 421 /* Registers:
 422  *  SPRG_SCRATCH0: guest r10
 423  *  r4: vcpu pointer
 424  *  r11: vcpu->arch.shared
 425  *  r14: KVM exit number
 426  */
 427 _GLOBAL(kvmppc_resume_host)
 428         /* Save remaining volatile guest register state to vcpu. */
 429         mfspr   r3, SPRN_VRSAVE
 430         PPC_STL r0, VCPU_GPR(R0)(r4)
 431         mflr    r5
 432         mfspr   r6, SPRN_SPRG4
 433         PPC_STL r5, VCPU_LR(r4)
 434         mfspr   r7, SPRN_SPRG5
 435         stw     r3, VCPU_VRSAVE(r4)
 436         PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
 437         mfspr   r8, SPRN_SPRG6
 438         PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
 439         mfspr   r9, SPRN_SPRG7
 440         PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
 441         mfxer   r3
 442         PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
 443
 444         /* save guest MAS registers and restore host mas4 & mas6 */
 445         mfspr   r5, SPRN_MAS0
 446         PPC_STL r3, VCPU_XER(r4)
 447         mfspr   r6, SPRN_MAS1
 448         stw     r5, VCPU_SHARED_MAS0(r11)
 449         mfspr   r7, SPRN_MAS2
 450         stw     r6, VCPU_SHARED_MAS1(r11)
 451         PPC_STD(r7, VCPU_SHARED_MAS2, r11)
 452         mfspr   r5, SPRN_MAS3
 453         mfspr   r6, SPRN_MAS4
 454         stw     r5, VCPU_SHARED_MAS7_3+4(r11)
 455         mfspr   r7, SPRN_MAS6
 456         stw     r6, VCPU_SHARED_MAS4(r11)
 457         mfspr   r5, SPRN_MAS7
 458         lwz     r6, VCPU_HOST_MAS4(r4)
 459         stw     r7, VCPU_SHARED_MAS6(r11)
 460         lwz     r8, VCPU_HOST_MAS6(r4)
 461         mtspr   SPRN_MAS4, r6
 462         stw     r5, VCPU_SHARED_MAS7_3+0(r11)
 463         mtspr   SPRN_MAS6, r8
 464         /* Enable MAS register updates via exception */
 465         mfspr   r3, SPRN_EPCR
 466         rlwinm  r3, r3, 0, ~SPRN_EPCR_DMIUH
 467         mtspr   SPRN_EPCR, r3
 468         isync
 469
 470 #ifdef CONFIG_64BIT
 471         /*
 472          * We enter with interrupts disabled in hardware, but
 473          * we need to call RECONCILE_IRQ_STATE to ensure
 474          * that the software state is kept in sync.
 475          */
 476         RECONCILE_IRQ_STATE(r3,r5)
 477 #endif
 478
 479         /* Switch to kernel stack and jump to handler. */
 480         PPC_LL  r3, HOST_RUN(r1)
 481         mr      r5, r14 /* intno */
 482         mr      r14, r4 /* Save vcpu pointer. */
 483         bl      kvmppc_handle_exit
 484
 485         /* Restore vcpu pointer and the nonvolatiles we used. */
 486         mr      r4, r14
 487         PPC_LL  r14, VCPU_GPR(R14)(r4)
 488
 489         andi.   r5, r3, RESUME_FLAG_NV
 490         beq     skip_nv_load
 491         PPC_LL  r15, VCPU_GPR(R15)(r4)
 492         PPC_LL  r16, VCPU_GPR(R16)(r4)
 493         PPC_LL  r17, VCPU_GPR(R17)(r4)
 494         PPC_LL  r18, VCPU_GPR(R18)(r4)
 495         PPC_LL  r19, VCPU_GPR(R19)(r4)
 496         PPC_LL  r20, VCPU_GPR(R20)(r4)
 497         PPC_LL  r21, VCPU_GPR(R21)(r4)
 498         PPC_LL  r22, VCPU_GPR(R22)(r4)
 499         PPC_LL  r23, VCPU_GPR(R23)(r4)
 500         PPC_LL  r24, VCPU_GPR(R24)(r4)
 501         PPC_LL  r25, VCPU_GPR(R25)(r4)
 502         PPC_LL  r26, VCPU_GPR(R26)(r4)
 503         PPC_LL  r27, VCPU_GPR(R27)(r4)
 504         PPC_LL  r28, VCPU_GPR(R28)(r4)
 505         PPC_LL  r29, VCPU_GPR(R29)(r4)
 506         PPC_LL  r30, VCPU_GPR(R30)(r4)
 507         PPC_LL  r31, VCPU_GPR(R31)(r4)
 508 skip_nv_load:
 509         /* Should we return to the guest? */
 510         andi.   r5, r3, RESUME_FLAG_HOST
 511         beq     lightweight_exit
 512
 513         srawi   r3, r3, 2 /* Shift -ERR back down. */
 514
 515 heavyweight_exit:
 516         /* Not returning to guest. */
 517         PPC_LL  r5, HOST_STACK_LR(r1)
 518         lwz     r6, HOST_CR(r1)
 519
 520         /*
 521          * We already saved guest volatile register state; now save the
 522          * non-volatiles.
 523          */
 524
 525         PPC_STL r15, VCPU_GPR(R15)(r4)
 526         PPC_STL r16, VCPU_GPR(R16)(r4)
 527         PPC_STL r17, VCPU_GPR(R17)(r4)
 528         PPC_STL r18, VCPU_GPR(R18)(r4)
 529         PPC_STL r19, VCPU_GPR(R19)(r4)
 530         PPC_STL r20, VCPU_GPR(R20)(r4)
 531         PPC_STL r21, VCPU_GPR(R21)(r4)
 532         PPC_STL r22, VCPU_GPR(R22)(r4)
 533         PPC_STL r23, VCPU_GPR(R23)(r4)
 534         PPC_STL r24, VCPU_GPR(R24)(r4)
 535         PPC_STL r25, VCPU_GPR(R25)(r4)
 536         PPC_STL r26, VCPU_GPR(R26)(r4)
 537         PPC_STL r27, VCPU_GPR(R27)(r4)
 538         PPC_STL r28, VCPU_GPR(R28)(r4)
 539         PPC_STL r29, VCPU_GPR(R29)(r4)
 540         PPC_STL r30, VCPU_GPR(R30)(r4)
 541         PPC_STL r31, VCPU_GPR(R31)(r4)
 542
 543         /* Load host non-volatile register state from host stack. */
 544         PPC_LL  r14, HOST_NV_GPR(R14)(r1)
 545         PPC_LL  r15, HOST_NV_GPR(R15)(r1)
 546         PPC_LL  r16, HOST_NV_GPR(R16)(r1)
 547         PPC_LL  r17, HOST_NV_GPR(R17)(r1)
 548         PPC_LL  r18, HOST_NV_GPR(R18)(r1)
 549         PPC_LL  r19, HOST_NV_GPR(R19)(r1)
 550         PPC_LL  r20, HOST_NV_GPR(R20)(r1)
 551         PPC_LL  r21, HOST_NV_GPR(R21)(r1)
 552         PPC_LL  r22, HOST_NV_GPR(R22)(r1)
 553         PPC_LL  r23, HOST_NV_GPR(R23)(r1)
 554         PPC_LL  r24, HOST_NV_GPR(R24)(r1)
 555         PPC_LL  r25, HOST_NV_GPR(R25)(r1)
 556         PPC_LL  r26, HOST_NV_GPR(R26)(r1)
 557         PPC_LL  r27, HOST_NV_GPR(R27)(r1)
 558         PPC_LL  r28, HOST_NV_GPR(R28)(r1)
 559         PPC_LL  r29, HOST_NV_GPR(R29)(r1)
 560         PPC_LL  r30, HOST_NV_GPR(R30)(r1)
 561         PPC_LL  r31, HOST_NV_GPR(R31)(r1)
 562
 563         /* Return to kvm_vcpu_run(). */
 564         mtlr    r5
 565         mtcr    r6
 566         addi    r1, r1, HOST_STACK_SIZE
 567         /* r3 still contains the return code from kvmppc_handle_exit(). */
 568         blr
 569
 570 /* Registers:
 571  *  r3: kvm_run pointer
 572  *  r4: vcpu pointer
 573  */
 574 _GLOBAL(__kvmppc_vcpu_run)
 575         stwu    r1, -HOST_STACK_SIZE(r1)
 576         PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
 577
 578         /* Save host state to stack. */
 579         PPC_STL r3, HOST_RUN(r1)
 580         mflr    r3
 581         mfcr    r5
 582         PPC_STL r3, HOST_STACK_LR(r1)
 583
 584         stw     r5, HOST_CR(r1)
 585
 586         /* Save host non-volatile register state to stack. */
 587         PPC_STL r14, HOST_NV_GPR(R14)(r1)
 588         PPC_STL r15, HOST_NV_GPR(R15)(r1)
 589         PPC_STL r16, HOST_NV_GPR(R16)(r1)
 590         PPC_STL r17, HOST_NV_GPR(R17)(r1)
 591         PPC_STL r18, HOST_NV_GPR(R18)(r1)
 592         PPC_STL r19, HOST_NV_GPR(R19)(r1)
 593         PPC_STL r20, HOST_NV_GPR(R20)(r1)
 594         PPC_STL r21, HOST_NV_GPR(R21)(r1)
 595         PPC_STL r22, HOST_NV_GPR(R22)(r1)
 596         PPC_STL r23, HOST_NV_GPR(R23)(r1)
 597         PPC_STL r24, HOST_NV_GPR(R24)(r1)
 598         PPC_STL r25, HOST_NV_GPR(R25)(r1)
 599         PPC_STL r26, HOST_NV_GPR(R26)(r1)
 600         PPC_STL r27, HOST_NV_GPR(R27)(r1)
 601         PPC_STL r28, HOST_NV_GPR(R28)(r1)
 602         PPC_STL r29, HOST_NV_GPR(R29)(r1)
 603         PPC_STL r30, HOST_NV_GPR(R30)(r1)
 604         PPC_STL r31, HOST_NV_GPR(R31)(r1)
 605
 606         /* Load guest non-volatiles. */
 607         PPC_LL  r14, VCPU_GPR(R14)(r4)
 608         PPC_LL  r15, VCPU_GPR(R15)(r4)
 609         PPC_LL  r16, VCPU_GPR(R16)(r4)
 610         PPC_LL  r17, VCPU_GPR(R17)(r4)
 611         PPC_LL  r18, VCPU_GPR(R18)(r4)
 612         PPC_LL  r19, VCPU_GPR(R19)(r4)
 613         PPC_LL  r20, VCPU_GPR(R20)(r4)
 614         PPC_LL  r21, VCPU_GPR(R21)(r4)
 615         PPC_LL  r22, VCPU_GPR(R22)(r4)
 616         PPC_LL  r23, VCPU_GPR(R23)(r4)
 617         PPC_LL  r24, VCPU_GPR(R24)(r4)
 618         PPC_LL  r25, VCPU_GPR(R25)(r4)
 619         PPC_LL  r26, VCPU_GPR(R26)(r4)
 620         PPC_LL  r27, VCPU_GPR(R27)(r4)
 621         PPC_LL  r28, VCPU_GPR(R28)(r4)
 622         PPC_LL  r29, VCPU_GPR(R29)(r4)
 623         PPC_LL  r30, VCPU_GPR(R30)(r4)
 624         PPC_LL  r31, VCPU_GPR(R31)(r4)
 625
 626
 627 lightweight_exit:
 628         PPC_STL r2, HOST_R2(r1)
 629
 630         mfspr   r3, SPRN_PID
 631         stw     r3, VCPU_HOST_PID(r4)
 632         lwz     r3, VCPU_GUEST_PID(r4)
 633         mtspr   SPRN_PID, r3
 634
 635         PPC_LL  r11, VCPU_SHARED(r4)
 636         /* Disable MAS register updates via exception */
 637         mfspr   r3, SPRN_EPCR
 638         oris    r3, r3, SPRN_EPCR_DMIUH@h
 639         mtspr   SPRN_EPCR, r3
 640         isync
 641         /* Save host mas4 and mas6 and load guest MAS registers */
 642         mfspr   r3, SPRN_MAS4
 643         stw     r3, VCPU_HOST_MAS4(r4)
 644         mfspr   r3, SPRN_MAS6
 645         stw     r3, VCPU_HOST_MAS6(r4)
 646         lwz     r3, VCPU_SHARED_MAS0(r11)
 647         lwz     r5, VCPU_SHARED_MAS1(r11)
 648         PPC_LD(r6, VCPU_SHARED_MAS2, r11)
 649         lwz     r7, VCPU_SHARED_MAS7_3+4(r11)
 650         lwz     r8, VCPU_SHARED_MAS4(r11)
 651         mtspr   SPRN_MAS0, r3
 652         mtspr   SPRN_MAS1, r5
 653         mtspr   SPRN_MAS2, r6
 654         mtspr   SPRN_MAS3, r7
 655         mtspr   SPRN_MAS4, r8
 656         lwz     r3, VCPU_SHARED_MAS6(r11)
 657         lwz     r5, VCPU_SHARED_MAS7_3+0(r11)
 658         mtspr   SPRN_MAS6, r3
 659         mtspr   SPRN_MAS7, r5
 660
 661         /*
 662          * Host interrupt handlers may have clobbered these guest-readable
 663          * SPRGs, so we need to reload them here with the guest's values.
 664          */
 665         lwz     r3, VCPU_VRSAVE(r4)
 666         PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
 667         mtspr   SPRN_VRSAVE, r3
 668         PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
 669         mtspr   SPRN_SPRG4W, r5
 670         PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
 671         mtspr   SPRN_SPRG5W, r6
 672         PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
 673         mtspr   SPRN_SPRG6W, r7
 674         mtspr   SPRN_SPRG7W, r8
 675
 676         /* Load some guest volatiles. */
 677         PPC_LL  r3, VCPU_LR(r4)
 678         PPC_LL  r5, VCPU_XER(r4)
 679         PPC_LL  r6, VCPU_CTR(r4)
 680         lwz     r7, VCPU_CR(r4)
 681         PPC_LL  r8, VCPU_PC(r4)
 682         PPC_LD(r9, VCPU_SHARED_MSR, r11)
 683         PPC_LL  r0, VCPU_GPR(R0)(r4)
 684         PPC_LL  r1, VCPU_GPR(R1)(r4)
 685         PPC_LL  r2, VCPU_GPR(R2)(r4)
 686         PPC_LL  r10, VCPU_GPR(R10)(r4)
 687         PPC_LL  r11, VCPU_GPR(R11)(r4)
 688         PPC_LL  r12, VCPU_GPR(R12)(r4)
 689         PPC_LL  r13, VCPU_GPR(R13)(r4)
 690         mtlr    r3
 691         mtxer   r5
 692         mtctr   r6
 693         mtsrr0  r8
 694         mtsrr1  r9
 695
 696 #ifdef CONFIG_KVM_EXIT_TIMING
 697         /* save enter time */
 698 1:
 699         mfspr   r6, SPRN_TBRU
 700         mfspr   r9, SPRN_TBRL
 701         mfspr   r8, SPRN_TBRU
 702         cmpw    r8, r6
 703         stw     r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
 704         bne     1b
 705         stw     r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
 706 #endif
 707
 708         /*
 709          * Don't execute any instruction which can change CR after
 710          * below instruction.
 711          */
 712         mtcr    r7
 713
 714         /* Finish loading guest volatiles and jump to guest. */
 715         PPC_LL  r5, VCPU_GPR(R5)(r4)
 716         PPC_LL  r6, VCPU_GPR(R6)(r4)
 717         PPC_LL  r7, VCPU_GPR(R7)(r4)
 718         PPC_LL  r8, VCPU_GPR(R8)(r4)
 719         PPC_LL  r9, VCPU_GPR(R9)(r4)
 720
 721         PPC_LL  r3, VCPU_GPR(R3)(r4)
 722         PPC_LL  r4, VCPU_GPR(R4)(r4)
 723         rfi