arch/powerpc/kvm/bookehv_interrupts.S

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, write to the Free Software
  13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  14  *
  15  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  16  *
  17  * Author: Varun Sethi <varun.sethi@freescale.com>
  18  * Author: Scott Wood <scotwood@freescale.com>
  19  *
  20  * This file is derived from arch/powerpc/kvm/booke_interrupts.S
  21  */
  22
  23 #include <asm/ppc_asm.h>
  24 #include <asm/kvm_asm.h>
  25 #include <asm/reg.h>
  26 #include <asm/mmu-44x.h>
  27 #include <asm/page.h>
  28 #include <asm/asm-compat.h>
  29 #include <asm/asm-offsets.h>
  30 #include <asm/bitsperlong.h>
  31 #include <asm/thread_info.h>
  32
  33 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
  34
  35 #define GET_VCPU(vcpu, thread)  \
  36         PPC_LL  vcpu, THREAD_KVM_VCPU(thread)
  37
  38 #define LONGBYTES               (BITS_PER_LONG / 8)
  39
  40 #define VCPU_GPR(n)             (VCPU_GPRS + (n * LONGBYTES))
  41 #define VCPU_GUEST_SPRG(n)      (VCPU_GUEST_SPRGS + (n * LONGBYTES))
  42
  43 /* The host stack layout: */
  44 #define HOST_R1         (0 * LONGBYTES) /* Implied by stwu. */
  45 #define HOST_CALLEE_LR  (1 * LONGBYTES)
  46 #define HOST_RUN        (2 * LONGBYTES) /* struct kvm_run */
  47 /*
  48  * r2 is special: it holds 'current', and it made nonvolatile in the
  49  * kernel with the -ffixed-r2 gcc option.
  50  */
  51 #define HOST_R2         (3 * LONGBYTES)
  52 #define HOST_NV_GPRS    (4 * LONGBYTES)
  53 #define HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
  54 #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
  55 #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
  56 #define HOST_STACK_LR   (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
  57
  58 #define NEED_EMU                0x00000001 /* emulation -- save nv regs */
  59 #define NEED_DEAR               0x00000002 /* save faulting DEAR */
  60 #define NEED_ESR                0x00000004 /* save faulting ESR */
  61
  62 /*
  63  * On entry:
  64  * r4 = vcpu, r5 = srr0, r6 = srr1
  65  * saved in vcpu: cr, ctr, r3-r13
  66  */
  67 .macro kvm_handler_common intno, srr0, flags
  68         /* Restore host stack pointer */
  69         PPC_STL r1, VCPU_GPR(r1)(r4)
  70         PPC_STL r2, VCPU_GPR(r2)(r4)
  71         PPC_LL  r1, VCPU_HOST_STACK(r4)
  72         PPC_LL  r2, HOST_R2(r1)
  73
  74         mfspr   r10, SPRN_PID
  75         lwz     r8, VCPU_HOST_PID(r4)
  76         PPC_LL  r11, VCPU_SHARED(r4)
  77         PPC_STL r14, VCPU_GPR(r14)(r4) /* We need a non-volatile GPR. */
  78         li      r14, \intno
  79
  80         stw     r10, VCPU_GUEST_PID(r4)
  81         mtspr   SPRN_PID, r8
  82
  83 #ifdef CONFIG_KVM_EXIT_TIMING
  84         /* save exit time */
  85 1:      mfspr   r7, SPRN_TBRU
  86         mfspr   r8, SPRN_TBRL
  87         mfspr   r9, SPRN_TBRU
  88         cmpw    r9, r7
  89         PPC_STL r8, VCPU_TIMING_EXIT_TBL(r4)
  90         bne-    1b
  91         PPC_STL r9, VCPU_TIMING_EXIT_TBU(r4)
  92 #endif
  93
  94         .if     \flags & NEED_EMU
  95         lwz     r9, VCPU_KVM(r4)
  96         .endif
  97
  98         oris    r8, r6, MSR_CE@h
  99 #ifdef CONFIG_64BIT
 100         std     r6, (VCPU_SHARED_MSR)(r11)
 101 #else
 102         stw     r6, (VCPU_SHARED_MSR + 4)(r11)
 103 #endif
 104         ori     r8, r8, MSR_ME | MSR_RI
 105         PPC_STL r5, VCPU_PC(r4)
 106
 107         /*
 108          * Make sure CE/ME/RI are set (if appropriate for exception type)
 109          * whether or not the guest had it set.  Since mfmsr/mtmsr are
 110          * somewhat expensive, skip in the common case where the guest
 111          * had all these bits set (and thus they're still set if
 112          * appropriate for the exception type).
 113          */
 114         cmpw    r6, r8
 115         .if     \flags & NEED_EMU
 116         lwz     r9, KVM_LPID(r9)
 117         .endif
 118         beq     1f
 119         mfmsr   r7
 120         .if     \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
 121         oris    r7, r7, MSR_CE@h
 122         .endif
 123         .if     \srr0 != SPRN_MCSRR0
 124         ori     r7, r7, MSR_ME | MSR_RI
 125         .endif
 126         mtmsr   r7
 127 1:
 128
 129         .if     \flags & NEED_EMU
 130         /*
 131          * This assumes you have external PID support.
 132          * To support a bookehv CPU without external PID, you'll
 133          * need to look up the TLB entry and create a temporary mapping.
 134          *
 135          * FIXME: we don't currently handle if the lwepx faults.  PR-mode
 136          * booke doesn't handle it either.  Since Linux doesn't use
 137          * broadcast tlbivax anymore, the only way this should happen is
 138          * if the guest maps its memory execute-but-not-read, or if we
 139          * somehow take a TLB miss in the middle of this entry code and
 140          * evict the relevant entry.  On e500mc, all kernel lowmem is
 141          * bolted into TLB1 large page mappings, and we don't use
 142          * broadcast invalidates, so we should not take a TLB miss here.
 143          *
 144          * Later we'll need to deal with faults here.  Disallowing guest
 145          * mappings that are execute-but-not-read could be an option on
 146          * e500mc, but not on chips with an LRAT if it is used.
 147          */
 148
 149         mfspr   r3, SPRN_EPLC   /* will already have correct ELPID and EGS */
 150         PPC_STL r15, VCPU_GPR(r15)(r4)
 151         PPC_STL r16, VCPU_GPR(r16)(r4)
 152         PPC_STL r17, VCPU_GPR(r17)(r4)
 153         PPC_STL r18, VCPU_GPR(r18)(r4)
 154         PPC_STL r19, VCPU_GPR(r19)(r4)
 155         mr      r8, r3
 156         PPC_STL r20, VCPU_GPR(r20)(r4)
 157         rlwimi  r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
 158         PPC_STL r21, VCPU_GPR(r21)(r4)
 159         rlwimi  r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
 160         PPC_STL r22, VCPU_GPR(r22)(r4)
 161         rlwimi  r8, r10, EPC_EPID_SHIFT, EPC_EPID
 162         PPC_STL r23, VCPU_GPR(r23)(r4)
 163         PPC_STL r24, VCPU_GPR(r24)(r4)
 164         PPC_STL r25, VCPU_GPR(r25)(r4)
 165         PPC_STL r26, VCPU_GPR(r26)(r4)
 166         PPC_STL r27, VCPU_GPR(r27)(r4)
 167         PPC_STL r28, VCPU_GPR(r28)(r4)
 168         PPC_STL r29, VCPU_GPR(r29)(r4)
 169         PPC_STL r30, VCPU_GPR(r30)(r4)
 170         PPC_STL r31, VCPU_GPR(r31)(r4)
 171         mtspr   SPRN_EPLC, r8
 172
 173         /* disable preemption, so we are sure we hit the fixup handler */
 174 #ifdef CONFIG_PPC64
 175         clrrdi  r8,r1,THREAD_SHIFT
 176 #else
 177         rlwinm  r8,r1,0,0,31-THREAD_SHIFT       /* current thread_info */
 178 #endif
 179         li      r7, 1
 180         stw     r7, TI_PREEMPT(r8)
 181
 182         isync
 183
 184         /*
 185          * In case the read goes wrong, we catch it and write an invalid value
 186          * in LAST_INST instead.
 187          */
 188 1:      lwepx   r9, 0, r5
 189 2:
 190 .section .fixup, "ax"
 191 3:      li      r9, KVM_INST_FETCH_FAILED
 192         b       2b
 193 .previous
 194 .section __ex_table,"a"
 195         PPC_LONG_ALIGN
 196         PPC_LONG 1b,3b
 197 .previous
 198
 199         mtspr   SPRN_EPLC, r3
 200         li      r7, 0
 201         stw     r7, TI_PREEMPT(r8)
 202         stw     r9, VCPU_LAST_INST(r4)
 203         .endif
 204
 205         .if     \flags & NEED_ESR
 206         mfspr   r8, SPRN_ESR
 207         PPC_STL r8, VCPU_FAULT_ESR(r4)
 208         .endif
 209
 210         .if     \flags & NEED_DEAR
 211         mfspr   r9, SPRN_DEAR
 212         PPC_STL r9, VCPU_FAULT_DEAR(r4)
 213         .endif
 214
 215         b       kvmppc_resume_host
 216 .endm
 217
 218 /*
 219  * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
 220  */
 221 .macro kvm_handler intno srr0, srr1, flags
 222 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 223         GET_VCPU(r11, r10)
 224         PPC_STL r3, VCPU_GPR(r3)(r11)
 225         mfspr   r3, SPRN_SPRG_RSCRATCH0
 226         PPC_STL r4, VCPU_GPR(r4)(r11)
 227         PPC_LL  r4, THREAD_NORMSAVE(0)(r10)
 228         PPC_STL r5, VCPU_GPR(r5)(r11)
 229         PPC_STL r13, VCPU_CR(r11)
 230         mfspr   r5, \srr0
 231         PPC_STL r3, VCPU_GPR(r10)(r11)
 232         PPC_LL  r3, THREAD_NORMSAVE(2)(r10)
 233         PPC_STL r6, VCPU_GPR(r6)(r11)
 234         PPC_STL r4, VCPU_GPR(r11)(r11)
 235         mfspr   r6, \srr1
 236         PPC_STL r7, VCPU_GPR(r7)(r11)
 237         PPC_STL r8, VCPU_GPR(r8)(r11)
 238         PPC_STL r9, VCPU_GPR(r9)(r11)
 239         PPC_STL r3, VCPU_GPR(r13)(r11)
 240         mfctr   r7
 241         PPC_STL r12, VCPU_GPR(r12)(r11)
 242         PPC_STL r7, VCPU_CTR(r11)
 243         mr      r4, r11
 244         kvm_handler_common \intno, \srr0, \flags
 245 .endm
 246
 247 .macro kvm_lvl_handler intno scratch srr0, srr1, flags
 248 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 249         mfspr   r10, SPRN_SPRG_THREAD
 250         GET_VCPU(r11, r10)
 251         PPC_STL r3, VCPU_GPR(r3)(r11)
 252         mfspr   r3, \scratch
 253         PPC_STL r4, VCPU_GPR(r4)(r11)
 254         PPC_LL  r4, GPR9(r8)
 255         PPC_STL r5, VCPU_GPR(r5)(r11)
 256         PPC_STL r9, VCPU_CR(r11)
 257         mfspr   r5, \srr0
 258         PPC_STL r3, VCPU_GPR(r8)(r11)
 259         PPC_LL  r3, GPR10(r8)
 260         PPC_STL r6, VCPU_GPR(r6)(r11)
 261         PPC_STL r4, VCPU_GPR(r9)(r11)
 262         mfspr   r6, \srr1
 263         PPC_LL  r4, GPR11(r8)
 264         PPC_STL r7, VCPU_GPR(r7)(r11)
 265         PPC_STL r8, VCPU_GPR(r8)(r11)
 266         PPC_STL r3, VCPU_GPR(r10)(r11)
 267         mfctr   r7
 268         PPC_STL r12, VCPU_GPR(r12)(r11)
 269         PPC_STL r4, VCPU_GPR(r11)(r11)
 270         PPC_STL r7, VCPU_CTR(r11)
 271         mr      r4, r11
 272         kvm_handler_common \intno, \srr0, \flags
 273 .endm
 274
 275 kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
 276         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 277 kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
 278         SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
 279 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
 280         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR)
 281 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
 282 kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
 283 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
 284         SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
 285 kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
 286 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 287 kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
 288 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 289 kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
 290 kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
 291 kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
 292         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 293 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
 294         SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 295 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
 296 kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
 297 kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
 298 kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
 299 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
 300 kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
 301 kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
 302         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 303 kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
 304 kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
 305 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
 306 kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
 307         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 308 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 309         SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
 310 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 311         SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
 312
 313
 314 /* Registers:
 315  *  SPRG_SCRATCH0: guest r10
 316  *  r4: vcpu pointer
 317  *  r11: vcpu->arch.shared
 318  *  r14: KVM exit number
 319  */
 320 _GLOBAL(kvmppc_resume_host)
 321         /* Save remaining volatile guest register state to vcpu. */
 322         mfspr   r3, SPRN_VRSAVE
 323         PPC_STL r0, VCPU_GPR(r0)(r4)
 324         mflr    r5
 325         mfspr   r6, SPRN_SPRG4
 326         PPC_STL r5, VCPU_LR(r4)
 327         mfspr   r7, SPRN_SPRG5
 328         PPC_STL r3, VCPU_VRSAVE(r4)
 329         PPC_STL r6, VCPU_SHARED_SPRG4(r11)
 330         mfspr   r8, SPRN_SPRG6
 331         PPC_STL r7, VCPU_SHARED_SPRG5(r11)
 332         mfspr   r9, SPRN_SPRG7
 333         PPC_STL r8, VCPU_SHARED_SPRG6(r11)
 334         mfxer   r3
 335         PPC_STL r9, VCPU_SHARED_SPRG7(r11)
 336
 337         /* save guest MAS registers and restore host mas4 & mas6 */
 338         mfspr   r5, SPRN_MAS0
 339         PPC_STL r3, VCPU_XER(r4)
 340         mfspr   r6, SPRN_MAS1
 341         stw     r5, VCPU_SHARED_MAS0(r11)
 342         mfspr   r7, SPRN_MAS2
 343         stw     r6, VCPU_SHARED_MAS1(r11)
 344 #ifdef CONFIG_64BIT
 345         std     r7, (VCPU_SHARED_MAS2)(r11)
 346 #else
 347         stw     r7, (VCPU_SHARED_MAS2 + 4)(r11)
 348 #endif
 349         mfspr   r5, SPRN_MAS3
 350         mfspr   r6, SPRN_MAS4
 351         stw     r5, VCPU_SHARED_MAS7_3+4(r11)
 352         mfspr   r7, SPRN_MAS6
 353         stw     r6, VCPU_SHARED_MAS4(r11)
 354         mfspr   r5, SPRN_MAS7
 355         lwz     r6, VCPU_HOST_MAS4(r4)
 356         stw     r7, VCPU_SHARED_MAS6(r11)
 357         lwz     r8, VCPU_HOST_MAS6(r4)
 358         mtspr   SPRN_MAS4, r6
 359         stw     r5, VCPU_SHARED_MAS7_3+0(r11)
 360         mtspr   SPRN_MAS6, r8
 361         mfspr   r3, SPRN_EPCR
 362         rlwinm  r3, r3, 0, ~SPRN_EPCR_DMIUH
 363         mtspr   SPRN_EPCR, r3
 364         isync
 365
 366         /* Switch to kernel stack and jump to handler. */
 367         PPC_LL  r3, HOST_RUN(r1)
 368         mr      r5, r14 /* intno */
 369         mr      r14, r4 /* Save vcpu pointer. */
 370         bl      kvmppc_handle_exit
 371
 372         /* Restore vcpu pointer and the nonvolatiles we used. */
 373         mr      r4, r14
 374         PPC_LL  r14, VCPU_GPR(r14)(r4)
 375
 376         andi.   r5, r3, RESUME_FLAG_NV
 377         beq     skip_nv_load
 378         PPC_LL  r15, VCPU_GPR(r15)(r4)
 379         PPC_LL  r16, VCPU_GPR(r16)(r4)
 380         PPC_LL  r17, VCPU_GPR(r17)(r4)
 381         PPC_LL  r18, VCPU_GPR(r18)(r4)
 382         PPC_LL  r19, VCPU_GPR(r19)(r4)
 383         PPC_LL  r20, VCPU_GPR(r20)(r4)
 384         PPC_LL  r21, VCPU_GPR(r21)(r4)
 385         PPC_LL  r22, VCPU_GPR(r22)(r4)
 386         PPC_LL  r23, VCPU_GPR(r23)(r4)
 387         PPC_LL  r24, VCPU_GPR(r24)(r4)
 388         PPC_LL  r25, VCPU_GPR(r25)(r4)
 389         PPC_LL  r26, VCPU_GPR(r26)(r4)
 390         PPC_LL  r27, VCPU_GPR(r27)(r4)
 391         PPC_LL  r28, VCPU_GPR(r28)(r4)
 392         PPC_LL  r29, VCPU_GPR(r29)(r4)
 393         PPC_LL  r30, VCPU_GPR(r30)(r4)
 394         PPC_LL  r31, VCPU_GPR(r31)(r4)
 395 skip_nv_load:
 396         /* Should we return to the guest? */
 397         andi.   r5, r3, RESUME_FLAG_HOST
 398         beq     lightweight_exit
 399
 400         srawi   r3, r3, 2 /* Shift -ERR back down. */
 401
 402 heavyweight_exit:
 403         /* Not returning to guest. */
 404         PPC_LL  r5, HOST_STACK_LR(r1)
 405
 406         /*
 407          * We already saved guest volatile register state; now save the
 408          * non-volatiles.
 409          */
 410
 411         PPC_STL r15, VCPU_GPR(r15)(r4)
 412         PPC_STL r16, VCPU_GPR(r16)(r4)
 413         PPC_STL r17, VCPU_GPR(r17)(r4)
 414         PPC_STL r18, VCPU_GPR(r18)(r4)
 415         PPC_STL r19, VCPU_GPR(r19)(r4)
 416         PPC_STL r20, VCPU_GPR(r20)(r4)
 417         PPC_STL r21, VCPU_GPR(r21)(r4)
 418         PPC_STL r22, VCPU_GPR(r22)(r4)
 419         PPC_STL r23, VCPU_GPR(r23)(r4)
 420         PPC_STL r24, VCPU_GPR(r24)(r4)
 421         PPC_STL r25, VCPU_GPR(r25)(r4)
 422         PPC_STL r26, VCPU_GPR(r26)(r4)
 423         PPC_STL r27, VCPU_GPR(r27)(r4)
 424         PPC_STL r28, VCPU_GPR(r28)(r4)
 425         PPC_STL r29, VCPU_GPR(r29)(r4)
 426         PPC_STL r30, VCPU_GPR(r30)(r4)
 427         PPC_STL r31, VCPU_GPR(r31)(r4)
 428
 429         /* Load host non-volatile register state from host stack. */
 430         PPC_LL  r14, HOST_NV_GPR(r14)(r1)
 431         PPC_LL  r15, HOST_NV_GPR(r15)(r1)
 432         PPC_LL  r16, HOST_NV_GPR(r16)(r1)
 433         PPC_LL  r17, HOST_NV_GPR(r17)(r1)
 434         PPC_LL  r18, HOST_NV_GPR(r18)(r1)
 435         PPC_LL  r19, HOST_NV_GPR(r19)(r1)
 436         PPC_LL  r20, HOST_NV_GPR(r20)(r1)
 437         PPC_LL  r21, HOST_NV_GPR(r21)(r1)
 438         PPC_LL  r22, HOST_NV_GPR(r22)(r1)
 439         PPC_LL  r23, HOST_NV_GPR(r23)(r1)
 440         PPC_LL  r24, HOST_NV_GPR(r24)(r1)
 441         PPC_LL  r25, HOST_NV_GPR(r25)(r1)
 442         PPC_LL  r26, HOST_NV_GPR(r26)(r1)
 443         PPC_LL  r27, HOST_NV_GPR(r27)(r1)
 444         PPC_LL  r28, HOST_NV_GPR(r28)(r1)
 445         PPC_LL  r29, HOST_NV_GPR(r29)(r1)
 446         PPC_LL  r30, HOST_NV_GPR(r30)(r1)
 447         PPC_LL  r31, HOST_NV_GPR(r31)(r1)
 448
 449         /* Return to kvm_vcpu_run(). */
 450         mtlr    r5
 451         addi    r1, r1, HOST_STACK_SIZE
 452         /* r3 still contains the return code from kvmppc_handle_exit(). */
 453         blr
 454
 455 /* Registers:
 456  *  r3: kvm_run pointer
 457  *  r4: vcpu pointer
 458  */
 459 _GLOBAL(__kvmppc_vcpu_run)
 460         stwu    r1, -HOST_STACK_SIZE(r1)
 461         PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
 462
 463         /* Save host state to stack. */
 464         PPC_STL r3, HOST_RUN(r1)
 465         mflr    r3
 466         PPC_STL r3, HOST_STACK_LR(r1)
 467
 468         /* Save host non-volatile register state to stack. */
 469         PPC_STL r14, HOST_NV_GPR(r14)(r1)
 470         PPC_STL r15, HOST_NV_GPR(r15)(r1)
 471         PPC_STL r16, HOST_NV_GPR(r16)(r1)
 472         PPC_STL r17, HOST_NV_GPR(r17)(r1)
 473         PPC_STL r18, HOST_NV_GPR(r18)(r1)
 474         PPC_STL r19, HOST_NV_GPR(r19)(r1)
 475         PPC_STL r20, HOST_NV_GPR(r20)(r1)
 476         PPC_STL r21, HOST_NV_GPR(r21)(r1)
 477         PPC_STL r22, HOST_NV_GPR(r22)(r1)
 478         PPC_STL r23, HOST_NV_GPR(r23)(r1)
 479         PPC_STL r24, HOST_NV_GPR(r24)(r1)
 480         PPC_STL r25, HOST_NV_GPR(r25)(r1)
 481         PPC_STL r26, HOST_NV_GPR(r26)(r1)
 482         PPC_STL r27, HOST_NV_GPR(r27)(r1)
 483         PPC_STL r28, HOST_NV_GPR(r28)(r1)
 484         PPC_STL r29, HOST_NV_GPR(r29)(r1)
 485         PPC_STL r30, HOST_NV_GPR(r30)(r1)
 486         PPC_STL r31, HOST_NV_GPR(r31)(r1)
 487
 488         /* Load guest non-volatiles. */
 489         PPC_LL  r14, VCPU_GPR(r14)(r4)
 490         PPC_LL  r15, VCPU_GPR(r15)(r4)
 491         PPC_LL  r16, VCPU_GPR(r16)(r4)
 492         PPC_LL  r17, VCPU_GPR(r17)(r4)
 493         PPC_LL  r18, VCPU_GPR(r18)(r4)
 494         PPC_LL  r19, VCPU_GPR(r19)(r4)
 495         PPC_LL  r20, VCPU_GPR(r20)(r4)
 496         PPC_LL  r21, VCPU_GPR(r21)(r4)
 497         PPC_LL  r22, VCPU_GPR(r22)(r4)
 498         PPC_LL  r23, VCPU_GPR(r23)(r4)
 499         PPC_LL  r24, VCPU_GPR(r24)(r4)
 500         PPC_LL  r25, VCPU_GPR(r25)(r4)
 501         PPC_LL  r26, VCPU_GPR(r26)(r4)
 502         PPC_LL  r27, VCPU_GPR(r27)(r4)
 503         PPC_LL  r28, VCPU_GPR(r28)(r4)
 504         PPC_LL  r29, VCPU_GPR(r29)(r4)
 505         PPC_LL  r30, VCPU_GPR(r30)(r4)
 506         PPC_LL  r31, VCPU_GPR(r31)(r4)
 507
 508
 509 lightweight_exit:
 510         PPC_STL r2, HOST_R2(r1)
 511
 512         mfspr   r3, SPRN_PID
 513         stw     r3, VCPU_HOST_PID(r4)
 514         lwz     r3, VCPU_GUEST_PID(r4)
 515         mtspr   SPRN_PID, r3
 516
 517         PPC_LL  r11, VCPU_SHARED(r4)
 518         /* Save host mas4 and mas6 and load guest MAS registers */
 519         mfspr   r3, SPRN_MAS4
 520         stw     r3, VCPU_HOST_MAS4(r4)
 521         mfspr   r3, SPRN_MAS6
 522         stw     r3, VCPU_HOST_MAS6(r4)
 523         lwz     r3, VCPU_SHARED_MAS0(r11)
 524         lwz     r5, VCPU_SHARED_MAS1(r11)
 525 #ifdef CONFIG_64BIT
 526         ld      r6, (VCPU_SHARED_MAS2)(r11)
 527 #else
 528         lwz     r6, (VCPU_SHARED_MAS2 + 4)(r11)
 529 #endif
 530         lwz     r7, VCPU_SHARED_MAS7_3+4(r11)
 531         lwz     r8, VCPU_SHARED_MAS4(r11)
 532         mtspr   SPRN_MAS0, r3
 533         mtspr   SPRN_MAS1, r5
 534         mtspr   SPRN_MAS2, r6
 535         mtspr   SPRN_MAS3, r7
 536         mtspr   SPRN_MAS4, r8
 537         lwz     r3, VCPU_SHARED_MAS6(r11)
 538         lwz     r5, VCPU_SHARED_MAS7_3+0(r11)
 539         mtspr   SPRN_MAS6, r3
 540         mtspr   SPRN_MAS7, r5
 541         /* Disable MAS register updates via exception */
 542         mfspr   r3, SPRN_EPCR
 543         oris    r3, r3, SPRN_EPCR_DMIUH@h
 544         mtspr   SPRN_EPCR, r3
 545
 546         /*
 547          * Host interrupt handlers may have clobbered these guest-readable
 548          * SPRGs, so we need to reload them here with the guest's values.
 549          */
 550         lwz     r3, VCPU_VRSAVE(r4)
 551         lwz     r5, VCPU_SHARED_SPRG4(r11)
 552         mtspr   SPRN_VRSAVE, r3
 553         lwz     r6, VCPU_SHARED_SPRG5(r11)
 554         mtspr   SPRN_SPRG4W, r5
 555         lwz     r7, VCPU_SHARED_SPRG6(r11)
 556         mtspr   SPRN_SPRG5W, r6
 557         lwz     r8, VCPU_SHARED_SPRG7(r11)
 558         mtspr   SPRN_SPRG6W, r7
 559         mtspr   SPRN_SPRG7W, r8
 560
 561         /* Load some guest volatiles. */
 562         PPC_LL  r3, VCPU_LR(r4)
 563         PPC_LL  r5, VCPU_XER(r4)
 564         PPC_LL  r6, VCPU_CTR(r4)
 565         PPC_LL  r7, VCPU_CR(r4)
 566         PPC_LL  r8, VCPU_PC(r4)
 567 #ifdef CONFIG_64BIT
 568         ld      r9, (VCPU_SHARED_MSR)(r11)
 569 #else
 570         lwz     r9, (VCPU_SHARED_MSR + 4)(r11)
 571 #endif
 572         PPC_LL  r0, VCPU_GPR(r0)(r4)
 573         PPC_LL  r1, VCPU_GPR(r1)(r4)
 574         PPC_LL  r2, VCPU_GPR(r2)(r4)
 575         PPC_LL  r10, VCPU_GPR(r10)(r4)
 576         PPC_LL  r11, VCPU_GPR(r11)(r4)
 577         PPC_LL  r12, VCPU_GPR(r12)(r4)
 578         PPC_LL  r13, VCPU_GPR(r13)(r4)
 579         mtlr    r3
 580         mtxer   r5
 581         mtctr   r6
 582         mtcr    r7
 583         mtsrr0  r8
 584         mtsrr1  r9
 585
 586 #ifdef CONFIG_KVM_EXIT_TIMING
 587         /* save enter time */
 588 1:
 589         mfspr   r6, SPRN_TBRU
 590         mfspr   r7, SPRN_TBRL
 591         mfspr   r8, SPRN_TBRU
 592         cmpw    r8, r6
 593         PPC_STL r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
 594         bne     1b
 595         PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
 596 #endif
 597
 598         /* Finish loading guest volatiles and jump to guest. */
 599         PPC_LL  r5, VCPU_GPR(r5)(r4)
 600         PPC_LL  r6, VCPU_GPR(r6)(r4)
 601         PPC_LL  r7, VCPU_GPR(r7)(r4)
 602         PPC_LL  r8, VCPU_GPR(r8)(r4)
 603         PPC_LL  r9, VCPU_GPR(r9)(r4)
 604
 605         PPC_LL  r3, VCPU_GPR(r3)(r4)
 606         PPC_LL  r4, VCPU_GPR(r4)(r4)
 607         rfi