arch/powerpc/math-emu/math.c

   1 /*
   2  * Copyright (C) 1999  Eddie C. Dost  (ecd@atecom.com)
   3  */
   4
   5 #include <linux/types.h>
   6 #include <linux/sched.h>
   7
   8 #include <asm/uaccess.h>
   9 #include <asm/reg.h>
  10
  11 #include <asm/sfp-machine.h>
  12 #include <math-emu/double.h>
  13
  14 #define FLOATFUNC(x)    extern int x(void *, void *, void *, void *)
  15
  16 FLOATFUNC(fadd);
  17 FLOATFUNC(fadds);
  18 FLOATFUNC(fdiv);
  19 FLOATFUNC(fdivs);
  20 FLOATFUNC(fmul);
  21 FLOATFUNC(fmuls);
  22 FLOATFUNC(fsub);
  23 FLOATFUNC(fsubs);
  24
  25 FLOATFUNC(fmadd);
  26 FLOATFUNC(fmadds);
  27 FLOATFUNC(fmsub);
  28 FLOATFUNC(fmsubs);
  29 FLOATFUNC(fnmadd);
  30 FLOATFUNC(fnmadds);
  31 FLOATFUNC(fnmsub);
  32 FLOATFUNC(fnmsubs);
  33
  34 FLOATFUNC(fctiw);
  35 FLOATFUNC(fctiwz);
  36 FLOATFUNC(frsp);
  37
  38 FLOATFUNC(fcmpo);
  39 FLOATFUNC(fcmpu);
  40
  41 FLOATFUNC(mcrfs);
  42 FLOATFUNC(mffs);
  43 FLOATFUNC(mtfsb0);
  44 FLOATFUNC(mtfsb1);
  45 FLOATFUNC(mtfsf);
  46 FLOATFUNC(mtfsfi);
  47
  48 FLOATFUNC(lfd);
  49 FLOATFUNC(lfs);
  50
  51 FLOATFUNC(stfd);
  52 FLOATFUNC(stfs);
  53 FLOATFUNC(stfiwx);
  54
  55 FLOATFUNC(fabs);
  56 FLOATFUNC(fmr);
  57 FLOATFUNC(fnabs);
  58 FLOATFUNC(fneg);
  59
  60 /* Optional */
  61 FLOATFUNC(fre);
  62 FLOATFUNC(fres);
  63 FLOATFUNC(frsqrte);
  64 FLOATFUNC(frsqrtes);
  65 FLOATFUNC(fsel);
  66 FLOATFUNC(fsqrt);
  67 FLOATFUNC(fsqrts);
  68
  69
  70 #define OP31            0x1f            /*   31 */
  71 #define LFS             0x30            /*   48 */
  72 #define LFSU            0x31            /*   49 */
  73 #define LFD             0x32            /*   50 */
  74 #define LFDU            0x33            /*   51 */
  75 #define STFS            0x34            /*   52 */
  76 #define STFSU           0x35            /*   53 */
  77 #define STFD            0x36            /*   54 */
  78 #define STFDU           0x37            /*   55 */
  79 #define OP59            0x3b            /*   59 */
  80 #define OP63            0x3f            /*   63 */
  81
  82 /* Opcode 31: */
  83 /* X-Form: */
  84 #define LFSX            0x217           /*  535 */
  85 #define LFSUX           0x237           /*  567 */
  86 #define LFDX            0x257           /*  599 */
  87 #define LFDUX           0x277           /*  631 */
  88 #define STFSX           0x297           /*  663 */
  89 #define STFSUX          0x2b7           /*  695 */
  90 #define STFDX           0x2d7           /*  727 */
  91 #define STFDUX          0x2f7           /*  759 */
  92 #define STFIWX          0x3d7           /*  983 */
  93
  94 /* Opcode 59: */
  95 /* A-Form: */
  96 #define FDIVS           0x012           /*   18 */
  97 #define FSUBS           0x014           /*   20 */
  98 #define FADDS           0x015           /*   21 */
  99 #define FSQRTS          0x016           /*   22 */
 100 #define FRES            0x018           /*   24 */
 101 #define FMULS           0x019           /*   25 */
 102 #define FRSQRTES        0x01a           /*   26 */
 103 #define FMSUBS          0x01c           /*   28 */
 104 #define FMADDS          0x01d           /*   29 */
 105 #define FNMSUBS         0x01e           /*   30 */
 106 #define FNMADDS         0x01f           /*   31 */
 107
 108 /* Opcode 63: */
 109 /* A-Form: */
 110 #define FDIV            0x012           /*   18 */
 111 #define FSUB            0x014           /*   20 */
 112 #define FADD            0x015           /*   21 */
 113 #define FSQRT           0x016           /*   22 */
 114 #define FSEL            0x017           /*   23 */
 115 #define FRE             0x018           /*   24 */
 116 #define FMUL            0x019           /*   25 */
 117 #define FRSQRTE         0x01a           /*   26 */
 118 #define FMSUB           0x01c           /*   28 */
 119 #define FMADD           0x01d           /*   29 */
 120 #define FNMSUB          0x01e           /*   30 */
 121 #define FNMADD          0x01f           /*   31 */
 122
 123 /* X-Form: */
 124 #define FCMPU           0x000           /*    0 */
 125 #define FRSP            0x00c           /*   12 */
 126 #define FCTIW           0x00e           /*   14 */
 127 #define FCTIWZ          0x00f           /*   15 */
 128 #define FCMPO           0x020           /*   32 */
 129 #define MTFSB1          0x026           /*   38 */
 130 #define FNEG            0x028           /*   40 */
 131 #define MCRFS           0x040           /*   64 */
 132 #define MTFSB0          0x046           /*   70 */
 133 #define FMR             0x048           /*   72 */
 134 #define MTFSFI          0x086           /*  134 */
 135 #define FNABS           0x088           /*  136 */
 136 #define FABS            0x108           /*  264 */
 137 #define MFFS            0x247           /*  583 */
 138 #define MTFSF           0x2c7           /*  711 */
 139
 140
 141 #define AB      2
 142 #define AC      3
 143 #define ABC     4
 144 #define D       5
 145 #define DU      6
 146 #define X       7
 147 #define XA      8
 148 #define XB      9
 149 #define XCR     11
 150 #define XCRB    12
 151 #define XCRI    13
 152 #define XCRL    16
 153 #define XE      14
 154 #define XEU     15
 155 #define XFLB    10
 156
 157 #ifdef CONFIG_MATH_EMULATION
 158 static int
 159 record_exception(struct pt_regs *regs, int eflag)
 160 {
 161         u32 fpscr;
 162
 163         fpscr = __FPU_FPSCR;
 164
 165         if (eflag) {
 166                 fpscr |= FPSCR_FX;
 167                 if (eflag & EFLAG_OVERFLOW)
 168                         fpscr |= FPSCR_OX;
 169                 if (eflag & EFLAG_UNDERFLOW)
 170                         fpscr |= FPSCR_UX;
 171                 if (eflag & EFLAG_DIVZERO)
 172                         fpscr |= FPSCR_ZX;
 173                 if (eflag & EFLAG_INEXACT)
 174                         fpscr |= FPSCR_XX;
 175                 if (eflag & EFLAG_INVALID)
 176                         fpscr |= FPSCR_VX;
 177                 if (eflag & EFLAG_VXSNAN)
 178                         fpscr |= FPSCR_VXSNAN;
 179                 if (eflag & EFLAG_VXISI)
 180                         fpscr |= FPSCR_VXISI;
 181                 if (eflag & EFLAG_VXIDI)
 182                         fpscr |= FPSCR_VXIDI;
 183                 if (eflag & EFLAG_VXZDZ)
 184                         fpscr |= FPSCR_VXZDZ;
 185                 if (eflag & EFLAG_VXIMZ)
 186                         fpscr |= FPSCR_VXIMZ;
 187                 if (eflag & EFLAG_VXVC)
 188                         fpscr |= FPSCR_VXVC;
 189                 if (eflag & EFLAG_VXSOFT)
 190                         fpscr |= FPSCR_VXSOFT;
 191                 if (eflag & EFLAG_VXSQRT)
 192                         fpscr |= FPSCR_VXSQRT;
 193                 if (eflag & EFLAG_VXCVI)
 194                         fpscr |= FPSCR_VXCVI;
 195         }
 196
 197 //      fpscr &= ~(FPSCR_VX);
 198         if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
 199                      FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
 200                      FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI))
 201                 fpscr |= FPSCR_VX;
 202
 203         fpscr &= ~(FPSCR_FEX);
 204         if (((fpscr & FPSCR_VX) && (fpscr & FPSCR_VE)) ||
 205             ((fpscr & FPSCR_OX) && (fpscr & FPSCR_OE)) ||
 206             ((fpscr & FPSCR_UX) && (fpscr & FPSCR_UE)) ||
 207             ((fpscr & FPSCR_ZX) && (fpscr & FPSCR_ZE)) ||
 208             ((fpscr & FPSCR_XX) && (fpscr & FPSCR_XE)))
 209                 fpscr |= FPSCR_FEX;
 210
 211         __FPU_FPSCR = fpscr;
 212
 213         return (fpscr & FPSCR_FEX) ? 1 : 0;
 214 }
 215 #endif /* CONFIG_MATH_EMULATION */
 216
 217 int
 218 do_mathemu(struct pt_regs *regs)
 219 {
 220         void *op0 = 0, *op1 = 0, *op2 = 0, *op3 = 0;
 221         unsigned long pc = regs->nip;
 222         signed short sdisp;
 223         u32 insn = 0;
 224         int idx = 0;
 225 #ifdef CONFIG_MATH_EMULATION
 226         int (*func)(void *, void *, void *, void *);
 227         int type = 0;
 228         int eflag, trap;
 229 #endif
 230
 231         if (get_user(insn, (u32 *)pc))
 232                 return -EFAULT;
 233
 234         switch (insn >> 26) {
 235         case LFS:       func = lfs;     type = D;       break;
 236         case LFSU:      func = lfs;     type = DU;      break;
 237         case LFD:       func = lfd;     type = D;       break;
 238         case LFDU:      func = lfd;     type = DU;      break;
 239         case STFS:      func = stfs;    type = D;       break;
 240         case STFSU:     func = stfs;    type = DU;      break;
 241         case STFD:      func = stfd;    type = D;       break;
 242         case STFDU:     func = stfd;    type = DU;      break;
 243
 244         case OP31:
 245                 switch ((insn >> 1) & 0x3ff) {
 246                 case LFSX:      func = lfs;     type = XE;      break;
 247                 case LFSUX:     func = lfs;     type = XEU;     break;
 248                 case LFDX:      func = lfd;     type = XE;      break;
 249                 case LFDUX:     func = lfd;     type = XEU;     break;
 250                 case STFSX:     func = stfs;    type = XE;      break;
 251                 case STFSUX:    func = stfs;    type = XEU;     break;
 252                 case STFDX:     func = stfd;    type = XE;      break;
 253                 case STFDUX:    func = stfd;    type = XEU;     break;
 254                 case STFIWX:    func = stfiwx;  type = XE;      break;
 255                 default:
 256                         goto illegal;
 257                 }
 258                 break;
 259
 260         case OP59:
 261                 switch ((insn >> 1) & 0x1f) {
 262                 case FDIVS:     func = fdivs;   type = AB;      break;
 263                 case FSUBS:     func = fsubs;   type = AB;      break;
 264                 case FADDS:     func = fadds;   type = AB;      break;
 265                 case FSQRTS:    func = fsqrts;  type = XB;      break;
 266                 case FRES:      func = fres;    type = XB;      break;
 267                 case FMULS:     func = fmuls;   type = AC;      break;
 268                 case FRSQRTES:  func = frsqrtes;type = XB;      break;
 269                 case FMSUBS:    func = fmsubs;  type = ABC;     break;
 270                 case FMADDS:    func = fmadds;  type = ABC;     break;
 271                 case FNMSUBS:   func = fnmsubs; type = ABC;     break;
 272                 case FNMADDS:   func = fnmadds; type = ABC;     break;
 273                 default:
 274                         goto illegal;
 275                 }
 276                 break;
 277
 278         case OP63:
 279                 if (insn & 0x20) {
 280                         switch ((insn >> 1) & 0x1f) {
 281                         case FDIV:      func = fdiv;    type = AB;      break;
 282                         case FSUB:      func = fsub;    type = AB;      break;
 283                         case FADD:      func = fadd;    type = AB;      break;
 284                         case FSQRT:     func = fsqrt;   type = XB;      break;
 285                         case FRE:       func = fre;     type = XB;      break;
 286                         case FSEL:      func = fsel;    type = ABC;     break;
 287                         case FMUL:      func = fmul;    type = AC;      break;
 288                         case FRSQRTE:   func = frsqrte; type = XB;      break;
 289                         case FMSUB:     func = fmsub;   type = ABC;     break;
 290                         case FMADD:     func = fmadd;   type = ABC;     break;
 291                         case FNMSUB:    func = fnmsub;  type = ABC;     break;
 292                         case FNMADD:    func = fnmadd;  type = ABC;     break;
 293                         default:
 294                                 goto illegal;
 295                         }
 296                         break;
 297                 }
 298
 299                 switch ((insn >> 1) & 0x3ff) {
 300                 case FCMPU:     func = fcmpu;   type = XCR;     break;
 301                 case FRSP:      func = frsp;    type = XB;      break;
 302                 case FCTIW:     func = fctiw;   type = XB;      break;
 303                 case FCTIWZ:    func = fctiwz;  type = XB;      break;
 304                 case FCMPO:     func = fcmpo;   type = XCR;     break;
 305                 case MTFSB1:    func = mtfsb1;  type = XCRB;    break;
 306                 case FNEG:      func = fneg;    type = XB;      break;
 307                 case MCRFS:     func = mcrfs;   type = XCRL;    break;
 308                 case MTFSB0:    func = mtfsb0;  type = XCRB;    break;
 309                 case FMR:       func = fmr;     type = XB;      break;
 310                 case MTFSFI:    func = mtfsfi;  type = XCRI;    break;
 311                 case FNABS:     func = fnabs;   type = XB;      break;
 312                 case FABS:      func = fabs;    type = XB;      break;
 313                 case MFFS:      func = mffs;    type = X;       break;
 314                 case MTFSF:     func = mtfsf;   type = XFLB;    break;
 315                 default:
 316                         goto illegal;
 317                 }
 318                 break;
 319
 320         default:
 321                 goto illegal;
 322         }
 323
 324         switch (type) {
 325         case AB:
 326                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 327                 op1 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);
 328                 op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);
 329                 break;
 330
 331         case AC:
 332                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 333                 op1 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);
 334                 op2 = (void *)&current->thread.TS_FPR((insn >>  6) & 0x1f);
 335                 break;
 336
 337         case ABC:
 338                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 339                 op1 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);
 340                 op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);
 341                 op3 = (void *)&current->thread.TS_FPR((insn >>  6) & 0x1f);
 342                 break;
 343
 344         case D:
 345                 idx = (insn >> 16) & 0x1f;
 346                 sdisp = (insn & 0xffff);
 347                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 348                 op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
 349                 break;
 350
 351         case DU:
 352                 idx = (insn >> 16) & 0x1f;
 353                 if (!idx)
 354                         goto illegal;
 355
 356                 sdisp = (insn & 0xffff);
 357                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 358                 op1 = (void *)(regs->gpr[idx] + sdisp);
 359                 break;
 360
 361         case X:
 362                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 363                 break;
 364
 365         case XA:
 366                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 367                 op1 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);
 368                 break;
 369
 370         case XB:
 371                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 372                 op1 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);
 373                 break;
 374
 375         case XE:
 376                 idx = (insn >> 16) & 0x1f;
 377                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 378                 if (!idx) {
 379                         if (((insn >> 1) & 0x3ff) == STFIWX)
 380                                 op1 = (void *)(regs->gpr[(insn >> 11) & 0x1f]);
 381                         else
 382                                 goto illegal;
 383                 } else {
 384                         op1 = (void *)(regs->gpr[idx] + regs->gpr[(insn >> 11) & 0x1f]);
 385                 }
 386
 387                 break;
 388
 389         case XEU:
 390                 idx = (insn >> 16) & 0x1f;
 391                 op0 = (void *)&current->thread.TS_FPR((insn >> 21) & 0x1f);
 392                 op1 = (void *)((idx ? regs->gpr[idx] : 0)
 393                                 + regs->gpr[(insn >> 11) & 0x1f]);
 394                 break;
 395
 396         case XCR:
 397                 op0 = (void *)&regs->ccr;
 398                 op1 = (void *)((insn >> 23) & 0x7);
 399                 op2 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f);
 400                 op3 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);
 401                 break;
 402
 403         case XCRL:
 404                 op0 = (void *)&regs->ccr;
 405                 op1 = (void *)((insn >> 23) & 0x7);
 406                 op2 = (void *)((insn >> 18) & 0x7);
 407                 break;
 408
 409         case XCRB:
 410                 op0 = (void *)((insn >> 21) & 0x1f);
 411                 break;
 412
 413         case XCRI:
 414                 op0 = (void *)((insn >> 23) & 0x7);
 415                 op1 = (void *)((insn >> 12) & 0xf);
 416                 break;
 417
 418         case XFLB:
 419                 op0 = (void *)((insn >> 17) & 0xff);
 420                 op1 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f);
 421                 break;
 422
 423         default:
 424                 goto illegal;
 425         }
 426
 427         eflag = func(op0, op1, op2, op3);
 428
 429         if (insn & 1) {
 430                 regs->ccr &= ~(0x0f000000);
 431                 regs->ccr |= (__FPU_FPSCR >> 4) & 0x0f000000;
 432         }
 433
 434         trap = record_exception(regs, eflag);
 435         if (trap)
 436                 return 1;
 437
 438         switch (type) {
 439         case DU:
 440         case XEU:
 441                 regs->gpr[idx] = (unsigned long)op1;
 442                 break;
 443
 444         default:
 445                 break;
 446         }
 447
 448         regs->nip += 4;
 449         return 0;
 450
 451 illegal:
 452         return -ENOSYS;
 453 }