arch/powerpc/mm/hash_native_64.c

   1 /*
   2  * native hashtable management.
   3  *
   4  * SMP scalability work:
   5  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #undef DEBUG_LOW
  14
  15 #include <linux/spinlock.h>
  16 #include <linux/bitops.h>
  17 #include <linux/of.h>
  18 #include <linux/threads.h>
  19 #include <linux/smp.h>
  20
  21 #include <asm/machdep.h>
  22 #include <asm/mmu.h>
  23 #include <asm/mmu_context.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/tlbflush.h>
  26 #include <asm/tlb.h>
  27 #include <asm/cputable.h>
  28 #include <asm/udbg.h>
  29 #include <asm/kexec.h>
  30 #include <asm/ppc-opcode.h>
  31
  32 #ifdef DEBUG_LOW
  33 #define DBG_LOW(fmt...) udbg_printf(fmt)
  34 #else
  35 #define DBG_LOW(fmt...)
  36 #endif
  37
  38 #define HPTE_LOCK_BIT 3
  39
  40 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
  41
  42 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
  43 {
  44         unsigned long va;
  45         unsigned int penc;
  46
  47         /*
  48          * We need 14 to 65 bits of va for a tlibe of 4K page
  49          * With vpn we ignore the lower VPN_SHIFT bits already.
  50          * And top two bits are already ignored because we can
  51          * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
  52          * of 12.
  53          */
  54         va = vpn << VPN_SHIFT;
  55         /*
  56          * clear top 16 bits of 64bit va, non SLS segment
  57          * Older versions of the architecture (2.02 and earler) require the
  58          * masking of the top 16 bits.
  59          */
  60         va &= ~(0xffffULL << 48);
  61
  62         switch (psize) {
  63         case MMU_PAGE_4K:
  64                 /* clear out bits after (52) [0....52.....63] */
  65                 va &= ~((1ul << (64 - 52)) - 1);
  66                 va |= ssize << 8;
  67                 va |= mmu_psize_defs[apsize].sllp << 6;
  68                 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
  69                              : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
  70                              : "memory");
  71                 break;
  72         default:
  73                 /* We need 14 to 14 + i bits of va */
  74                 penc = mmu_psize_defs[psize].penc[apsize];
  75                 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
  76                 va |= penc << 12;
  77                 va |= ssize << 8;
  78                 /* Add AVAL part */
  79                 if (psize != apsize) {
  80                         /*
  81                          * MPSS, 64K base page size and 16MB parge page size
  82                          * We don't need all the bits, but rest of the bits
  83                          * must be ignored by the processor.
  84                          * vpn cover upto 65 bits of va. (0...65) and we need
  85                          * 58..64 bits of va.
  86                          */
  87                         va |= (vpn & 0xfe);
  88                 }
  89                 va |= 1; /* L */
  90                 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
  91                              : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
  92                              : "memory");
  93                 break;
  94         }
  95 }
  96
  97 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
  98 {
  99         unsigned long va;
 100         unsigned int penc;
 101
 102         /* VPN_SHIFT can be atmost 12 */
 103         va = vpn << VPN_SHIFT;
 104         /*
 105          * clear top 16 bits of 64 bit va, non SLS segment
 106          * Older versions of the architecture (2.02 and earler) require the
 107          * masking of the top 16 bits.
 108          */
 109         va &= ~(0xffffULL << 48);
 110
 111         switch (psize) {
 112         case MMU_PAGE_4K:
 113                 /* clear out bits after(52) [0....52.....63] */
 114                 va &= ~((1ul << (64 - 52)) - 1);
 115                 va |= ssize << 8;
 116                 va |= mmu_psize_defs[apsize].sllp << 6;
 117                 asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
 118                              : : "r"(va) : "memory");
 119                 break;
 120         default:
 121                 /* We need 14 to 14 + i bits of va */
 122                 penc = mmu_psize_defs[psize].penc[apsize];
 123                 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
 124                 va |= penc << 12;
 125                 va |= ssize << 8;
 126                 /* Add AVAL part */
 127                 if (psize != apsize) {
 128                         /*
 129                          * MPSS, 64K base page size and 16MB parge page size
 130                          * We don't need all the bits, but rest of the bits
 131                          * must be ignored by the processor.
 132                          * vpn cover upto 65 bits of va. (0...65) and we need
 133                          * 58..64 bits of va.
 134                          */
 135                         va |= (vpn & 0xfe);
 136                 }
 137                 va |= 1; /* L */
 138                 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
 139                              : : "r"(va) : "memory");
 140                 break;
 141         }
 142
 143 }
 144
 145 static inline void tlbie(unsigned long vpn, int psize, int apsize,
 146                          int ssize, int local)
 147 {
 148         unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
 149         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 150
 151         if (use_local)
 152                 use_local = mmu_psize_defs[psize].tlbiel;
 153         if (lock_tlbie && !use_local)
 154                 raw_spin_lock(&native_tlbie_lock);
 155         asm volatile("ptesync": : :"memory");
 156         if (use_local) {
 157                 __tlbiel(vpn, psize, apsize, ssize);
 158                 asm volatile("ptesync": : :"memory");
 159         } else {
 160                 __tlbie(vpn, psize, apsize, ssize);
 161                 asm volatile("eieio; tlbsync; ptesync": : :"memory");
 162         }
 163         if (lock_tlbie && !use_local)
 164                 raw_spin_unlock(&native_tlbie_lock);
 165 }
 166
 167 static inline void native_lock_hpte(struct hash_pte *hptep)
 168 {
 169         unsigned long *word = &hptep->v;
 170
 171         while (1) {
 172                 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
 173                         break;
 174                 while(test_bit(HPTE_LOCK_BIT, word))
 175                         cpu_relax();
 176         }
 177 }
 178
 179 static inline void native_unlock_hpte(struct hash_pte *hptep)
 180 {
 181         unsigned long *word = &hptep->v;
 182
 183         clear_bit_unlock(HPTE_LOCK_BIT, word);
 184 }
 185
 186 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
 187                         unsigned long pa, unsigned long rflags,
 188                         unsigned long vflags, int psize, int apsize, int ssize)
 189 {
 190         struct hash_pte *hptep = htab_address + hpte_group;
 191         unsigned long hpte_v, hpte_r;
 192         int i;
 193
 194         if (!(vflags & HPTE_V_BOLTED)) {
 195                 DBG_LOW("    insert(group=%lx, vpn=%016lx, pa=%016lx,"
 196                         " rflags=%lx, vflags=%lx, psize=%d)\n",
 197                         hpte_group, vpn, pa, rflags, vflags, psize);
 198         }
 199
 200         for (i = 0; i < HPTES_PER_GROUP; i++) {
 201                 if (! (hptep->v & HPTE_V_VALID)) {
 202                         /* retry with lock held */
 203                         native_lock_hpte(hptep);
 204                         if (! (hptep->v & HPTE_V_VALID))
 205                                 break;
 206                         native_unlock_hpte(hptep);
 207                 }
 208
 209                 hptep++;
 210         }
 211
 212         if (i == HPTES_PER_GROUP)
 213                 return -1;
 214
 215         hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
 216         hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
 217
 218         if (!(vflags & HPTE_V_BOLTED)) {
 219                 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
 220                         i, hpte_v, hpte_r);
 221         }
 222
 223         hptep->r = hpte_r;
 224         /* Guarantee the second dword is visible before the valid bit */
 225         eieio();
 226         /*
 227          * Now set the first dword including the valid bit
 228          * NOTE: this also unlocks the hpte
 229          */
 230         hptep->v = hpte_v;
 231
 232         __asm__ __volatile__ ("ptesync" : : : "memory");
 233
 234         return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
 235 }
 236
 237 static long native_hpte_remove(unsigned long hpte_group)
 238 {
 239         struct hash_pte *hptep;
 240         int i;
 241         int slot_offset;
 242         unsigned long hpte_v;
 243
 244         DBG_LOW("    remove(group=%lx)\n", hpte_group);
 245
 246         /* pick a random entry to start at */
 247         slot_offset = mftb() & 0x7;
 248
 249         for (i = 0; i < HPTES_PER_GROUP; i++) {
 250                 hptep = htab_address + hpte_group + slot_offset;
 251                 hpte_v = hptep->v;
 252
 253                 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
 254                         /* retry with lock held */
 255                         native_lock_hpte(hptep);
 256                         hpte_v = hptep->v;
 257                         if ((hpte_v & HPTE_V_VALID)
 258                             && !(hpte_v & HPTE_V_BOLTED))
 259                                 break;
 260                         native_unlock_hpte(hptep);
 261                 }
 262
 263                 slot_offset++;
 264                 slot_offset &= 0x7;
 265         }
 266
 267         if (i == HPTES_PER_GROUP)
 268                 return -1;
 269
 270         /* Invalidate the hpte. NOTE: this also unlocks it */
 271         hptep->v = 0;
 272
 273         return i;
 274 }
 275
 276 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
 277                                  unsigned long vpn, int bpsize,
 278                                  int apsize, int ssize, int local)
 279 {
 280         struct hash_pte *hptep = htab_address + slot;
 281         unsigned long hpte_v, want_v;
 282         int ret = 0;
 283
 284         want_v = hpte_encode_avpn(vpn, bpsize, ssize);
 285
 286         DBG_LOW("    update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
 287                 vpn, want_v & HPTE_V_AVPN, slot, newpp);
 288
 289         native_lock_hpte(hptep);
 290
 291         hpte_v = hptep->v;
 292         /*
 293          * We need to invalidate the TLB always because hpte_remove doesn't do
 294          * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
 295          * random entry from it. When we do that we don't invalidate the TLB
 296          * (hpte_remove) because we assume the old translation is still
 297          * technically "valid".
 298          */
 299         if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
 300                 DBG_LOW(" -> miss\n");
 301                 ret = -1;
 302         } else {
 303                 DBG_LOW(" -> hit\n");
 304                 /* Update the HPTE */
 305                 hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
 306                         (newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C));
 307         }
 308         native_unlock_hpte(hptep);
 309
 310         /* Ensure it is out of the tlb too. */
 311         tlbie(vpn, bpsize, apsize, ssize, local);
 312
 313         return ret;
 314 }
 315
 316 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
 317 {
 318         struct hash_pte *hptep;
 319         unsigned long hash;
 320         unsigned long i;
 321         long slot;
 322         unsigned long want_v, hpte_v;
 323
 324         hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
 325         want_v = hpte_encode_avpn(vpn, psize, ssize);
 326
 327         /* Bolted mappings are only ever in the primary group */
 328         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
 329         for (i = 0; i < HPTES_PER_GROUP; i++) {
 330                 hptep = htab_address + slot;
 331                 hpte_v = hptep->v;
 332
 333                 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
 334                         /* HPTE matches */
 335                         return slot;
 336                 ++slot;
 337         }
 338
 339         return -1;
 340 }
 341
 342 /*
 343  * Update the page protection bits. Intended to be used to create
 344  * guard pages for kernel data structures on pages which are bolted
 345  * in the HPT. Assumes pages being operated on will not be stolen.
 346  *
 347  * No need to lock here because we should be the only user.
 348  */
 349 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
 350                                        int psize, int ssize)
 351 {
 352         unsigned long vpn;
 353         unsigned long vsid;
 354         long slot;
 355         struct hash_pte *hptep;
 356
 357         vsid = get_kernel_vsid(ea, ssize);
 358         vpn = hpt_vpn(ea, vsid, ssize);
 359
 360         slot = native_hpte_find(vpn, psize, ssize);
 361         if (slot == -1)
 362                 panic("could not find page to bolt\n");
 363         hptep = htab_address + slot;
 364
 365         /* Update the HPTE */
 366         hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
 367                 (newpp & (HPTE_R_PP | HPTE_R_N));
 368         /*
 369          * Ensure it is out of the tlb too. Bolted entries base and
 370          * actual page size will be same.
 371          */
 372         tlbie(vpn, psize, psize, ssize, 0);
 373 }
 374
 375 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
 376                                    int bpsize, int apsize, int ssize, int local)
 377 {
 378         struct hash_pte *hptep = htab_address + slot;
 379         unsigned long hpte_v;
 380         unsigned long want_v;
 381         unsigned long flags;
 382
 383         local_irq_save(flags);
 384
 385         DBG_LOW("    invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
 386
 387         want_v = hpte_encode_avpn(vpn, bpsize, ssize);
 388         native_lock_hpte(hptep);
 389         hpte_v = hptep->v;
 390
 391         /*
 392          * We need to invalidate the TLB always because hpte_remove doesn't do
 393          * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
 394          * random entry from it. When we do that we don't invalidate the TLB
 395          * (hpte_remove) because we assume the old translation is still
 396          * technically "valid".
 397          */
 398         if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
 399                 native_unlock_hpte(hptep);
 400         else
 401                 /* Invalidate the hpte. NOTE: this also unlocks it */
 402                 hptep->v = 0;
 403
 404         /* Invalidate the TLB */
 405         tlbie(vpn, bpsize, apsize, ssize, local);
 406
 407         local_irq_restore(flags);
 408 }
 409
 410 static inline int __hpte_actual_psize(unsigned int lp, int psize)
 411 {
 412         int i, shift;
 413         unsigned int mask;
 414
 415         /* start from 1 ignoring MMU_PAGE_4K */
 416         for (i = 1; i < MMU_PAGE_COUNT; i++) {
 417
 418                 /* invalid penc */
 419                 if (mmu_psize_defs[psize].penc[i] == -1)
 420                         continue;
 421                 /*
 422                  * encoding bits per actual page size
 423                  *        PTE LP     actual page size
 424                  *    rrrr rrrz         >=8KB
 425                  *    rrrr rrzz         >=16KB
 426                  *    rrrr rzzz         >=32KB
 427                  *    rrrr zzzz         >=64KB
 428                  * .......
 429                  */
 430                 shift = mmu_psize_defs[i].shift - LP_SHIFT;
 431                 if (shift > LP_BITS)
 432                         shift = LP_BITS;
 433                 mask = (1 << shift) - 1;
 434                 if ((lp & mask) == mmu_psize_defs[psize].penc[i])
 435                         return i;
 436         }
 437         return -1;
 438 }
 439
 440 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
 441                         int *psize, int *apsize, int *ssize, unsigned long *vpn)
 442 {
 443         unsigned long avpn, pteg, vpi;
 444         unsigned long hpte_v = hpte->v;
 445         unsigned long vsid, seg_off;
 446         int size, a_size, shift;
 447         /* Look at the 8 bit LP value */
 448         unsigned int lp = (hpte->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
 449
 450         if (!(hpte_v & HPTE_V_LARGE)) {
 451                 size   = MMU_PAGE_4K;
 452                 a_size = MMU_PAGE_4K;
 453         } else {
 454                 for (size = 0; size < MMU_PAGE_COUNT; size++) {
 455
 456                         /* valid entries have a shift value */
 457                         if (!mmu_psize_defs[size].shift)
 458                                 continue;
 459
 460                         a_size = __hpte_actual_psize(lp, size);
 461                         if (a_size != -1)
 462                                 break;
 463                 }
 464         }
 465         /* This works for all page sizes, and for 256M and 1T segments */
 466         *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
 467         shift = mmu_psize_defs[size].shift;
 468
 469         avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
 470         pteg = slot / HPTES_PER_GROUP;
 471         if (hpte_v & HPTE_V_SECONDARY)
 472                 pteg = ~pteg;
 473
 474         switch (*ssize) {
 475         case MMU_SEGSIZE_256M:
 476                 /* We only have 28 - 23 bits of seg_off in avpn */
 477                 seg_off = (avpn & 0x1f) << 23;
 478                 vsid    =  avpn >> 5;
 479                 /* We can find more bits from the pteg value */
 480                 if (shift < 23) {
 481                         vpi = (vsid ^ pteg) & htab_hash_mask;
 482                         seg_off |= vpi << shift;
 483                 }
 484                 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
 485         case MMU_SEGSIZE_1T:
 486                 /* We only have 40 - 23 bits of seg_off in avpn */
 487                 seg_off = (avpn & 0x1ffff) << 23;
 488                 vsid    = avpn >> 17;
 489                 if (shift < 23) {
 490                         vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
 491                         seg_off |= vpi << shift;
 492                 }
 493                 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
 494         default:
 495                 *vpn = size = 0;
 496         }
 497         *psize  = size;
 498         *apsize = a_size;
 499 }
 500
 501 /*
 502  * clear all mappings on kexec.  All cpus are in real mode (or they will
 503  * be when they isi), and we are the only one left.  We rely on our kernel
 504  * mapping being 0xC0's and the hardware ignoring those two real bits.
 505  *
 506  * TODO: add batching support when enabled.  remember, no dynamic memory here,
 507  * athough there is the control page available...
 508  */
 509 static void native_hpte_clear(void)
 510 {
 511         unsigned long vpn = 0;
 512         unsigned long slot, slots, flags;
 513         struct hash_pte *hptep = htab_address;
 514         unsigned long hpte_v;
 515         unsigned long pteg_count;
 516         int psize, apsize, ssize;
 517
 518         pteg_count = htab_hash_mask + 1;
 519
 520         local_irq_save(flags);
 521
 522         /* we take the tlbie lock and hold it.  Some hardware will
 523          * deadlock if we try to tlbie from two processors at once.
 524          */
 525         raw_spin_lock(&native_tlbie_lock);
 526
 527         slots = pteg_count * HPTES_PER_GROUP;
 528
 529         for (slot = 0; slot < slots; slot++, hptep++) {
 530                 /*
 531                  * we could lock the pte here, but we are the only cpu
 532                  * running,  right?  and for crash dump, we probably
 533                  * don't want to wait for a maybe bad cpu.
 534                  */
 535                 hpte_v = hptep->v;
 536
 537                 /*
 538                  * Call __tlbie() here rather than tlbie() since we
 539                  * already hold the native_tlbie_lock.
 540                  */
 541                 if (hpte_v & HPTE_V_VALID) {
 542                         hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
 543                         hptep->v = 0;
 544                         __tlbie(vpn, psize, apsize, ssize);
 545                 }
 546         }
 547
 548         asm volatile("eieio; tlbsync; ptesync":::"memory");
 549         raw_spin_unlock(&native_tlbie_lock);
 550         local_irq_restore(flags);
 551 }
 552
 553 /*
 554  * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
 555  * the lock all the time
 556  */
 557 static void native_flush_hash_range(unsigned long number, int local)
 558 {
 559         unsigned long vpn;
 560         unsigned long hash, index, hidx, shift, slot;
 561         struct hash_pte *hptep;
 562         unsigned long hpte_v;
 563         unsigned long want_v;
 564         unsigned long flags;
 565         real_pte_t pte;
 566         struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
 567         unsigned long psize = batch->psize;
 568         int ssize = batch->ssize;
 569         int i;
 570
 571         local_irq_save(flags);
 572
 573         for (i = 0; i < number; i++) {
 574                 vpn = batch->vpn[i];
 575                 pte = batch->pte[i];
 576
 577                 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
 578                         hash = hpt_hash(vpn, shift, ssize);
 579                         hidx = __rpte_to_hidx(pte, index);
 580                         if (hidx & _PTEIDX_SECONDARY)
 581                                 hash = ~hash;
 582                         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
 583                         slot += hidx & _PTEIDX_GROUP_IX;
 584                         hptep = htab_address + slot;
 585                         want_v = hpte_encode_avpn(vpn, psize, ssize);
 586                         native_lock_hpte(hptep);
 587                         hpte_v = hptep->v;
 588                         if (!HPTE_V_COMPARE(hpte_v, want_v) ||
 589                             !(hpte_v & HPTE_V_VALID))
 590                                 native_unlock_hpte(hptep);
 591                         else
 592                                 hptep->v = 0;
 593                 } pte_iterate_hashed_end();
 594         }
 595
 596         if (mmu_has_feature(MMU_FTR_TLBIEL) &&
 597             mmu_psize_defs[psize].tlbiel && local) {
 598                 asm volatile("ptesync":::"memory");
 599                 for (i = 0; i < number; i++) {
 600                         vpn = batch->vpn[i];
 601                         pte = batch->pte[i];
 602
 603                         pte_iterate_hashed_subpages(pte, psize,
 604                                                     vpn, index, shift) {
 605                                 __tlbiel(vpn, psize, psize, ssize);
 606                         } pte_iterate_hashed_end();
 607                 }
 608                 asm volatile("ptesync":::"memory");
 609         } else {
 610                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 611
 612                 if (lock_tlbie)
 613                         raw_spin_lock(&native_tlbie_lock);
 614
 615                 asm volatile("ptesync":::"memory");
 616                 for (i = 0; i < number; i++) {
 617                         vpn = batch->vpn[i];
 618                         pte = batch->pte[i];
 619
 620                         pte_iterate_hashed_subpages(pte, psize,
 621                                                     vpn, index, shift) {
 622                                 __tlbie(vpn, psize, psize, ssize);
 623                         } pte_iterate_hashed_end();
 624                 }
 625                 asm volatile("eieio; tlbsync; ptesync":::"memory");
 626
 627                 if (lock_tlbie)
 628                         raw_spin_unlock(&native_tlbie_lock);
 629         }
 630
 631         local_irq_restore(flags);
 632 }
 633
 634 void __init hpte_init_native(void)
 635 {
 636         ppc_md.hpte_invalidate  = native_hpte_invalidate;
 637         ppc_md.hpte_updatepp    = native_hpte_updatepp;
 638         ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp;
 639         ppc_md.hpte_insert      = native_hpte_insert;
 640         ppc_md.hpte_remove      = native_hpte_remove;
 641         ppc_md.hpte_clear_all   = native_hpte_clear;
 642         ppc_md.flush_hash_range = native_flush_hash_range;
 643 }